CN108666367A - Fin field effect pipe and forming method thereof - Google Patents
Fin field effect pipe and forming method thereof Download PDFInfo
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- CN108666367A CN108666367A CN201710198362.XA CN201710198362A CN108666367A CN 108666367 A CN108666367 A CN 108666367A CN 201710198362 A CN201710198362 A CN 201710198362A CN 108666367 A CN108666367 A CN 108666367A
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- separation layer
- field effect
- effect pipe
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- 238000000034 method Methods 0.000 title claims abstract description 72
- 230000005669 field effect Effects 0.000 title claims abstract description 68
- 239000010410 layer Substances 0.000 claims abstract description 341
- 238000000926 separation method Methods 0.000 claims abstract description 196
- 239000011241 protective layer Substances 0.000 claims abstract description 87
- 239000004065 semiconductor Substances 0.000 claims abstract description 58
- 239000000758 substrate Substances 0.000 claims abstract description 56
- 238000004140 cleaning Methods 0.000 claims abstract description 34
- 238000011049 filling Methods 0.000 claims abstract description 12
- 239000000463 material Substances 0.000 claims description 90
- 238000002955 isolation Methods 0.000 claims description 28
- 230000008569 process Effects 0.000 claims description 22
- 230000001681 protective effect Effects 0.000 claims description 19
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 11
- 229910000673 Indium arsenide Inorganic materials 0.000 claims description 7
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 claims description 7
- 238000005137 deposition process Methods 0.000 claims description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 10
- 239000000243 solution Substances 0.000 description 10
- 230000000694 effects Effects 0.000 description 9
- 230000015572 biosynthetic process Effects 0.000 description 8
- 238000005260 corrosion Methods 0.000 description 8
- 230000007797 corrosion Effects 0.000 description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 238000005516 engineering process Methods 0.000 description 7
- 229910052710 silicon Inorganic materials 0.000 description 7
- 239000010703 silicon Substances 0.000 description 7
- 229910052732 germanium Inorganic materials 0.000 description 6
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 5
- 229910010271 silicon carbide Inorganic materials 0.000 description 5
- 239000000377 silicon dioxide Substances 0.000 description 5
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 4
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 4
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 4
- 238000001312 dry etching Methods 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 229910052733 gallium Inorganic materials 0.000 description 4
- 229910052738 indium Inorganic materials 0.000 description 4
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 4
- 239000012212 insulator Substances 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 230000008901 benefit Effects 0.000 description 3
- 229910052681 coesite Inorganic materials 0.000 description 3
- 229910052906 cristobalite Inorganic materials 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 229910052682 stishovite Inorganic materials 0.000 description 3
- 229910052905 tridymite Inorganic materials 0.000 description 3
- 239000006117 anti-reflective coating Substances 0.000 description 2
- 239000006227 byproduct Substances 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 239000000047 product Substances 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 238000004904 shortening Methods 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 229910052582 BN Inorganic materials 0.000 description 1
- PZNSFCLAULLKQX-UHFFFAOYSA-N Boron nitride Chemical compound N#B PZNSFCLAULLKQX-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 238000004458 analytical method Methods 0.000 description 1
- 238000000231 atomic layer deposition Methods 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000010790 dilution Methods 0.000 description 1
- 239000012895 dilution Substances 0.000 description 1
- 238000004821 distillation Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000005086 pumping Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
- 239000002699 waste material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/7855—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with at least two independent gates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Abstract
A kind of fin field effect pipe of present invention offer and forming method thereof, the forming method includes：Semiconductor substrate is provided, there are multiple discrete fins in the semiconductor substrate；The first separation layer is formed in the semiconductor substrate that the fin exposes, first separation layer covers the partial sidewall of the fin, and less than at the top of the fin at the top of first separation layer；Protective layer is formed on the fin side wall that first separation layer exposes；The second separation layer is formed between the fin, second separation layer covers the top of first separation layer and the side wall of the protective layer；After forming second separation layer, the fin of the segment thickness or full depth between second separation layer is removed, forms opening；The opening is started the cleaning processing；After being started the cleaning processing to the opening, the channel layer of the full opening of filling is formed.The electric property for the fin field effect pipe that the present invention is formed is improved.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, more particularly to a kind of fin field effect pipe and forming method thereof.
Background technology
With the rapid development of semiconductor technology, the characteristic size of semiconductor devices constantly reduces.Features in semiconductor devices
More stringent requirements are proposed for performance of the reduction of size to semiconductor devices.
Currently, the size of Metal-Oxide Semiconductor field-effect transistor (MOSFET) constantly becomes smaller.In order to adapt to
The channel length of the reduction of process node, MOSFET field-effect tube is also being gradually shortened.The shortening of channel length, which has, increases core
The benefits such as the tube core density of piece, the switching speed for increasing MOSFET field-effect tube.
However, the shortening of channel length be easy to cause the problem of grid is deteriorated to channel controllability, to keep grid electric
It presses the difficulty of pinch off (pinch off) raceway groove also increasing, and then causes sub- threshold values leaky, that is, short-channel effect occur
(short-channel effects, SCE).
Therefore, in order to better adapt to the scaled requirement of device size, semiconductor technology is gradually from plane
Mosfet transistor is to three-dimensional transistor (such as fin field effect pipe) transition with more high effect.Fin field effect pipe
With good channel controllability, short-channel effect can be reduced.
Prior art fin field effect pipe has that electric property cannot meet semiconductor applications technology growth requirement.
Therefore, the electric property for how improving fin field effect pipe, the problem of becoming urgent need to resolve.
Invention content
Problems solved by the invention is to provide a kind of fin field effect pipe and forming method thereof, improves fin field effect pipe
Electric property.
To solve the above problems, the present invention provides a kind of forming method of fin field effect pipe, including：Semiconductor lining is provided
Bottom has multiple discrete fins in the semiconductor substrate；The fin expose semiconductor substrate on formed first every
Absciss layer, first separation layer covers the partial sidewall of the fin, and is less than the fin top at the top of first separation layer
Portion；Protective layer is formed on the fin side wall that first separation layer exposes；The second separation layer, institute are formed between the fin
It states the second separation layer and covers the top of first separation layer and the side wall of the protective layer；Forming second separation layer
Later, the fin of segment thickness or full depth of the removal between second separation layer forms opening, and the protection
Layer is located on the opening sidewalls；The opening is started the cleaning processing；After being started the cleaning processing to the opening, formation is filled out
Channel layer full of the opening, the material of the channel layer are different from the material of fin；After forming the channel layer, go
Except the second separation layer of segment thickness so that be higher than the channel layer bottom at the top of remaining second separation layer；Remove segment thickness
The second separation layer after, remove the protective layer that remaining second separation layer exposes.
Optionally, the step of forming the protective layer include：Protective film, and the guarantor are formed on first separation layer
The covering of cuticula guarantor's type is higher than the fin at the top of first separation layer；Removal is located at the top of first separation layer and fin top
The protective film in portion forms the protective layer.
Optionally, along being parallel to the semiconductor substrate surface and on fin extending direction, the protective layer
Thickness be：20 angstroms to 60 angstroms.
Optionally, the technique for forming the protective layer includes：Atom layer deposition process.
Optionally, include to the technique started the cleaning processing that is open：SiCoNi techniques.
Optionally, the step of forming the channel layer include：Channel epitaxial layer is formed in said opening, outside the raceway groove
Prolong at the top of layer higher than at the top of second separation layer；Planarization process is carried out to the channel epitaxial layer, removal is higher than described the
Channel epitaxial layer at the top of two separation layers forms the channel layer.
Optionally, the material of the channel layer is SiGe, Ge or InAs.
Optionally, the material hardness of the protective layer is more than the material hardness of first separation layer；The protective layer
Material hardness is more than the material hardness of second separation layer.
Optionally, the material of the protective layer includes one or more of SiN, SiBCN, SiOCN or SiCN.
Optionally, the step of formation second separation layer includes：The second isolation film for covering the fin is formed, it is described
Higher than at the top of the fin at the top of second isolation film；Planarization process is carried out to second isolation film, is exposed at the top of fin, shape
At second separation layer.
Optionally, along the direction perpendicular to semiconductor substrate surface, the height of the channel layer is：5nm to 8nm.
Optionally, in the step of removing the second separation layer of segment thickness, the thickness of second separation layer is removed 300
Angstrom within the scope of 700 angstroms.
Optionally, the technique of the protective layer of the remaining second separation layer exposing of removal includes：Dry etch process.
Optionally, the semiconductor substrate includes being used to form the first area of NMOS device and being used to form PMOS device
Second area.
Optionally, the channel layer is located at the first area；The processing step for forming the opening includes：Described
Graph layer is formed on second separation layer in one region, the graph layer also covers at the top of the fin of first area；With the figure
Layer is mask, and the fin of segment thickness or full depth of the removal between the second separation layer of the second area is formed
The opening.
Correspondingly, the present invention also provides a kind of fin field effect pipes, including：Semiconductor substrate, in the semiconductor substrate
With multiple discrete fins；The first separation layer in the semiconductor substrate that the fin exposes, first separation layer
The side wall of the fin is covered, and less than at the top of the fin at the top of first separation layer；On at the top of the fin
Channel layer, and the material of the channel layer is different from the material of the fin；The second isolation on first separation layer
Layer, second separation layer covers the partial sidewall of the channel layer, and is higher than the channel layer at the top of second separation layer
Bottom；Protective layer between second separation layer and the channel layer side wall.
Optionally, the material hardness of the protective layer is more than the material hardness of first separation layer；The protective layer
Material hardness is more than the material hardness of second separation layer.
Optionally, the material of the channel layer includes：SiGe, Ge or InAs.
Optionally, along the direction perpendicular to semiconductor substrate surface, the height of the channel layer is：5nm to 8nm.
Optionally, the material of the protective layer includes one or more of SiN, SiBCN, SiOCN or SiCN.
Compared with prior art, technical scheme of the present invention has the following advantages：
First after the step of forming protective layer on the fin that the first separation layer exposes, form the protective layer, formation is filled out
Channel layer full of the opening, the material of the channel layer are different from the material of fin.The step of forming the opening it
Afterwards, before the step of forming the channel layer, the opening can be started the cleaning processing, the present invention in the first separation layer due to revealing
Protective layer is formed on the fin gone out so that the protective layer pair second separation layer during cleaning treatment generates protection, improves
The influence of the second washed solution corrosion of separation layer side wall, the problem of increase so as to avoid the opening size.Therefore,
After being started the cleaning processing to the opening, form the channel layer of the full opening of filling, the size of the channel layer with it is described
The size of opening is identical.Technical scheme of the present invention improves the problem of channel layer size increases, so as to improve fin
The electric property of field-effect tube.
In optional technical solution, along being parallel to the semiconductor substrate surface and on fin extending direction,
The thickness of the protective layer is 20 angstroms to 60 angstroms.If the thickness of the protective layer is too small, carried out at cleaning to the opening
During reason, the protective effect of the second separation layer of the protective layer pair is poor；If the thickness of the opening is excessive, after making
The technology difficulty of the continuous removal protective layer is big.Therefore, the thickness range of protective layer of the present invention is 20 angstroms to 60 angstroms so that
Foregoing problems are eased, to further improve the electric property of fin field effect pipe.
Description of the drawings
Fig. 1 to Fig. 9 is a kind of corresponding structural schematic diagram of each step of fin field effect pipe forming method；
Figure 10 to Figure 22 is the corresponding structural schematic diagram of one each step of embodiment forming method of fin field effect pipe of the present invention.
Specific implementation mode
Electric property according to the fin field effect pipe of background technology formation is to be improved.In conjunction with a kind of fin field effect
The forming method of pipe analyzes its electric property reason to be improved.
Referring to figs. 1 to Fig. 9, a kind of corresponding structural schematic diagram of each step of fin field effect pipe forming method is shown.
With reference to figure 1, semiconductor substrate 100 is provided, there is multiple discrete fins 110, institute in the semiconductor substrate 100
Stating on 110 top of fin has hard mask 111；The semiconductor substrate 100 includes being used to form the first area I of NMOS device
With the second area II for being used to form PMOS device.
With reference to figure 2, separation layer 120, the separation layer 120 are formed in the semiconductor substrate 100 that the fin 110 exposes
Top is flushed with 111 top of the hard mask.
With reference to figure 3, the separation layer 120 of segment thickness is removed, exposes 110 top of fin, in removal segment thickness separation layer
Removal is located at the hard mask 111 on 110 top of fin during 120 (with reference to figure 2).
With reference to figure 4, graph layer 131, the graph layer 131 are formed at 120 top of the separation layer positioned at first area I
Also covering is positioned at 110 top of fin of first area I.
It is mask with the graph layer 131 with reference to figure 5, part of the removal between the separation layer 120 of second area II
The fin 110 of thickness forms opening 140.
It with reference to figure 6, is formed after the opening 140, the opening 140 is started the cleaning processing.
With reference to figure 7, the channel epitaxial layer 150 for filling the opening 140 is formed, 150 top of the channel epitaxial layer is higher than
120 top of the separation layer.
With reference to figure 8, planarization process is carried out to the channel epitaxial layer 150, removal is higher than 120 top of the separation layer
Channel epitaxial layer 150 forms channel layer 151；The figure is removed during channel epitaxial layer 150 described in planarization process
131 (with reference to figure 7) of layer.
With reference to figure 9, the separation layer 120 of segment thickness is removed, and 120 top of remaining separation layer is made to be higher than the channel layer
151 bottoms.
The electric property for the fin field effect pipe that above-mentioned forming method is formed is to be improved.
It is found through analysis, the reason for causing the electric property of fin field effect pipe to be improved includes：Form the opening
After 140, to it is described opening 140 start the cleaning processing the step of in, since the hardness of 120 material of the separation layer is smaller, hold
It is vulnerable to the corrosion of cleaning solution, to cause the problem of the becoming large-sized of 140 (in conjunction with reference to figure 5 and Fig. 6) of opening.Phase
It answers, since the opening 140 provides Process ba- sis to be subsequently formed the channel layer 151, so as to cause being formed described in filling
The size of the channel layer 151 of opening 140 also can be larger, therefore reduces the electric property of fin field effect pipe.
In order to solve the above technical problem, the present invention provides a kind of forming methods of fin field effect pipe, including：There is provided half
Conductor substrate has multiple discrete fins in the semiconductor substrate；It is formed in the semiconductor substrate that the fin exposes
First separation layer, first separation layer cover the partial sidewall of the fin, and less than described at the top of first separation layer
At the top of fin；Protective layer is formed on the fin side wall that first separation layer exposes；Between the fin formed second every
Absciss layer, second separation layer cover the top of first separation layer and the side wall of the protective layer；Forming described the
After two separation layers, the fin of the segment thickness or full depth between second separation layer is removed, forms opening, and
The protective layer is located on the opening sidewalls；The opening is started the cleaning processing；It is started the cleaning processing to the opening
Afterwards, the channel layer of the full opening of filling is formed, the material of the channel layer is different from the material of fin；Forming the raceway groove
After layer, the second separation layer of segment thickness is removed so that be higher than the channel layer bottom at the top of remaining second separation layer；Removal
After second separation layer of segment thickness, the protective layer that remaining second separation layer exposes is removed.
Since before the step of forming the opening, protective layer is formed on the fin that the first separation layer exposes so that
The protective layer pair second separation layer during cleaning treatment generates protective effect, improves the second separation layer side wall by clear
The influence of dilution corrosion, the problem of increase so as to avoid the opening size.
After being started the cleaning processing to the opening, the channel layer of the full opening of filling, the ruler of the channel layer are formed
It is very little identical as the size of the opening that is being formed, due to having protective layer on the side wall of the opening, carried out to the opening
During cleaning, the size of the opening will not increase because of the corrosion of cleaning solution, correspondingly, the channel layer formed
Size is also maintained constant.For not forming the technical solution of protective layer, this programme solves the size of channel layer
The problem of becoming larger, to improve the electric property of fin field effect pipe.
To make the above purposes, features and advantages of the invention more obvious and understandable, below in conjunction with the accompanying drawings to the present invention
Specific embodiment be described in detail.
Figure 10 to Figure 22 is the corresponding structural schematic diagram of one each step of embodiment forming method of fin field effect pipe of the present invention.
With reference to figure 10, semiconductor substrate 200 is provided, there are multiple discrete fins 210 in the semiconductor substrate 200.
In the present embodiment, the semiconductor substrate 200 includes being used to form the first area I of NMOS device and being used to form
The second area II of PMOS device, correspondingly, the fin field effect pipe formed is cmos device.In other embodiments of the invention
In, the semiconductor substrate can only include the first area for being used to form NMOS device or be used to form PMOS device the
One kind in two regions, correspondingly, the fin field effect pipe formed is NMOS device or PMOS device.
In the present embodiment, the material of the semiconductor substrate 200 is silicon.In other embodiments of the present invention, described partly to lead
The material of body substrate can also be germanium, SiGe, silicon carbide, GaAs or gallium indium.In other embodiments, the semiconductor
Substrate can also be the germanium substrate on silicon substrate or insulator on insulator.
In the present embodiment, the material of the fin 210 is silicon.In other embodiments of the present invention, the material of the fin
Can also be germanium, SiGe, silicon carbide, GaAs or gallium indium.
In the present embodiment, the fin field effect pipe further includes：Hard mask 211 on 210 top of the fin.Institute
Hard mask 211 is stated for playing the role of protection 210 top of fin in the technique for being subsequently formed the first separation layer.
In the present embodiment, the material of the hard mask 211 is silicon nitride；In other embodiments of the present invention, described to cover firmly
The material of film can also be silicon oxynitride, silicon carbide or boron nitride.
In conjunction with reference to figure 11 and Figure 12, the first separation layer is formed in the semiconductor substrate 200 that the fin 210 exposes
221 (as shown in figure 12), first separation layer 221 cover the partial sidewall of the fin 210, and first separation layer
221 tops are less than 210 top of the fin.
With reference to figure 11, initial first isolation film is formed in the semiconductor substrate 200 that the fin 210 exposes, it is described first
Begin to be higher than 210 top of the fin at the top of the first isolation film；To carrying out planarization process, dew at the top of initial first isolation film
Go out 211 top of the hard mask, forms the first isolation film 220.
First isolation film 220 provides Process ba- sis to be subsequently formed the first separation layer.
In the present embodiment, the material of first isolation film 220 is SiO2。
With reference to figure 12 removal portion is etched back to after carrying out planarization process to first isolation film 220 (with reference to figure 11)
Divide first isolation film 220 of thickness, form the first separation layer 221, first separation layer 221 covers the fin 210
Partial sidewall, and the top of first separation layer 221 is less than 210 top of the fin.
First separation layer 221 can play the role of the adjacent fin of electric isolation 210.
In the present embodiment, the material of first separation layer 221 is SiO2。
The technique of first isolation film 220 for being etched back to removal segment thickness includes：Dry etching or wet etching.
In the present embodiment, the technique for being etched back to first isolation film 220 of removal segment thickness is dry etching.
In conjunction with reference to figure 13 and Figure 14, protective layer is formed on 210 side wall of fin that first separation layer 221 exposes
231。
The step of below with reference to attached drawing to forming protective layer 231, elaborates.
With reference to figure 13, protective film 230 is formed on first separation layer 221, and the covering of 230 guarantor's type of the protective film is high
Fin 210 in first separation layer, 221 top.
The protective film 230 provides Process ba- sis to form protective layer in subsequent technique.
In the present embodiment, the material of the protective film 230 is SiN；In other embodiments of the present invention, the protective film
230 material can also be one or more of SiBCN, SiOCN or SiCN.
The technique for forming the protective film 230 includes：Physical vapour deposition (PVD), chemical vapor deposition or atomic layer deposition.
In the present embodiment, the protective film 230 is formed using atom layer deposition process so that the deposition effect of the protective film 230 obtains
To raising.Correspondingly, the quality for the protective layer 230 being subsequently formed also gets a promotion.
With reference to figure 14, removal is located at the protective film 230 at 210 top of first separation layer, 221 top and fin, is formed
Protective layer 231.
The effect of the protective layer 231 is to protect second be subsequently formed in the step of subsequently being cleaned to opening
Separation layer avoids or reduces the corrosion impact of the washed solution of the second separation layer, to cause the opening to increase
The problem of.Correspondingly, after due to being started the cleaning processing to the opening, the channel layer of the full opening of filling is formed, it is described
The size of channel layer is identical as the size of the opening, and therefore, the protective layer 231 improves the channel layer size being subsequently formed
The problem of increase, to improve the electric property of fin field effect pipe.
In order to make the protective effect of the protective layer 231 preferably play, the material of the protective layer 231 using hardness compared with
Greatly and it is not easy the material easily corroded by cleaning.Due to the material of first separation layer 221 and the second separation layer being subsequently formed
Expect that hardness is smaller, is vulnerable to the influence of cleaning solution corrosion, therefore the material of the protective layer 231 uses and first separation layer
221 different materials, and the material of the protective layer 231 is also different from the material for the second separation layer being subsequently formed.
The material hardness of the protective layer 231 is more than the material hardness of first separation layer 221, the protective layer 231
Material hardness be also greater than the material hardness of the second separation layer being subsequently formed.Therefore, in the present embodiment, the protective layer 231
Material using the larger SiN of hardness；In other embodiments of the present invention, the material of the protective layer can also be SiBCN,
One or more of SiOCN or SiCN.
It should be noted that the protective layer 231 is parallel to 200 surface of the semiconductor substrate and perpendicular to fin on edge
Thickness on 210 extending directions can neither it is excessive can not be too small.If the thickness of the protective layer 231 is too small, subsequently right
During the opening starts the cleaning processing, the protective layer 231 to the protective effect of the second separation layer being subsequently formed compared with
Difference, or even cannot play the role of that the second separation layer is prevented to be cleaned solution corrosion；If the thickness of the protective layer 231 is excessive,
It can then make the technology difficulty for subsequently removing the protective layer 231 larger, and will also result in the waste of process materials.Therefore, originally
In embodiment, along being parallel to 200 surface of the semiconductor substrate and on 210 extending direction of fin, the protective layer
231 thickness is within the scope of 20 angstroms to 60 angstroms.
With reference to figure 15, the second separation layer 240 is formed between the fin 210, second separation layer 240 covers described
The top of first separation layer 221 and the side wall of the protective layer 231.
Second separation layer 240 and first separation layer 221 play the role of the adjacent fin of electric isolation 210；
And second separation layer 240 can also provide technique base to be subsequently formed the channel layer of opening and the full opening of filling
Plinth.
In the present embodiment, the material of second separation layer 240 is SiO2.The step of forming the second separation layer 240
Including：The second isolation film is formed on the first separation layer 221 that the fin 210 exposes, and is higher than at the top of second isolation film
210 top of the fin；It is formed after second isolation film, to carrying out planarization process at the top of second isolation film, directly
To 210 top of the fin is exposed, second separation layer 240 is formed, second separation layer 240 covers first isolation
221 top of layer and the side wall of the protective layer 231.
In conjunction with referring to figures 16 to Figure 18, after forming second separation layer 240, removal is located at second separation layer
The fin 210 of segment thickness between 240 forms opening 260, and the protective layer 231 is located on 260 side walls of the opening；
The opening 260 is started the cleaning processing.
The step of starting the cleaning processing below with reference to the attached drawing opening 260 described to formation and to the opening 260 is done
Detailed description.
With reference to figure 16, graphic films 250 are formed on second separation layer 240, the graphic films 250 cover fin 210
Top.
The graphic films 250 is are subsequently formed the Process ba- sis that graph layer provides graphical treatment.
In the present embodiment, the material of the graphic films 250 is SiN.In other embodiments of the present invention, the graphic films
Material can also be photoresist, bottom antireflective coating or reflection coating provided.
With reference to figure 17, processing is patterned to the graphic films 250, in the second separation layer 240 of the first area I
Upper formation graph layer 251, the graph layer 251 also cover 210 top of fin of first area I.
The graph layer 251 makes as the mask for being subsequently formed opening for protecting the fin 210 positioned at first area I
It obtains in the step of forming the opening, only removal is located at the segment thickness between the second separation layer 240 of second area II
Fin 210, to form the opening in second area II.
In the present embodiment, the step of being patterned processing to the graphic films 250, includes：On the graphic films 250
Form patterned photoresist layer；Using the patterned photoresist layer as graphic films 250 described in mask etching, described first
Graph layer 251 is formed on the second separation layer 240 of region I.
In the present embodiment, the material of the graph layer 251 is SiN.In other embodiments of the present invention, the graph layer
251 material can also be photoresist, bottom antireflective coating or reflection coating provided.
It is mask with the graph layer 251 with reference to figure 18, second separation layer 240 of the removal positioned at the second area II
Between segment thickness fin 210, formed opening 260；It is formed after opening 260, the opening 260 is carried out at cleaning
Reason.
The channel layer that the opening 260 expires the opening 260 to be subsequently formed filling provides spatial position so that follow-up shape
At the channel layer size with it is described opening 260 size it is consistent.
Be mask with the graph layer 251 in the present embodiment, due to only remove positioned at the second area II second every
The fin 210 of segment thickness between absciss layer 240, therefore 260 bottom of the opening formed is higher than first separation layer 221
Top, and form matcoveredn 231 on the side wall of the opening 260.It in other embodiments of the present invention, can also be with the figure
Shape layer is mask, the fin of full depth of the removal between the second separation layer of the second area so that the opening
It is flushed at the top of bottom and first separation layer, and matcoveredn is formed on the side wall of the opening.
The opening 260 is started the cleaning processing so that the cleannes of the opening 260 are improved, so as to improve
It is subsequently formed the quality of channel layer.Due to forming matcoveredn 231 on the side wall of the opening 260, the protective layer 231 is right
The opening 260 has protective effect so that and the opening 260 is not readily susceptible to the influence of cleaning solution, so that by
The size of the opening 260 is maintained constant after cleaning treatment.
In the present embodiment, the technique started the cleaning processing to the opening 260 includes：SiCoNi techniques.Specifically, described
The step of SiCoNi etching technics includes：With NF3And NH3Mixed gas as etching gas；Pass through the etching gas and position
Impurity reaction in the opening 260, forms by-product；By-product distillation is decomposed into gaseous products；Pass through pumping
Mode removes the gaseous products.
In conjunction with reference to figure 19 and Figure 20, after being started the cleaning processing to the opening 260, the full opening of filling is formed
The material of 260 channel layer 271, the channel layer 271 is different from the material of fin 210.
With reference to figure 19, channel epitaxial layer 270 is formed in the opening 260,270 top of the channel epitaxial layer is higher than institute
State 240 top of the second separation layer.
The channel epitaxial layer 270 provides Process ba- sis to be subsequently formed channel layer.
In the present embodiment, the channel epitaxial layer 270 is formed using selective epitaxial growth process.The channel epitaxial layer
270 material is SiGe.In other embodiments of the present invention, the material of the channel epitaxial layer can also be Ge or InAs.
With reference to figure 20, planarization process is carried out to the channel epitaxial layer 270 (with reference to figure 19), removal is higher than described second
The channel epitaxial layer 270 at 240 top of separation layer, forms channel layer 271.
In the present embodiment, protective layer 231 is also formed on the side wall of the channel layer 271.Since the channel layer 271 is
Formed on the basis of the filling full opening 260 (with reference to figure 18), correspondingly, the size of the channel layer 271 with it is described
The size of opening 260 is identical.In the present embodiment, after the step of forming the opening 260, the channel layer 271 is being formed
The step of before, the opening 260 can be started the cleaning processing, to improve the cleannes of the opening 260, so that described
The quality of channel epitaxial layer 270 is improved, and then improves the quality of the channel layer 271.
It should be noted that in the step of being cleaned to the opening 260, due to the side wall in the opening 260
Upper formation matcoveredn 231, the protective layer 231 can protect second separation layer 240, avoid the second separation layer 240
The influence of washed solution corrosion increases to avoid the problem that or reduce 260 sizes of the opening, also keeps away accordingly
Exempt from or reduce the problem of 271 size of the channel layer increases, and then improves the electric property of fin field effect pipe.
The channel layer 271 can improve the carrier mobility of fin field effect pipe, so as to improve fin field effect pipe
Electric property.Therefore, in the present embodiment, the material selection of the channel layer 271 can improve the SiGe of carrier mobility
Material.In other embodiments of the present invention, the material of the channel layer can also be Ge or InAs.
Along on the direction on 200 surface of semiconductor substrate, the height of the channel layer 271 can neither it is excessive not yet
It can be too small.If the height of the channel layer 271 is excessive, the short-channel effect of fin field effect pipe can be caused more serious；If
The height of the channel layer 271 is too small, then is not easy to meet the technique manufacture demand of fin field effect pipe in the subsequent process.Cause
This, in the present embodiment, along on the direction on 200 surface of semiconductor substrate, the height of the channel layer 271 be 5nm extremely
8nm。
The second separation layer 240 of segment thickness is removed after forming the channel layer 271 so that remaining with reference to figure 21
Second separation layer, 240 top is higher than 271 bottom of the channel layer.
Remaining second separation layer 240 and first separation layer 221 can play the work of the adjacent fin of electric isolation 210
With.
In the step of removing the second separation layer 240 of segment thickness, the thickness for removing second separation layer 240 can neither
It is excessive can not be too small.If the thickness for removing second separation layer 240 is excessive, it can make remaining second separation layer 240
Isolation effect is poor；If the thickness for removing second separation layer 240 is too small, remaining second separation layer 240 can be made to expose
The height of the channel layer 271 is too small, is not easy to meet fin field effect so as to cause the channel layer 271 in the subsequent process
The technique of pipe manufactures demand.Therefore, in the present embodiment, in the step of removing the second separation layer 240 of segment thickness, described in removal
The thickness of second separation layer 240 is within the scope of 300 angstroms to 700 angstroms.
With reference to figure 22, after the second separation layer 240 for removing segment thickness, remove what remaining second separation layer 240 exposed
Protective layer 231.
The technique for the protective layer 231 that remaining second separation layer 240 of removal exposes includes wet etching, dry etching or ash
Chemical industry skill.In the present embodiment, the technique for removing the protective layer 231 that remaining second separation layer 240 exposes is dry etching.
Correspondingly, the present invention also provides a kind of fin field effect pipes shows fin field effect pipe of the present invention with reference to figure 22
The structural schematic diagram of one embodiment.The fin field effect pipe includes：Semiconductor substrate 200 has in the semiconductor substrate 200
There are multiple discrete fins 210；The first separation layer 221 in the semiconductor substrate 200 that the fin 210 exposes, it is described
First separation layer 221 covers the side wall of the fin 210, and first separation layer, 221 top is low with 210 top of the fin
In 210 top of the fin；Channel layer 271 on 210 top of the fin, and the material of the channel layer 271 and institute
The material for stating fin 210 is different；The second separation layer 240 on first separation layer 221, second separation layer 240
The partial sidewall of the channel layer 271 is covered, and second separation layer, 240 top is higher than 271 bottom of the channel layer；It is located at
Protective layer 231 between 271 side wall of second separation layer 240 and the channel layer.
In the present embodiment, the semiconductor substrate 200 includes having the first area I of NMOS device and with PMOS device
Second area II, correspondingly, formed fin field effect pipe be cmos device.In other embodiments of the present invention, described half
Conductor substrate can only include the one kind having in the first area of NMOS device or the second area with PMOS device, phase
It answers, the fin field effect pipe of formation is NMOS device or PMOS device.
In the present embodiment, the material of the semiconductor substrate 200 is silicon.In other embodiments of the present invention, described partly to lead
The material of body substrate can also be germanium, SiGe, silicon carbide, GaAs or gallium indium.In other embodiments, the semiconductor
Substrate can also be the germanium substrate on silicon substrate or insulator on insulator.
In the present embodiment, the material of the fin 210 is silicon.In other embodiments of the present invention, the material of the fin
Can also be germanium, SiGe, silicon carbide, GaAs or gallium indium.
First separation layer 221 can play the role of the adjacent fin of electric isolation 210.In the present embodiment, described
The material of one separation layer 221 is silica.
In the present embodiment, first separation layer, 221 top is less than 210 top of the fin.In other implementations of the present invention
In example, it can also be flushed with fin top at the top of first separation layer.
In the present embodiment, there is protective layer between 271 side wall of second separation layer 240 and the channel layer
231, the protective layer 231 is for protecting second separation layer 240.In the present embodiment, the material hardness of the protective layer 231
More than the material hardness of first separation layer 221；The material hardness of the protective layer 231 is also greater than second separation layer
240 material hardness.Specifically, the material of the protective layer 231 is using the big SiN of hardness；In other embodiments of the present invention,
The material of the protective layer can also be one or more of SiBCN, SiOCN or SiCN.
Second separation layer 240 and first separation layer 221 play the role of the adjacent fin of electric isolation 210.
In the present embodiment, the material of second separation layer 240 is silica.
The channel layer 271 can improve the carrier mobility of fin field effect pipe, so as to improve fin field effect pipe
Electric property.Therefore, in the present embodiment, the material selection of the channel layer 271 can improve the SiGe of carrier mobility
Material.In other embodiments of the present invention, the material of the channel layer can also be Ge or InAs.
Along on the direction on 200 surface of semiconductor substrate, the height of the channel layer 271 can neither it is excessive not yet
It can be too small.If the height of the channel layer 271 is excessive, the short-channel effect of fin field effect pipe can be caused more serious；If
The height of the channel layer 271 is too small, then is not easy to meet the technique manufacture demand of fin field effect pipe.Therefore, the present embodiment
In, along on the direction on 200 surface of semiconductor substrate, the height of the channel layer 271 is 5nm to 8nm.
Although present disclosure is as above, present invention is not limited to this.Any those skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the range of restriction.
Claims (20)
1. a kind of forming method of fin field effect pipe, which is characterized in that including：
Semiconductor substrate is provided, there are multiple discrete fins in the semiconductor substrate；
The first separation layer is formed in the semiconductor substrate that the fin exposes, first separation layer covers the portion of the fin
Divide side wall, and less than at the top of the fin at the top of first separation layer；
Protective layer is formed on the fin side wall that first separation layer exposes；
The second separation layer is formed between the fin, second separation layer covers top and the institute of first separation layer
State the side wall of protective layer；
After forming second separation layer, segment thickness or full depth of the removal between second separation layer
Fin forms opening, and the protective layer is located on the opening sidewalls；
The opening is started the cleaning processing；
After being started the cleaning processing to the opening, form the channel layer of the full opening of filling, the material of the channel layer with
The material of fin is different；
After forming the channel layer, the second separation layer of segment thickness is removed so that be higher than at the top of remaining second separation layer
The channel layer bottom；
After the second separation layer for removing segment thickness, the protective layer that remaining second separation layer exposes is removed.
2. the forming method of fin field effect pipe as described in claim 1, which is characterized in that the step of forming the protective layer
Including：
Protective film is formed on first separation layer, and protective film guarantor type covering is higher than at the top of first separation layer
Fin；
Removal is located at the protective film at the top of first separation layer and at the top of fin, forms the protective layer.
3. the forming method of fin field effect pipe as described in claim 1, which is characterized in that be parallel to the semiconductor on edge
Substrate surface and on fin extending direction, the thickness of the protective layer is：20 angstroms to 60 angstroms.
4. the forming method of fin field effect pipe as described in claim 1, which is characterized in that the technique for forming the protective layer
Including：Atom layer deposition process.
5. the forming method of fin field effect pipe as described in claim 1, which is characterized in that carried out at cleaning to the opening
The technique of reason includes：SiCoNi techniques.
6. the forming method of fin field effect pipe as described in claim 1, which is characterized in that the step of forming the channel layer
Including：
Channel epitaxial layer is formed in said opening, is higher than at the top of second separation layer at the top of the channel epitaxial layer；
Planarization process is carried out to the channel epitaxial layer, removal is higher than the channel epitaxial layer at the top of second separation layer, shape
At the channel layer.
7. the forming method of fin field effect pipe as described in claim 1, which is characterized in that the material of the channel layer is
SiGe, Ge or InAs.
8. the forming method of fin field effect pipe as described in claim 1, which is characterized in that the material hardness of the protective layer
More than the material hardness of first separation layer；The material that the material hardness of the protective layer is more than second separation layer is hard
Degree.
9. the forming method of fin field effect pipe as claimed in claim 8, which is characterized in that the material of the protective layer includes
One or more of SiN, SiBCN, SiOCN or SiCN.
10. the forming method of fin field effect pipe as described in claim 1, which is characterized in that form second separation layer
The step of include：
The second isolation film for covering the fin is formed, is higher than at the top of the fin at the top of second isolation film；
Planarization process is carried out to second isolation film, is exposed at the top of fin, second separation layer is formed.
11. the forming method of fin field effect pipe as described in claim 1, which is characterized in that served as a contrast along perpendicular to semiconductor
On the direction of bottom surface, the height of the channel layer is：5nm to 8nm.
12. the forming method of fin field effect pipe as described in claim 1, which is characterized in that remove the second of segment thickness
In the step of separation layer, the thickness of second separation layer is removed within the scope of 300 angstroms to 700 angstroms.
13. the forming method of fin field effect pipe as described in claim 1, which is characterized in that remaining second separation layer of removal
The technique of the protective layer of exposing includes：Dry etch process.
14. the forming method of fin field effect pipe as described in claim 1, which is characterized in that the semiconductor substrate includes
It is used to form the first area of NMOS device and is used to form the second area of PMOS device.
15. the forming method of fin field effect pipe as claimed in claim 14, which is characterized in that the channel layer is located at described
First area；The processing step for forming the opening includes：
Graph layer is formed on the second separation layer of the first area, the graph layer also covers the fin top of first area
Portion；
Using the graph layer as mask, segment thickness or all thick of the removal between the second separation layer of the second area
The fin of degree forms the opening.
16. a kind of fin field effect pipe, which is characterized in that including：
Semiconductor substrate has multiple discrete fins in the semiconductor substrate；
Expose the first separation layer in semiconductor substrate positioned at the fin, first separation layer covers the side of the fin
Wall, and less than at the top of the fin at the top of first separation layer；
Channel layer at the top of the fin, and the material of the channel layer is different from the material of the fin；
The second separation layer on first separation layer, second separation layer cover the partial sidewall of the channel layer,
And it is higher than the channel layer bottom at the top of second separation layer；
Protective layer between second separation layer and the channel layer side wall.
17. fin field effect pipe as claimed in claim 16, which is characterized in that the material hardness of the protective layer is more than described
The material hardness of first separation layer；The material hardness of the protective layer is more than the material hardness of second separation layer.
18. fin field effect pipe as claimed in claim 16, which is characterized in that the material of the channel layer includes：SiGe、Ge
Or InAs.
19. fin field effect pipe as claimed in claim 16, which is characterized in that along perpendicular to the side of semiconductor substrate surface
Upwards, the height of the channel layer is：5nm to 8nm.
20. fin field effect pipe as claimed in claim 16, which is characterized in that the material of the protective layer include SiN,
One or more of SiBCN, SiOCN or SiCN.
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| US20080124893A1 (en) * | 2006-07-03 | 2008-05-29 | Samsung Electronics Co., Ltd. | Method of manufacturing a semiconductor device |
| US9257344B2 (en) * | 2009-12-03 | 2016-02-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFETs with different fin height and EPI height setting |
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