CN108666361B - Through hole alignment-free power device and manufacturing method thereof - Google Patents
Through hole alignment-free power device and manufacturing method thereof Download PDFInfo
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Abstract
The invention is suitable for the field of semiconductors, and provides a through hole alignment-free power device and a preparation method thereof, wherein the device comprises a substrate, an epitaxial layer and a deep groove structure arranged on the epitaxial layer, wherein the deep groove structure sequentially comprises an insulating layer and a grid electrode from outside to inside, the insulating layer forms a hopper-shaped structure with the angle less than 60 degrees along the direction of the deep groove by oxidation of the deep groove structure, and the top of the deep groove structure is covered with an oxide layer; a source electrode and a channel are formed on the epitaxial layer outside the deep groove structure through ion implantation; and a through hole formed by etching the oxide layer, the through hole connecting the source electrode and the channel to form ohmic contact. The insulating layer of the power device is in a bucket-shaped structure along the direction of the deep groove through oxidation, so that the limitation of minimum photoetching line width and alignment precision during through hole etching is avoided, the density of the device is increased, and the on-resistance of the power device is reduced.
Description
Technical Field
The invention belongs to the field of semiconductors, and particularly relates to a through hole alignment-free power device and a manufacturing method thereof.
Background
Power semiconductors are semiconductor products that perform electric energy (power) processing, play an important role in controlling the transition between strong electricity and weak points, and have been popular and paid attention by engineers since birth. Over the years of development, the use of power semiconductors in associated power supply circuits has not been an alternative.
Fig. 1 shows a structure of a conventional N-type power MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), wherein 1 is a highly doped substrate, the doping concentration of which is usually above 1e19, and the resistivity of which is usually between 0.5m Ω/cm and 5m Ω/cm; 2, an epitaxial layer is arranged on the substrate 1, the breakdown voltage of the device mainly depends on the thickness of the epitaxial layer and the doping concentration of the epitaxial layer, for a device with the breakdown voltage of 100V, the thickness of the epitaxial layer is generally required to be more than 8 μm, the higher the breakdown voltage of the device is, the lower the doping concentration of the corresponding epitaxial layer is, and the thicker the epitaxial layer is; 3 is a Gate Oxide layer (Gate Oxide), the thickness of which affects the threshold voltage of the device and the breakdown voltage of its Gate; 4 is polysilicon for forming a gate; 5 is a P-type channel (Pbody), the doping concentration of which determines the threshold voltage of the device and can reduce the conduction of a parasitic triode of the device by increasing the doping concentration of the P-type channel; 6 is a source of N-type; and 7 is a through hole for connecting the source electrode 6 and the P-type channel 5. The source electrode 6 is connected with the heavily doped P-type channel 5 through the side wall of the through hole 7 to form ohmic contact. In order to ensure a better ohmic Contact between the via 7 and the P-type channel 5, a CT implantation (Contact implantation, highly doped P-type implantation) is usually performed, wherein the implantation dose is usually above 1e15 and the energy is usually between 40-60 keV.
In order to meet the design requirement of high-current power devices, the on-resistance of the devices is required to be continuously reduced, and as can be seen from fig. 1, the on-resistance of the power MOSFET is represented by Rsub、RdriftAnd RchComposition, R for different breakdown voltagessub、RdriftAnd RchThe design ratio of (a) is also different. In low voltage devices, e.g. devices with breakdown voltages less than 80V, the channel resistance RchThe proportion of the total resistance is more than 20%, and even more than 40%. Therefore, the channel resistance R is reduced under the condition that the breakdown voltage of the device is relatively lowchThis is particularly critical to reducing the on-resistance of the device.
At present, the channel resistance R is generally reduced by increasing the density of the devicechWhile increasing device density requires a reduction in via WMI.e. reduce the width of fig. 1
Width of (W) ofMThe width of (a) means that the width of Mesa includes the width of the via hole, and in order to take certain process variations into consideration, the via hole needs to be spaced apart from the gate oxide layer 3 by a certain distance to prevent the via hole from being connected to the gate. The process deviation includes the process deviation of the gate and the process deviation of the through hole. In addition, the via hole needs to have a minimum distance from the gate, and the minimum distance is because the via hole has a high-concentration P-type implantation, which has a certain width, and if the via hole is too close to the gate, the doping concentration of the P-type impurity in communication is increased, so that the threshold voltage is influenced, and the threshold voltage is increased.
However, in the prior art design, the width of the via is usually determined by the width of the photolithography plate, and the width of the via is difficult to be made small due to the limitation of the minimum size of the photolithography. In addition, the alignment accuracy of the photolithography mask needs to be considered, so that the Mesa width of the existing power MOSFET cannot be made small, which results in that the on-resistance of a low-voltage power device cannot be effectively reduced, and further becomes a difficult design problem of a high-current power device.
Disclosure of Invention
The embodiment of the invention aims to provide a through hole alignment-free power device, and aims to solve the problem that the width of a through hole of the conventional power device is limited by the minimum photoetching size and cannot be further reduced, so that the on-resistance of the power device is larger.
The embodiment of the invention is realized in such a way that a through hole alignment-free power device comprises a substrate and an epitaxial layer, wherein the power device is provided with a deep groove structure on the epitaxial layer, the deep groove structure sequentially comprises an insulating layer and a grid electrode from outside to inside, the insulating layer forms a bucket-shaped structure with the angle less than 60 degrees along the direction of the deep groove by oxidation of the deep groove structure, and the top of the deep groove structure is covered with an oxide layer;
the power device further includes: a source electrode and a channel are formed on the epitaxial layer outside the deep groove structure through ion implantation; and
and a through hole formed by etching the oxide layer, wherein the through hole is connected with the source electrode and the channel to form ohmic contact.
Another objective of an embodiment of the present invention is to provide a method for manufacturing a power device with a through hole free from alignment, where the method includes manufacturing a substrate and an epitaxial layer, and after the epitaxial layer is manufactured, the method further includes the following steps:
manufacturing a deep groove structure on the epitaxial layer;
sequentially forming an insulating layer and a grid electrode in the deep groove structure;
forming a source electrode and a channel on the epitaxial layer outside the deep groove structure through ion implantation;
forming a hopper-shaped structure with the depth of less than 60 degrees on the insulating layer in the deep groove structure along the direction of the deep groove by oxidation, and covering an oxide layer on the top layer;
and etching the oxide layer to form a through hole so as to connect the source electrode and the channel to form ohmic contact.
According to the embodiment of the invention, the insulating layer of the power device is in a bucket-shaped structure along the direction of the deep groove through oxidation, so that the limitation of minimum photoetching line width and alignment precision is avoided when the through hole is etched, the density of the device is increased, and the on-resistance of the power device is reduced.
Drawings
FIG. 1 is a cross-sectional structure diagram of a conventional N-type power MOSFET;
fig. 2-a to fig. 2-i are exploded schematic diagrams of a method for manufacturing a power device without via alignment according to an embodiment of the present invention;
fig. 3 is a cross-sectional view of a super junction structure of a power device with a through hole free from alignment according to an embodiment of the present invention;
fig. 4 is a cross-sectional view of a thick-oxide structure of a power device with a via free from alignment according to an embodiment of the present invention;
fig. 5 is a cross-sectional view of a structure of a multi-layer epitaxial layer of a via-alignment-free power device according to an embodiment of the invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention. In addition, the technical features involved in the embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.
According to the embodiment of the invention, the insulating layer of the power device is in a bucket-shaped structure along the direction of the deep groove through oxidation, so that the limitation of minimum photoetching line width and alignment precision is avoided when the through hole is etched, the density of the device is increased, and the on-resistance of the power device is reduced.
According to an embodiment of the invention, the through-hole alignment-free power device comprises a substrate and an epitaxial layer, wherein the power device is provided with a deep groove structure on the epitaxial layer, the deep groove structure sequentially comprises an insulating layer and a grid electrode from outside to inside, the insulating layer forms a hopper-shaped structure with the angle less than 60 degrees along the direction of the deep groove by oxidation of the deep groove structure, and the top of the deep groove structure is covered with an oxide layer;
the power device further includes: a source electrode and a channel are formed on the epitaxial layer outside the deep groove structure through ion implantation; and
and etching a through hole formed by the oxide layer, wherein the through hole is connected with the source electrode and the channel to form ohmic contact.
In the following, the embodiment of the present invention is described by taking a silicon-based N-type power MOSFET as an example, and it should be noted that the embodiment of the present invention can be applied to other semiconductor materials, such as SiC, IGBT materials, and the like, and certainly, the silicon-based power MOSFET can also be a P-type.
Fig. 2-a to 2-i show cross-sectional structures of the power device without via alignment according to the embodiment of the present invention, and only the portions relevant to the present invention are shown for convenience of illustration.
As an embodiment of the present invention, a through-hole alignment-free silicon-based N-type power MOSFET includes a substrate 11 and an epitaxial layer 12, wherein the substrate 11 is preferably a highly doped N-type substrate, the epitaxial layer is preferably an N-type epitaxial layer, the N-type power MOSFET has a deep trench structure on the epitaxial layer 12, the deep trench structure sequentially includes a gate oxide 14 and a polysilicon 15 from outside to inside, the deep trench structure forms a funnel-shaped structure of less than 60 degrees along a deep trench direction by oxidation of the gate oxide 14, and an oxide layer 17 covers the top of the deep trench structure;
the silicon-based N-type power MOSFET with the through hole free from contraposition further comprises: a source and a channel formed by ion implantation in the epitaxial layer 12 outside the deep trench structure; and
and etching a through hole formed by the oxide layer, wherein the through hole is connected with the source electrode and the channel to form ohmic contact.
In an embodiment of the invention, the via may be etched through a photoresist-formed lithographic pattern 6, typically to a depth of around 3000A. The oxide layer 17 covers the deep trench structure completely or partially depending on the etching size of the via hole, and the etching size of the via hole should be smaller than or equal to the maximum distance AA' between the top epitaxy of the bucket-shaped structure at two opposite positions in the radial section of the deep trench structure. When the etching size of the through hole is equal to AA', the oxidation layer 17 completely covers the deep groove structure; when the etching size of the through hole is smaller than AA', the oxide layer 17 partially covers the deep groove structure.
As can be seen in fig. 2-d, 2-e, the oxide layer 17 may comprise a wet oxide layer and a deposited oxide layer, which are gradually formed through a multi-step oxidation process.
It should be noted that the epitaxial layer 12 may be a single-layer epitaxy or a multi-layer epitaxy, and the doping concentration of the epitaxial layer is constant for the single-layer epitaxy. For multi-layer epitaxy, the doping concentration of the multiple epitaxial layers is different, and in combination with fig. 2-i, the epitaxial layers 12a and 12b are usually made lower in the epitaxial layer 12b than the epitaxial layer 12a in order to increase the breakdown voltage in practical applications; if the on-resistance is to be reduced, the epitaxial layer 12b is usually doped at a higher concentration than the epitaxial layer 12 a.
According to the embodiment of the invention, the insulating layer of the power device is in a bucket-shaped structure along the direction of the deep groove through oxidation, so that the limitation of minimum photoetching line width and alignment precision is avoided when the through hole is etched, the density of the device is increased, and the on-resistance of the power device is reduced.
Fig. 3 is a cross-sectional view of a super junction structure of a power device with a through hole free from alignment according to an embodiment of the present invention, and only a part related to the present invention is shown for convenience of illustration.
As a preferred embodiment of the present invention, the epitaxial layer 12 forms a drift region, and in order to reduce the on-resistance of the drift region, a P-pillar 18 may be added in the drift region to form a super junction structure, and taking a silicon-based N-type power MOSFET as an example, the P-pillar 18 may generate lateral depletion with the drift region 12, so that the on-resistance of the drift region may be greatly reduced.
Alternatively, the drift region may have multiple layers, and the source field plate 19 is isolated from the silicon wafer by an insulating layer by adding the source field plate 19 to the drift region, as shown in fig. 4.
Fig. 4 is a cross-sectional view of a super junction structure of a power device with a through hole free from alignment according to an embodiment of the present invention, and only a part related to the present invention is shown for convenience of illustration.
As an embodiment of the present invention, the insulating layer may adopt a thick Oxide (Field Oxide), the thickness of which generally depends on the breakdown voltage of the device, the thickness of 10 is generally 6000A for a device with a breakdown voltage of 100V, the thickness of 10 is generally 3500A for a device with a breakdown voltage of 60V, and the higher the breakdown voltage of the device is, the thicker the Field Oxide needs to be.
In the embodiment of the present invention, the source field plate 19 functions to laterally deplete the drift region, which can greatly increase the doping concentration of the drift region without sacrificing the breakdown voltage, thereby reducing the on-resistance of the drift region.
According to the embodiment of the invention, the insulating layer of the power device is in a bucket-shaped structure along the direction of the deep groove through oxidation, so that the limitation of minimum photoetching line width and alignment precision is avoided when the through hole is etched, the density of the device is increased, and the on-resistance of the power device is reduced.
Another objective of an embodiment of the present invention is to provide a method for manufacturing a power device with a through hole free from alignment, where the method includes manufacturing a substrate and an epitaxial layer, and after the epitaxial layer is manufactured, the method further includes the following steps:
manufacturing a deep groove structure on the epitaxial layer;
sequentially forming an insulating layer and a grid electrode in the deep groove structure;
forming a source electrode and a channel on the epitaxial layer outside the deep groove structure through ion implantation;
forming a hopper-shaped structure with the depth of less than 60 degrees on the insulating layer in the deep groove structure along the direction of the deep groove by oxidation, and covering an oxide layer on the top layer;
and etching the oxide layer to form a through hole so as to connect the source electrode and the channel to form ohmic contact.
The following embodiments of the present invention are described with reference to silicon-based N-type power MOSFETs.
Step S101, fabricating a substrate 11, and referring to fig. 2-a, the substrate 11 may be a highly doped N-type substrate;
step S102, manufacturing an epitaxial layer 12 on a substrate 11, wherein the epitaxial layer 12 is an N-type epitaxial layer;
in the embodiment of the present invention, the epitaxial layer 12 may be a single-layer epitaxy or a multi-layer epitaxy, and the doping concentration of the epitaxial layer is constant for the single-layer epitaxy. For multi-layer epitaxy, the doping concentration of the epitaxial layers is different, and in conjunction with fig. 5, the doping concentration of the epitaxial layer 12b is generally lower than that of the epitaxial layer 12a in order to increase the breakdown voltage in practical applications, for the epitaxial layers 12a and 12 b; if the on-resistance is to be reduced, the epitaxial layer 12b is usually doped at a higher concentration than the epitaxial layer 12 a.
Preferably, in order to repair the damage to the silicon wafer caused by the subsequent etching process, step S103 may be added, in which a sacrificial oxidation is performed, that is, an Oxide layer (Oxide) is grown and then etched, or step S104 may be directly performed.
Step S103, depositing an Oxide layer (Oxide)13 or a Nitride layer (Nitride) on the epitaxial layer 12, and etching a notch on the deposited Oxide layer or Nitride layer in combination with FIG. 2-b;
in the embodiment of the present invention, an Oxide layer (Oxide) or Nitride layer (Nitride)13 is deposited on the N-type epitaxial layer 12, and a photo Mask (Mask) is used to open a notch on the Oxide layer 13.
Step S104, etching the epitaxial layer through the notch to manufacture a deep groove structure;
step S105, sequentially forming a gate oxide layer 14 and a polysilicon layer 15 in the deep trench structure, and then etching off an oxide layer or a nitride layer, as shown in FIG. 2-c;
in the embodiment of the present invention, a deep trench is formed by etching the epitaxial layer 12 through the notch, a Gate Oxide (Gate Oxide)14 is formed in the deep trench, a polysilicon (Poly)15 is deposited in the Gate Oxide, and then a Poly Etch Back (Etch Back) is performed. After depositing Poly, one CMP may be performed before etching back. The deposited Poly is typically highly doped with a doping concentration above 1e 21.
Step S106, forming a source and a channel on the epitaxial layer 12 outside the deep groove structure through ion implantation;
in an embodiment of the invention, the source is formed by an Arsenic implant and the channel is formed by a Boron implant. The surface of the polysilicon 15 is substantially flush with the surface of the epitaxial layer 12 in fig. 2-c, but in practice the surface of the polysilicon 15 may be made slightly lower than the surface of the epitaxial layer 12.
Step S107, forming a hopper-shaped structure with a depth of less than 60 degrees along the deep trench direction by oxidizing the gate oxide 14 in the deep trench structure, and covering an oxide layer 17 on the top layer;
in the embodiment of the invention, silicon and polysilicon are completely oxidized and can be oxidized for multiple times, and in order to improve the oxidation speed, water vapor can be increased firstly to be oxidized by adopting wet oxygen, and then the wet oxygen is oxidized by deposition.
Depending on the desired ILD (gate line width) thickness, a layer of Oxide may be deposited on top, and then Reflow of a basic BPSG (borophosphosilicate glass) to flatten the topography of the surface Oxide.
In the actual process of the process, Poly and Silicon are oxidized simultaneously, the oxidation speed of Poly is faster than that of Silicon, so the thickness of Oxide corresponding to Poly is thicker, more Poly is eaten, and the thickness of Oxide corresponding to Silicon is thinner.
And step S108, etching the oxide layer to form a through hole so as to connect the source electrode and the channel to form ohmic contact.
In an embodiment of the present invention, the via hole may be etched by a photoresist-formed photolithographic pattern (photoevask) 6, which is formed by photolithography using a Photomask (Mask), typically with an etching depth of the via hole around 3000A. The oxide layer 17 covers the deep trench structure completely or partially depending on the etching size of the via hole, and the etching size of the via hole should be smaller than or equal to the maximum distance AA' between the top epitaxy of the bucket-shaped structure at two opposite positions in the radial section of the deep trench structure. When the etching size of the through hole is equal to AA', the oxidation layer 17 completely covers the deep groove structure; when the etching size of the through hole is smaller than AA', the oxide layer 17 partially covers the deep groove structure.
Importantly, the width of the Photomask (Mask)6 can be larger than the actually required width, fig. 2-h and fig. 2-i respectively show the etching effect of the etching size of the through hole corresponding to B-B 'and C-C', and the lower epitaxial layer (Silicon)12 is exposed by etching the Oxide layer (Oxide) 17.
As a preferred embodiment of the present invention, in order to reduce the on-resistance of the drift region, after step S102, the epitaxial layer is used as the drift region, and the P-pillar 18 is added in the drift region to form a super junction structure, for example, a silicon-based N-type power MOSFET, the P-pillar 18 can laterally deplete the drift region 12, so that the on-resistance of the drift region can be greatly reduced.
In the super junction structure, the drift region can have multiple layers, and the source field plate 19 is added in the drift region, so that the source field plate 19 is isolated from the silicon wafer by using an insulating layer, as shown in fig. 4.
As another preferred embodiment of the present invention, the insulating layer may also adopt a thick Oxide structure (Field Oxide), and with reference to fig. 4, after step S105, a thick Oxide structure (Field Oxide)10 is further fabricated at the bottom of the polysilicon, so as to improve the withstand voltage of the device, where the thickness of 10 is usually 6000A for a device with a breakdown voltage of 100V, and the thickness of 10 is usually 3500A for a device with a breakdown voltage of 60V, and the higher the breakdown voltage of the device, the thicker the thickness of Field Oxide needs to be.
In the embodiment of the present invention, the source field plate 19 functions to laterally deplete the drift region, which can greatly increase the doping concentration of the drift region without sacrificing the breakdown voltage, thereby reducing the on-resistance of the drift region.
According to the embodiment of the invention, the insulating layer of the power device is in a bucket-shaped structure along the direction of the deep groove through oxidation, so that the limitation of minimum photoetching line width and alignment precision is avoided when the through hole is etched, the density of the device is increased, and the on-resistance of the power device is reduced.
The present invention is not limited to the above preferred embodiments, and any modifications, equivalent substitutions and improvements made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (2)
1. A through hole alignment-free power device comprises a substrate and an epitaxial layer and is characterized in that the power device is provided with a deep groove structure on the epitaxial layer, the deep groove structure sequentially comprises an insulating layer and a grid electrode from outside to inside, the deep groove structure enables the insulating layer to form a bucket-shaped structure with the angle less than 60 degrees along the direction of the deep groove through oxidation, and the top of the deep groove structure is covered with an oxide layer;
the power device further includes: a source electrode and a channel are formed on the epitaxial layer outside the deep groove structure through ion implantation; and
a through hole formed by etching the oxide layer is connected with the source electrode and the channel to form ohmic contact;
the epitaxial layer forms a drift region, a P column is added in the drift region to form a super junction structure, and the P column and the drift region generate lateral depletion;
the drift region is provided with a plurality of layers, a source field plate is added in the drift region, so that the source field plate is isolated from the drift region by an insulating layer, the insulating layer adopts a thick oxygen structure, and the higher the breakdown voltage of the device is, the thicker the thickness of the thick oxygen structure is;
the oxide layer comprises a wet oxygen oxide layer and a deposited oxide layer;
the epitaxial layer is a single-layer epitaxy or a multi-layer epitaxy, the doping concentration of the epitaxial layer is fixed and invariable for the single-layer epitaxy, and the doping concentrations of the epitaxial layers are different for the multi-layer epitaxy; if the breakdown voltage is improved, enabling the doping concentration of the epitaxial layer close to the substrate to be lower than that of the epitaxial layer far away from the substrate; if the on-resistance is reduced, enabling the doping concentration of the epitaxial layer close to the substrate to be higher than that of the epitaxial layer far away from the substrate;
wherein the etching size of the through hole is equal to the farthest distance between the top epitaxy of the bucket-shaped structure at two opposite positions in the radial section of the deep groove structure
And the oxide layer completely covers the deep groove structure.
2. A manufacturing method of a through hole alignment-free power device comprises the steps of manufacturing a substrate and an epitaxial layer, and is characterized by further comprising the following steps after the epitaxial layer is manufactured:
manufacturing a deep groove structure on the epitaxial layer;
sequentially forming an insulating layer and a grid electrode in the deep groove structure;
forming a source electrode and a channel on the epitaxial layer outside the deep groove structure through ion implantation;
forming a hopper-shaped structure with the depth of less than 60 degrees on the insulating layer in the deep groove structure along the deep groove direction through multi-step oxidation, and covering an oxide layer on the top layer;
etching the oxide layer to form a through hole so as to connect the source electrode and the channel to form ohmic contact;
the epitaxial layer forms a drift region, a P column is added in the drift region to form a super junction structure, and the P column and the drift region generate lateral depletion;
the drift region is provided with a plurality of layers, a source field plate is added in the drift region, so that the source field plate is isolated from the drift region by an insulating layer, the insulating layer adopts a thick oxygen structure, and the higher the breakdown voltage of the device is, the thicker the thickness of the thick oxygen structure is;
the multi-step oxidation comprises: wet oxygen oxidation and deposition oxidation;
the epitaxial layer is a single-layer epitaxy or a multi-layer epitaxy, the doping concentration of the epitaxial layer is fixed and invariable for the single-layer epitaxy, and the doping concentrations of the epitaxial layers are different for the multi-layer epitaxy; if the breakdown voltage is improved, enabling the doping concentration of the epitaxial layer close to the substrate to be lower than that of the epitaxial layer far away from the substrate; if the on-resistance is reduced, enabling the doping concentration of the epitaxial layer close to the substrate to be higher than that of the epitaxial layer far away from the substrate;
wherein the etching size of the through hole is equal to the farthest distance between the top epitaxy of the bucket-shaped structure at two opposite positions in the radial section of the deep groove structure
And the oxide layer completely covers the deep groove structure.
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| US9136381B1 (en) * | 2014-11-18 | 2015-09-15 | Texas Instruments Incorporated | Super junction MOSFET with integrated channel diode |
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