CN108666361B - Through hole alignment-free power device and manufacturing method thereof - Google Patents

Abstract

The invention is suitable for the field of semiconductors, and provides a through hole alignment-free power device and a preparation method thereof, wherein the device comprises a substrate, an epitaxial layer and a deep groove structure arranged on the epitaxial layer, wherein the deep groove structure sequentially comprises an insulating layer and a grid electrode from outside to inside, the insulating layer forms a hopper-shaped structure with the angle less than 60 degrees along the direction of the deep groove by oxidation of the deep groove structure, and the top of the deep groove structure is covered with an oxide layer; a source electrode and a channel are formed on the epitaxial layer outside the deep groove structure through ion implantation; and a through hole formed by etching the oxide layer, the through hole connecting the source electrode and the channel to form ohmic contact. The insulating layer of the power device is in a bucket-shaped structure along the direction of the deep groove through oxidation, so that the limitation of minimum photoetching line width and alignment precision during through hole etching is avoided, the density of the device is increased, and the on-resistance of the power device is reduced.

Description

A power device with through-hole alignment-free and its manufacturing method

technical field

The invention belongs to the field of semiconductors, and in particular relates to a power device with through-hole alignment-free and a manufacturing method thereof.

Background technique

Power semiconductors are semiconductor products that process electrical energy (power) and play a very important role in the conversion control between strong electricity and weak points. Since their birth, they have been loved and concerned by engineers. After a long period of development, the application of power semiconductors in related power circuits has become irreplaceable.

Figure 1 shows the structure of a common N-type power MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor, metal oxide semiconductor field effect transistor), wherein, 1 is a highly doped substrate, and its doping concentration Usually above 1e19, its resistivity is usually between 0.5mΩ/cm-5mΩ/cm; 2 is the epitaxial layer on substrate 1, the breakdown voltage of the device mainly depends on the thickness of the epitaxial layer and its doping concentration, For a device with a breakdown voltage of 100V, the thickness of the epitaxial layer usually needs to be greater than 8 μm. The higher the breakdown voltage of the device, the lower the corresponding epitaxial layer doping concentration and the thicker the epitaxial layer thickness; 3 is the gate oxide Layer (Gate Oxide), its thickness affects the threshold voltage of the device and the breakdown voltage of the gate; 4 is polysilicon, used to form the gate; 5 is the P-type channel (Pbody), whose doping concentration determines the threshold of the device voltage, and can reduce the parasitic transistor conduction of the device by increasing the doping concentration of the P-type channel; 6 is the N-type source; 7 is a through hole, which is used to connect the source 6 and the P-type channel 5. The source electrode 6 is connected to the heavily doped P-type channel 5 through the sidewall of the through hole 7 to form an ohmic contact. In order to ensure better ohmic contact between the through hole 7 and the P-type channel 5, a CT Implant (Contact Implant, highly doped P-type implantation) is usually required. The implantation dose is usually above 1e15, and the energy is usually 40 Between -60keV.

In order to meet the design requirements of high-current power devices, it is required to continuously reduce the on-resistance of the device. It can be seen from Figure 1 that the on-resistance of the power MOSFET is composed of R _sub , R _drift and R _ch . For different breakdown voltages, R _sub The design ratios of , R _drift and R _ch are also different. In a low-voltage device, such as a device with a breakdown voltage of less than 80V, the channel resistance R _ch accounts for more than 20% of the total resistance, or even more than 40%. Therefore, when the breakdown voltage of the device is relatively low, reducing the channel resistance R _ch is particularly critical for reducing the on-resistance of the device.

的宽度，该W_M的宽度是指Mesa的宽度包括通孔的宽度，以及为了考虑到一定的工艺偏差，通孔跟栅氧层3需要一定的距离，防止通孔跟栅连在一起。其中工艺偏差包括栅极的工艺偏差，也包括通孔的工艺偏差。此外，通孔还需要跟栅有一个最小的距离，这个最小的距离是因为通孔有一个高浓度的P型注入，这个注入会有一定的衡阔，如果跟栅离的太近，会增加沟通的P型杂质的掺杂浓度，从而会影响阈值电压，会增加阈值电压。At present, the channel resistance R _ch is usually reduced by increasing the density of the device, and increasing the density of the device requires reducing the width of the through hole W _M , that is, reducing the width of the through hole W M in FIG. 1 .

The width of the W _M refers to the width of the Mesa including the width of the through hole, and in order to take into account certain process deviations, a certain distance is required between the through hole and the gate oxide layer 3 to prevent the through hole and the gate from being connected together. The process deviation includes the process deviation of the gate, and also includes the process deviation of the through hole. In addition, the through hole also needs to have a minimum distance from the gate. This minimum distance is because the through hole has a high concentration of P-type injection. This injection will have a certain width. If it is too close to the gate, it will increase The doping concentration of the communicated P-type impurities, which will affect the threshold voltage, will increase the threshold voltage.

However, in the existing design, the width of the through hole is usually determined by the width of the lithography plate. Due to the limitation of the minimum size of the lithography, it is difficult to make the width of the through hole very small. In addition, the alignment accuracy of the lithography plate also needs to be considered. Therefore, the Mesa width of the power MOSFET cannot be made small at present, which leads to the inability to effectively reduce the on-resistance of low-voltage power devices, and thus becomes a design problem for high-current power devices.

SUMMARY OF THE INVENTION

The purpose of the embodiments of the present invention is to provide a power device with through-hole alignment-free, aiming to solve the problem that the width of the through-hole of the existing power device is limited by the minimum size of lithography, which cannot be further reduced, resulting in a large on-resistance of the power device. The problem.

The embodiments of the present invention are implemented as follows: a power device with a through-hole alignment-free, the power device includes a substrate and an epitaxial layer, the power device has a deep groove structure on the epitaxial layer, and the deep The trench structure includes an insulating layer and a gate in sequence from the outside to the inside, the deep trench structure is oxidized to form a bucket-shaped structure of less than 60 degrees in the insulating layer along the direction of the deep trench, and the top of the deep trench structure is covered with an oxide layer;

The power device further includes: a source electrode and a channel formed by ion implantation in the epitaxial layer outside the deep trench structure; and

A through hole is formed by etching the oxide layer, and the through hole connects the source electrode and the channel to form an ohmic contact.

Another object of the embodiments of the present invention is to provide a method for fabricating a power device with through-hole alignment-free, the method includes fabricating a substrate and an epitaxial layer, and the method further includes the following steps after fabricating the epitaxial layer:

making a deep trench structure on the epitaxial layer;

forming an insulating layer and a gate sequentially in the deep trench structure;

The source electrode and the channel are formed by ion implantation on the epitaxial layer outside the deep trench structure;

The insulating layer in the deep trench structure is formed into a bucket-shaped structure with a degree of less than 60 degrees along the direction of the deep trench by oxidation, and the top layer is covered with an oxide layer;

The oxide layer is etched to form through holes to connect the source and the channel to form ohmic contacts.

In the embodiment of the present invention, the insulating layer of the power device is formed into a bucket-shaped structure along the direction of the deep groove through oxidation, so as to ensure that the minimum line width and alignment accuracy of lithography are not limited during the etching of the through hole, which is beneficial to increase the device density and reduce the On-resistance of power devices.

Description of drawings

1 is a cross-sectional structural diagram of an existing N-type power MOSFET;

2-a to 2-i are schematic diagrams of decomposition steps of a method for manufacturing a power device with a through-hole alignment-free according to an embodiment of the present invention;

3 is a cross-sectional view of a superjunction structure of a power device with a through hole alignment-free provided according to an embodiment of the present invention;

4 is a cross-sectional view of a thick oxygen structure of a power device with a through hole alignment-free according to an embodiment of the present invention;

FIG. 5 is a structural cross-sectional view of a multi-layer epitaxial layer of a power device with a through hole alignment-free according to an embodiment of the present invention.

Detailed ways

In order to make the objectives, technical solutions and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention, but not to limit the present invention. In addition, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

In the embodiment of the present invention, the insulating layer of the power device is formed into a bucket-shaped structure along the direction of the deep groove through oxidation, so as to ensure that the minimum line width and alignment accuracy of lithography are not limited during the etching of the through hole, which is beneficial to increase the device density and reduce the On-resistance of power devices.

As an embodiment of the present invention, the through-hole alignment-free power device includes a substrate and an epitaxial layer, the power device has a deep groove structure on the epitaxial layer, and the deep groove structure sequentially includes an insulating layer and a gate from the outside to the inside, The deep groove structure makes the insulating layer form a bucket-shaped structure with a degree of less than 60 degrees along the direction of the deep groove through oxidation, and the top of the deep groove structure is covered with an oxide layer;

The power device further includes: a source electrode and a channel formed by ion implantation in the epitaxial layer outside the deep trench structure; and

Through holes formed by etching the oxide layer, the through holes connect the source electrode and the channel to form an ohmic contact.

The following embodiments of the present invention are described by taking a silicon-based N-type power MOSFET as an example. It is worth noting that the embodiments of the present invention can also be applied to other semiconductor materials, such as SiC, IGBT materials, etc. Of course, silicon-based power MOSFETs can also be is the P type.

Figures 2-a to 2-i show the cross-sectional structure of the power device with the through-hole alignment-free provided by the embodiment of the present invention. For the convenience of description, only parts related to the present invention are shown.

As an embodiment of the present invention, the through-hole alignment-free silicon-based N-type power MOSFET includes a substrate 11 and an epitaxial layer 12, wherein the substrate 11 is preferably a highly doped N-type substrate, the epitaxial layer is preferably an N-type epitaxial layer, and the N-type epitaxial layer is preferred. The type power MOSFET has a deep trench structure on the epitaxial layer 12. The deep trench structure includes gate oxide 14 and polysilicon 15 in turn from the outside to the inside. structure, the top of the deep trench structure is covered with an oxide layer 17;

The through-hole alignment-free silicon-based N-type power MOSFET further includes: a source electrode and a channel formed by ion implantation in the epitaxial layer 12 outside the deep trench structure; and

Through holes formed by etching the oxide layer, the through holes connect the source electrode and the channel to form an ohmic contact.

In the embodiment of the present invention, the through hole can be etched through the photolithography pattern 6 formed by the photoresist, and the etching depth is usually around 3000A. The oxide layer 17 completely covers the deep groove structure or partially covers the deep groove structure depending on the etching size of the through hole, and the etching size of the through hole should be smaller than or equal to the two opposite positions in the radial section of the deep groove structure. The furthest distance AA' between the top epitaxy of the like structure. When the etching size of the through hole should be equal to AA', the oxide layer 17 completely covers the deep trench structure; when the etching size of the through hole should be smaller than AA', the oxide layer 17 partially covers the deep trench structure.

It can be seen from FIG. 2-d and FIG. 2-e that the oxide layer 17 may include a wet oxygen oxide layer and a deposited oxide layer, which are gradually formed through a multi-step oxidation process.

It should be noted that the epitaxial layer 12 may be a single-layer epitaxy or a multi-layer epitaxy. For the single-layer epitaxy, the doping concentration of the epitaxial layer is fixed. For multi-layer epitaxy, the doping concentration of multiple epitaxial layers is different. Referring to Fig. 2-i, epitaxial layers 12a and 12b, in order to improve the breakdown voltage in practical applications, the doping concentration ratio of epitaxial layer 12b is usually The epitaxial layer 12a is low; in order to reduce the on-resistance, the doping concentration of the epitaxial layer 12b is usually higher than that of the epitaxial layer 12a.

In the embodiment of the present invention, the insulating layer of the power device is formed into a bucket-shaped structure along the direction of the deep groove through oxidation, so as to ensure that the minimum line width and alignment accuracy of lithography are not limited during the etching of the through hole, which is beneficial to increase the device density and reduce the On-resistance of power devices.

3 is a cross-sectional view of a superjunction structure of a power device with a through hole alignment-free according to an embodiment of the present invention. For convenience of description, only parts related to the present invention are shown.

As a preferred embodiment of the present invention, the epitaxial layer 12 forms a drift region. In order to reduce the on-resistance of the drift region, a P-pillar 18 can be added to the drift region to form a superjunction structure. Taking a silicon-based N-type power MOSFET as an example, the P-type The P pillar 18 can generate lateral depletion with the drift region 12, so that the on-resistance of the drift region can be greatly reduced.

In addition, the drift region may have multiple layers. By adding a source field plate 19 in the drift region, the source field plate 19 and the silicon wafer are isolated by an insulating layer, see FIG. 4 .

FIG. 4 is a cross-sectional view of a superjunction structure of a power device with a through hole alignment-free according to an embodiment of the present invention. For convenience of description, only parts related to the present invention are shown.

As an embodiment of the present invention, the insulating layer can adopt a thick oxide structure (Field Oxide), and its thickness usually depends on the breakdown voltage of the device. For a device with a breakdown voltage of 100V, the thickness of 10 is usually 6000A. For the breakdown voltage For a 60V device, the thickness of 10 is usually 3500A, the higher the breakdown voltage of the device, the thickness of the Field Oxide needs to be thicker.

In the embodiment of the present invention, the function of the source field plate 19 is to deplete the drift region laterally, which can greatly increase the doping concentration of the drift region without sacrificing the breakdown voltage, thereby reducing the conduction of the drift region. resistance.

In the embodiment of the present invention, the insulating layer of the power device is formed into a bucket-shaped structure along the direction of the deep groove through oxidation, so as to ensure that the minimum line width and alignment accuracy of lithography are not limited during the etching of the through hole, which is beneficial to increase the device density and reduce the On-resistance of power devices.

Another object of the embodiments of the present invention is to provide a method for fabricating a power device with through-hole alignment-free, the method includes fabricating a substrate and an epitaxial layer, and the method further includes the following steps after fabricating the epitaxial layer:

Fabrication of deep trench structures on the epitaxial layer;

forming an insulating layer and a gate sequentially in the deep trench structure;

The source electrode and the channel are formed by ion implantation on the epitaxial layer outside the deep trench structure;

The insulating layer in the deep trench structure is formed into a bucket-shaped structure with a degree of less than 60 degrees along the direction of the deep trench by oxidation, and the top layer is covered with an oxide layer;

The oxide layer is etched to form through holes to connect the source and the channel to form ohmic contacts.

The following embodiments of the present invention will be described by taking a silicon-based N-type power MOSFET as an example.

In step S101, a substrate 11 is fabricated. Referring to FIG. 2-a, the substrate 11 can be a highly doped N-type substrate;

Step S102, an epitaxial layer 12 is fabricated on the substrate 11, and the epitaxial layer 12 is an N-type epitaxial layer;

In the embodiment of the present invention, the epitaxial layer 12 may be a single-layer epitaxy or a multi-layer epitaxy. For the single-layer epitaxy, the doping concentration of the epitaxial layer is fixed. For multi-layer epitaxy, the doping concentration of multiple epitaxial layers is different. Referring to Fig. 5, the epitaxial layers 12a and 12b, in order to improve the breakdown voltage in practical applications, the doping concentration of the epitaxial layer 12b is usually higher than that of the epitaxial layer. 12a is low; in order to reduce the on-resistance, the doping concentration of the epitaxial layer 12b is usually higher than that of the epitaxial layer 12a.

Preferably, in order to repair the damage to the silicon wafer caused by the subsequent etching process, step S103 may be added to perform a sacrificial oxidation, that is, an oxide layer (Oxide) is grown, and then etched away, or step S104 may be directly performed.

Step S103, depositing an oxide layer (Oxide) 13 or a nitride layer (Nitride) on the epitaxial layer 12, referring to FIG. 2-b, and etching a notch on the deposited oxide layer or nitride layer;

In the embodiment of the present invention, an oxide layer (Oxide) or a nitride layer (Nitride) 13 is deposited on the N-type epitaxial layer 12, and a notch is formed on the oxide layer 13 by using a photomask (Mask).

In step S104, the epitaxial layer is etched through the groove to form a deep groove structure;

Step S105, forming gate oxide 14 and polysilicon 15 in sequence in the deep trench structure, and then etching off the oxide layer or the nitride layer, see Fig. 2-c;

In the embodiment of the present invention, a deep trench is formed by etching the epitaxial layer 12 through the notch, and a gate oxide (Gate Oxide) 14 is grown in the deep trench structure, polysilicon (Poly) 15 is deposited in the gate oxide, and then Poly Etch Back. After depositing the Poly, you can do a CMP first before doing the engraving. The deposited Poly is usually highly doped, with a doping concentration above 1e21.

Step S106, forming a source electrode and a channel by ion implantation on the epitaxial layer 12 outside the deep trench structure;

In the embodiment of the present invention, the source electrode is formed by Arsenic implantation, and the channel is formed by Boron implantation. In FIG. 2-c, the surface of the polysilicon 15 is substantially flush with the surface of the epitaxial layer 12, but in fact, the surface of the polysilicon 15 can be made slightly lower than the surface of the epitaxial layer 12.

Step S107, the gate oxide 14 in the deep trench structure is formed into a bucket-shaped structure of less than 60 degrees along the direction of the deep trench by oxidation, and the top layer is covered with an oxide layer 17;

In the embodiment of the present invention, all silicon and polysilicon are oxidized, and can be oxidized in multiple times. In order to improve the oxidation speed, wet oxygen can be added to increase water vapor first, and then the oxidation can be carried out by deposition.

According to the thickness of the ILD (gate line width) we need, a layer of Oxide can be deposited on it, and then the basic BPSG (borophosphosilicate glass) Reflow (reflow) is used to flatten the surface Oxide.

In the actual process of the process, Poly and Silicon are oxidized at the same time, and the oxidation speed of Poly will be faster than that of Silicon, so its corresponding Oxide thickness will be thicker, more Poly will be eaten, and the corresponding Oxide thickness on Silicon will be thinner. Some.

In step S108, the oxide layer is etched to form a through hole, so as to connect the source electrode and the channel to form an ohmic contact.

In the embodiment of the present invention, the through hole can be etched through a photolithography pattern (Photomask) 6 formed by photoresist, and the photolithography pattern is formed by lithography on a photomask (Mask), usually the etching depth of the through hole is around 3000A. The oxide layer 17 completely covers the deep groove structure or partially covers the deep groove structure depending on the etching size of the through hole, and the etching size of the through hole should be smaller than or equal to the two opposite positions in the radial section of the deep groove structure. The furthest distance AA' between the top epitaxy of the like structure. When the etching size of the through hole should be equal to AA', the oxide layer 17 completely covers the deep trench structure; when the etching size of the through hole should be smaller than AA', the oxide layer 17 partially covers the deep trench structure.

What is important is that the width of the photomask (Mask) 6 can be larger than the actual required width. Figure 2-h and Figure 2-i respectively show that the etching size of the through hole is at the corresponding etching size of B-B' and C-C'. The etching effect is obtained by etching the oxide layer (Oxide) 17, so that the underlying epitaxial layer (Silicon) 12 is exposed. Because the gate oxide forms a bucket-shaped structure with a wide upper and a narrow lower through oxidation in the embodiment of the present invention, The width of the Oxide on the surface of the silicon wafer is wide, and the width of the Oxide in the silicon wafer is narrow. Therefore, regardless of the size of the opening of the reticle, as long as the photomask formed is smaller than the width corresponding to A-A', the width and shape of the exposed Silicon will be the same. the same.

As a preferred embodiment of the present invention, in order to reduce the on-resistance of the drift region, after step S102, an epitaxial layer can be used as the drift region, and a P-pillar 18 is added to the drift region to form a superjunction structure, and a silicon-based N-type power MOSFET can be used. For example, the P-type P-pillar 18 can be laterally depleted with the drift region 12, so that the on-resistance of the drift region can be greatly reduced.

In the superjunction structure, the drift region can have multiple layers. By adding the source field plate 19 in the drift region, the source field plate 19 and the silicon wafer are isolated by an insulating layer, referring to FIG. 4 .

As another preferred embodiment of the present invention, the insulating layer can also adopt a thick oxygen structure (Field Oxide), with reference to FIG. 4, after step S105, a thick oxygen structure (Field Oxide) 10 is further fabricated on the bottom of the polysilicon, thereby improving the device's performance. Withstand voltage value, for a device with a breakdown voltage of 100V, the thickness of 10 is usually 6000A, and for a device with a breakdown voltage of 60V, the thickness of 10 is usually 3500A. The higher the breakdown voltage of the device, the thicker the Field Oxide needs to be. thick.

In the embodiment of the present invention, the function of the source field plate 19 is to deplete the drift region laterally, which can greatly increase the doping concentration of the drift region without sacrificing the breakdown voltage, thereby reducing the conduction of the drift region. resistance.

In the embodiment of the present invention, the insulating layer of the power device is formed into a bucket-shaped structure along the direction of the deep groove through oxidation, so as to ensure that the minimum line width and alignment accuracy of lithography are not limited during the etching of the through hole, which is beneficial to increase the device density and reduce the On-resistance of power devices.

The above are only preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements and improvements made within the spirit and principles of the present invention shall be included in the protection scope of the present invention. Inside.

Claims (2)

1. A power device with through-hole alignment-free, the power device comprises a substrate and an epitaxial layer, wherein the power device has a deep groove structure on the epitaxial layer, and in the deep groove structure The insulating layer and the gate are sequentially included from the outside to the inside, the deep trench structure is oxidized so that the insulating layer forms a bucket-shaped structure with a degree of less than 60 degrees along the direction of the deep trench, and the top of the deep trench structure is covered with an oxide layer; The power device further includes: a source electrode and a channel formed by ion implantation in the epitaxial layer outside the deep trench structure; and A through hole formed by etching the oxide layer, the through hole connects the source electrode and the channel to form an ohmic contact; Wherein, the epitaxial layer forms a drift region, a P pillar is added to the drift region to form a superjunction structure, and the P pillar and the drift region are laterally depleted; The drift region has multiple layers. By adding a source field plate to the drift region, an insulating layer is used to isolate the source field plate from the drift region. The insulating layer adopts a thick oxygen structure. The higher the breakdown voltage of , the thicker the thickness of the thick oxygen structure; The oxide layer includes a wet oxygen oxide layer and a deposition oxide layer; The epitaxial layer is single-layer epitaxy or multi-layer epitaxy. For the single-layer epitaxy, the doping concentration of the epitaxial layer is fixed. For the multi-layer epitaxy, the doping concentration of the multiple epitaxial layers is different; in order to increase the breakdown voltage, the doping concentration of the epitaxial layer close to the substrate is lower than that of the epitaxial layer far from the substrate; in order to reduce the on-resistance, the doping concentration of the epitaxial layer close to the substrate is made lower The doping concentration of the epitaxial layer is higher than that of the epitaxial layer away from the substrate; Wherein, the etching size of the through hole is equal to the farthest distance between the top epitaxy of the bucket-shaped structure at two opposite positions in the radial section of the deep groove structure

, the oxide layer completely covers the deep trench structure. 2. a method for making a power device with a through-hole alignment-free, the method comprises making a substrate and an epitaxial layer, and it is characterized in that, the method further comprises the following steps after making the epitaxial layer: making a deep trench structure on the epitaxial layer; forming an insulating layer and a gate sequentially in the deep trench structure; The source electrode and the channel are formed by ion implantation on the epitaxial layer outside the deep trench structure; Through multi-step oxidation, the insulating layer in the deep groove structure is formed into a bucket-shaped structure with a degree of less than 60 degrees along the direction of the deep groove, and the top layer is covered with an oxide layer; Etching the oxide layer to form a through hole to connect the source and the channel to form an ohmic contact; Wherein, the epitaxial layer forms a drift region, a P pillar is added to the drift region to form a superjunction structure, and the P pillar and the drift region are laterally depleted; The drift region has multiple layers. By adding a source field plate to the drift region, the source field plate and the drift region are isolated by an insulating layer. The insulating layer adopts a thick oxygen structure. The higher the breakdown voltage, the thicker the thickness of the thick oxygen structure; The multi-step oxidation includes: wet oxygen oxidation and deposition oxidation; The epitaxial layer is single-layer epitaxy or multi-layer epitaxy. For the single-layer epitaxy, the doping concentration of the epitaxial layer is fixed. For the multi-layer epitaxy, the doping concentration of the multiple epitaxial layers is different; in order to increase the breakdown voltage, the doping concentration of the epitaxial layer close to the substrate is lower than that of the epitaxial layer far from the substrate; in order to reduce the on-resistance, the doping concentration of the epitaxial layer close to the substrate is made lower The doping concentration of the epitaxial layer is higher than that of the epitaxial layer away from the substrate; Wherein, the etching size of the through hole is equal to the farthest distance between the top epitaxy of the bucket-shaped structure at two opposite positions in the radial section of the deep groove structure

, the oxide layer completely covers the deep trench structure.

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