CN108665942A - A kind of test method and equipment of nand flash memory chip - Google Patents
A kind of test method and equipment of nand flash memory chip Download PDFInfo
- Publication number
- CN108665942A CN108665942A CN201710212514.7A CN201710212514A CN108665942A CN 108665942 A CN108665942 A CN 108665942A CN 201710212514 A CN201710212514 A CN 201710212514A CN 108665942 A CN108665942 A CN 108665942A
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- CN
- China
- Prior art keywords
- test
- flash memory
- nand flash
- data block
- memory chip
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
Abstract
The embodiment of the invention discloses a kind of test method of nand flash memory chip and equipment.The method includes：Parameter testing instruction is received, parameter testing is carried out to the selected data block in nand flash memory chip according to parameter testing instruction；The test instruction of programming erasing loop attenuation is received during the parameter testing, the test instruction that loop attenuation is wiped according to the programming, is programmed the data block in the nand flash memory chip in addition to the selected data block test of erasing loop attenuation.For the problem that the testing time in the prior art is long, efficiency is low, method and apparatus provided in an embodiment of the present invention has achieved the effect that shorten the test period of flash chip, has improved testing efficiency.
Description
Technical field
The present embodiments relate to the test methods and equipment of memory technology more particularly to a kind of nand flash memory chip.
Background technology
Nand flash memory is one kind of Flash memories, belongs to nonvolatile semiconductor memory.Nand flash memory includes many numbers
According to block, each data block is made of the memory cell for being much arranged in array, for storing data.
Its basic performance will be determined after nand flash memory chip manufacture by testing, and actually made with determining whether to meet
Demand, is generally divided into parameter testing and the test of operation is wiped in read-write, voltage tester, temperature in parameter testing such as chip
Test or operating mode test etc., the purpose that operation test is wiped in read-write are to wipe operating characteristics to understand the read-write of chip.These
Test is usually required for long time, therefore, how to save the time of test, improves the efficiency of test, becomes current
Urgent problem to be solved.
Invention content
The embodiment of the present invention provides a kind of test method and equipment of nand flash memory chip, to solve to test in the prior art
The problem that time is long, efficiency is low.
In a first aspect, an embodiment of the present invention provides a kind of test method of nand flash memory chip, this method includes：
Parameter testing instruction is received, the selected data block in nand flash memory chip is joined according to parameter testing instruction
Number test；
The test instruction that programming erasing loop attenuation is received during the parameter testing, is followed according to programming erasing
The test instruction of ring decaying, erasing is programmed to the data block in the nand flash memory chip in addition to the selected data block
The test of loop attenuation.
Further, the method further includes：
Data block to being programmed erasing loop attenuation test is marked, and in the chips by label storage
Predeterminated position.
Second aspect, an embodiment of the present invention provides a kind of test equipment of nand flash memory chip, which includes：
First receiving module, for receiving parameter testing instruction；
First test module, for being joined to the selected data block of nand flash memory chip according to parameter testing instruction
Number test；
Second receiving module, the test for receiving programming erasing loop attenuation during the parameter testing refer to
It enables；
Second test module, the test for wiping loop attenuation according to the programming instructs, to the nand flash memory core
Data block in piece in addition to the selected data block is programmed the test of erasing loop attenuation.
Further, the equipment further includes：
Mark module for the data block for being programmed erasing loop attenuation test to be marked, and the label is deposited
The predeterminated position of storage in the chips.
The embodiment of the present invention is by while carrying out parameter testing, carrying out data block different in nand flash memory chip
Programming erasing loop attenuation test is realized to solve the problems, such as that the testing time is long in the prior art, efficiency is low and improves nand flash memory
The purpose of chip testing efficiency.
Description of the drawings
Fig. 1 is the flow chart of the test method for the nand flash memory chip that the embodiment of the present invention one provides；
Fig. 2 is the structural schematic diagram of the test equipment of nand flash memory chip provided by Embodiment 2 of the present invention.
Specific implementation mode
The present invention is described in further detail with reference to the accompanying drawings and examples.It is understood that this place is retouched
The specific embodiment stated is used only for explaining the present invention rather than limitation of the invention.It also should be noted that in order to just
Only the parts related to the present invention are shown in description, attached drawing rather than entire infrastructure.
It should be mentioned that some exemplary embodiments are described as before exemplary embodiment is discussed in greater detail
The processing described as flow chart or method.Although each step is described as the processing of sequence, many of which by flow chart
Step can be implemented concurrently, concomitantly or simultaneously.In addition, the sequence of each step can be rearranged.When its operation
The processing can be terminated when completion, it is also possible to the additional step being not included in attached drawing.The processing can be with
Corresponding to method, function, regulation, subroutine, subprogram etc..
Embodiment one
Fig. 1 is the flow chart of the test method for the nand flash memory chip that the embodiment of the present invention one provides, and the present embodiment can fit
The case where being tested for nand flash memory chip is applied to NAND flash memory storage equipment, and this method can be by nand flash memory chip
Test equipment executes, which may be used software and/or the mode of hardware is realized.
The method that the embodiment of the present invention one provides specifically includes：
S110, parameter testing instruction is received, is instructed to the selected data block in nand flash memory chip according to the parameter testing
Carry out parameter testing.
Wherein, parameter testing instruction may include test address and test content.Parameter testing address for example can be several
According to the address of block.The content of parameter testing may include temperature test, Hi-pot test or the operating mode of nand flash memory chip
Test etc..The parameter testing can be carried out to one or more data blocks.
S120, the test instruction that programming erasing loop attenuation is received during the parameter testing, according to the programming
The test instruction for wiping loop attenuation, compiles the data block in the nand flash memory chip in addition to the selected data block
Journey wipes the test of loop attenuation.
Due to carrying out the test that parameter testing can be unrelated with erasing loop attenuation is programmed to chip, Ke Yi
While carrying out parameter testing, other data blocks are programmed with erasing loop attenuation test parallel, to improve the effect of test
Rate.
The characteristics of due to nand flash memory chip itself, can only be write the data in storage unit as " 0 " from " 1 ", and cannot
Write as " 1 " from " 0 ", it, can only be the data of entire data all storage units in the block if wanting to realize the operation from " 0 " to " 1 "
Erasing, and erasing operation requires a great deal of time.Wherein, the data of storage unit are write to the process of " 0 " from " 1 " as, just
Being can not be to the floating of the storage unit if the data to be written are exactly " 1 " to the process of floating grid injection charge
Grid injects charge.The process that the data of entire data all storage units in the block are wiped, exactly in storage unit
Process derived from floating gate charge.After completing write operation, due to the electricity that applies during reading data of control grid
Pressure is smaller or does not apply voltage, is not enough to change original quantity of electric charge in floating grid, so read operation will not change
The original data of memory cell in nand flash memory chip.
Correspondingly, parameter attenuation can be carried out sample drawn data block in same series-produced nand flash memory chip
Test.For example, nand flash memory chip can generally carry out 100000 programming erasing circulate operations, then can examine before test
The threshold voltage distribution for surveying sample data block, is later programmed sample data block the loop test of operation and erasing operation
100000 times, after the completion of test, the threshold voltage distribution of sample data block is detected again, so as to obtain sample data block threshold
The attenuation of threshold voltage distribution.
Illustratively, it can be read after according to the data block address for obtaining carrying out parameter testing in data Block decoder
It is the first data block and the second data block to take data block address therein, i.e. block 0 and block 1, then to other data blocks,
As one or more in block 3 and block 4 is programmed erasing loop attenuation test.
The technical solution of the present embodiment, by while carrying out parameter testing, to number different in nand flash memory chip
Erasing loop attenuation test is programmed according to block to realize and improve to solve the problems, such as that the testing time is long in the prior art, efficiency is low
The purpose of nand flash memory chip testing efficiency.
Based on the above technical solution, it is preferred that the method further includes：It is surveyed to being programmed erasing loop attenuation
The data block of examination is marked, and the predeterminated position by label storage in the chips.
Wherein, after being programmed erasing loop attenuation test to sample data block, since number base can be used in it
Originally it uses up, data storage can not be normally carried out in subsequent work, so, it can be to being programmed erasing loop test
Sample data block is marked.May include sample data block address in label, label can be with default position stored in the chip
It sets, which can be the data block of the confirmation no problem before manufacture, and can be in the mistake that nand flash memory chip uses
Cheng Zhong preferentially reads the tag address wherein stored, then carries out write operation or other operations.
The benefit being arranged in this way is can be to avoid during nand flash memory chip use, and mistake writes data into sample
The phenomenon that leading to not be normally written or read in notebook data block.
Embodiment two
Fig. 2 is the structural schematic diagram of the test equipment of nand flash memory chip provided by Embodiment 2 of the present invention.Such as Fig. 2 institutes
Show, the test equipment of the nand flash memory chip includes：
First receiving module 210, for receiving parameter testing instruction；
First test module 220, for according to parameter testing instruction to the selected data block of nand flash memory chip into
Row parameter testing；
Second receiving module 230, the test for receiving programming erasing loop attenuation during the parameter testing
Instruction；
Second test module 240, the test for wiping loop attenuation according to the programming instructs, to the nand flash memory
Data block in chip in addition to the selected data block is programmed the test of erasing loop attenuation.
The technical solution of the present embodiment, by while carrying out parameter testing, to number different in nand flash memory chip
The test of erasing loop attenuation is programmed according to block, to solve the problems, such as that the testing time is long in the prior art, efficiency is low, realization carries
The purpose of high nand flash memory chip testing efficiency.
On the basis of the various embodiments described above, the equipment further includes：
Mark module 250, for the data block for being programmed erasing loop attenuation test to be marked, and by the label
The predeterminated position of storage in the chips.
The said goods can perform the method that any embodiment of the present invention is provided, and have the corresponding function module of execution method
And advantageous effect.
Note that above are only presently preferred embodiments of the present invention and institute's application technology principle.It will be appreciated by those skilled in the art that
The present invention is not limited to specific embodiments described here, can carry out for a person skilled in the art it is various it is apparent variation,
It readjusts and substitutes without departing from protection scope of the present invention.Therefore, although being carried out to the present invention by above example
It is described in further detail, but the present invention is not limited only to above example, without departing from the inventive concept, also
May include other more equivalent embodiments, and the scope of the present invention is determined by scope of the appended claims.
Claims (4)
1. a kind of test method of nand flash memory chip, which is characterized in that the method includes：
Parameter testing instruction is received, parameter survey is carried out to the selected data block in nand flash memory chip according to parameter testing instruction
Examination；
The test instruction that programming erasing loop attenuation is received during the parameter testing declines according to programming erasing cycle
The test instruction subtracted is programmed erasing cycle to the data block in the nand flash memory chip in addition to the selected data block
The test of decaying.
2. according to the method described in claim 1, it is characterized in that, the method further includes：
Data block to being programmed erasing loop attenuation test is marked, and by label storage in the chips pre-
If position.
3. a kind of test equipment of nand flash memory chip, which is characterized in that the equipment includes：
First receiving module, for receiving parameter testing instruction；
First test module, for carrying out parameter survey to the selected data block of nand flash memory chip according to parameter testing instruction
Examination；
Second receiving module, the test instruction for receiving programming erasing loop attenuation during the parameter testing；
Second test module, the test for wiping loop attenuation according to the programming instructs, in the nand flash memory chip
Data block in addition to the selected data block is programmed the test of erasing loop attenuation.
4. equipment according to claim 3, which is characterized in that the equipment further includes：
Mark module for the data block for being programmed erasing loop attenuation test to be marked, and the label is stored in
Predeterminated position in the chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201710212514.7A CN108665942A (en) | 2017-04-01 | 2017-04-01 | A kind of test method and equipment of nand flash memory chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710212514.7A CN108665942A (en) | 2017-04-01 | 2017-04-01 | A kind of test method and equipment of nand flash memory chip |
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| CN108665942A true CN108665942A (en) | 2018-10-16 |
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| CN201710212514.7A Pending CN108665942A (en) | 2017-04-01 | 2017-04-01 | A kind of test method and equipment of nand flash memory chip |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111863094A (en) * | 2019-04-29 | 2020-10-30 | 北京兆易创新科技股份有限公司 | Method and device for controlling erasing performance |
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| US20090006917A1 (en) * | 2007-06-26 | 2009-01-01 | Hynix Semiconductor, Inc. | Test circuit for supporting concurrent test mode in a semiconductor memory |
| CN102097133A (en) * | 2010-12-31 | 2011-06-15 | 中国人民解放军装备指挥技术学院 | System and method for testing reliability of mass storage system |
| US20130301335A1 (en) * | 2012-05-08 | 2013-11-14 | Adrian E. Ong | Architecture, system and method for testing resistive type memory |
| CN104765695A (en) * | 2015-04-03 | 2015-07-08 | 上海交通大学 | NAND FLASH bad block management system and method |
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2017
- 2017-04-01 CN CN201710212514.7A patent/CN108665942A/en active Pending
Patent Citations (6)
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| CN101241751A (en) * | 2007-02-08 | 2008-08-13 | 恩益禧电子股份有限公司 | Semiconductor device and method of testing semiconductor device |
| US20080192554A1 (en) * | 2007-02-08 | 2008-08-14 | Nec Electronics Corporation | Semiconductor device and method of testing semiconductor device |
| US20090006917A1 (en) * | 2007-06-26 | 2009-01-01 | Hynix Semiconductor, Inc. | Test circuit for supporting concurrent test mode in a semiconductor memory |
| CN102097133A (en) * | 2010-12-31 | 2011-06-15 | 中国人民解放军装备指挥技术学院 | System and method for testing reliability of mass storage system |
| US20130301335A1 (en) * | 2012-05-08 | 2013-11-14 | Adrian E. Ong | Architecture, system and method for testing resistive type memory |
| CN104765695A (en) * | 2015-04-03 | 2015-07-08 | 上海交通大学 | NAND FLASH bad block management system and method |
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| CN111863094A (en) * | 2019-04-29 | 2020-10-30 | 北京兆易创新科技股份有限公司 | Method and device for controlling erasing performance |
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Application publication date: 20181016 |