CN108664210B - IO command control method, IO command control system and solid-state storage device - Google Patents

Abstract

The application provides an IO command control method, a control system and solid-state storage equipment, and relates to the field of solid-state storage equipment. The disclosed method for IO command control includes: whether the pending NVM chip command can be submitted is determined based on the energy that the backup power supply can provide to the NVM chip. The method and the device are used for improving the reliability of IO command processing.

Description

IO command control method, IO command control system and solid-state storage device

Technical Field

The present application relates to the field of solid state storage devices, and in particular to handling abnormal power down events in solid state storage devices.

Background

FIG. 1 is a block diagram of a prior art solid state storage device. The solid state storage device 102 is coupled to a host for providing storage capability for the host. The host and solid state storage device 102 may be coupled by a variety of means including, but not limited to, connecting the host to the solid state storage device 102 via, for example, SATA (Serial Advanced Technology Attachment ), SCSI (Small Computer System Interface, small computer system interface), SAS (Serial Attached SCSI ), IDE (Integrated Drive Electronics, integrated drive electronics), USB (Universal Serial Bus ), PCIE (Peripheral Component Interconnect Express, PCIE, peripheral component interconnect Express), NVMe (NVM Express), ethernet, fibre channel, wireless communications network, and the like. The host may be an information processing device capable of communicating with the solid state storage device in the manner described above, such as a personal computer, tablet, server, portable computer, network switch, router, cellular telephone, personal digital assistant, or the like. The memory device 102 includes an interface 103, a control unit 104, one or more NVM chips 105, and a DRAM (Dynamic Random Access Memory ) 110.

NAND flash memory, phase change memory, feRAM (Ferroelectric RAM, ferroelectric memory), MRAM (Magnetic Random Access Memory, magnetoresistive memory), RRAM (Resistive Random Access Memory, resistive memory), and the like are common NVM.

The interface 103 may be adapted to exchange data with a host by way of, for example, SATA, IDE, USB, PCIE, NVMe, SAS, ethernet, fibre channel, etc.

The control unit 104 is used to control data transfer among the interface 103, NVM chip 105, and firmware memory 110, and also for storage management, host logical address to flash physical address mapping, erase balancing, bad block management, etc. The control component 104 can be implemented in a variety of ways, such as software, hardware, firmware, or a combination thereof, for example, the control component 104 can be in the form of an FPGA (Field-programmable gate array, field programmable gate array), an ASIC (Application Specific Integrated Circuit, application-specific integrated circuit), or a combination thereof; the control component 104 may also include a processor or controller in which software is executed to manipulate the hardware of the control component 104 to process IO (Input/Output) commands; control unit 104 may also be coupled to DRAM 110 and may access data of DRAM 110; FTL tables and/or cached data of IO commands may be stored in the DRAM.

Software and/or firmware (hereinafter collectively referred to as "firmware") running in control component 104 can be stored in NVM chip 105 or in another firmware memory. At power-up of solid state storage device 102, firmware is loaded from firmware memory into memory internal to DRAM 110 and/or control component 104. Optionally, the firmware is received and loaded through interface 103 or a debug interface.

The control section 104 includes a flash interface controller (or referred to as a media interface controller, a flash channel controller) that is coupled to the NVM chip 105 and issues commands to the NVM chip 105 in a manner conforming to an interface protocol of the NVM chip 105 to operate the NVM chip 105 and receive a command execution result output from the NVM chip 105. The interface protocols of NVM chip 105 include well-known interface protocols or standards such as "Toggle", "ONFI".

The memory Target (Target) is one or more Logic Units (LUNs) of a shared Chip Enable (CE) signal within the NAND flash package. Each logical unit has a logical unit number (Logic Unit Number). One or more dies (Die) may be included within the NAND flash package. Typically, the logic unit corresponds to a single die. The logic cell may include multiple planes (planes). Multiple planes within a logic unit may be accessed in parallel, while multiple logic units within a NAND flash memory chip may execute commands and report status independently of each other. In "Open NAND Flash Interface Specification (review 3.0)" available from http:// www.micron.com/-/media/Documents/Products/Other% 20Documents/ON FI3_0gold. Ashx, the meaning of target, logical unit, LUN, plane is provided as part of the prior art.

Data is typically stored and read on a storage medium on a page basis. While data is erased in blocks. A block contains a plurality of pages. Pages on a storage medium (referred to as physical pages) have a fixed size, e.g., 17664 bytes. The physical pages may also have other sizes. A physical page may include a plurality of data frames (data frames) therein, the data frames having a specified size, such as 4096 or 4416 bytes.

In solid state storage devices, FTL (Flash Translation Layer ) is utilized to maintain mapping information from logical addresses to physical addresses. The logical addresses constitute the storage space of the solid state storage device as perceived by upper level software such as the operating system. The physical address is an address for accessing a physical storage unit of the solid state storage device. Address mapping can also be implemented in the prior art using an intermediate address modality. For example, logical addresses are mapped to intermediate addresses, which in turn are further mapped to physical addresses.

The table structure storing mapping information from logical addresses to physical addresses is called FTL table. FTL tables are important metadata in solid state storage devices. Typically, the data items of the FTL table record address mapping relationships in units of data pages in the solid-state storage device.

FTL tables include a plurality of FTL table entries (or entries). In one embodiment, a correspondence of one logical page address to one physical page is recorded in each FTL table entry. In another example, correspondence between consecutive logical page addresses and consecutive physical pages is recorded in each FTL table entry. In yet another embodiment, a correspondence of logical block addresses to physical block addresses is recorded in each FTL table entry. In still another embodiment, the FTL table records a mapping relationship between a logical block address and a physical block address, and/or a mapping relationship between a logical page address and a physical page address.

When a read command from a host is processed, the solid-state storage device obtains a corresponding physical address from the FTL table by utilizing a logic address carried in the read command, sends a read request to the NVM chip according to the physical address, and receives data output by the NVM chip in response to the read request. When a write command from a host is processed, the solid state storage device allocates a physical address for the write command, records the correspondence between the logical address of the write command and the allocated physical address in the FTL table, and issues a write request to the NVM chip according to the allocated physical address.

A plurality of NVM chips are included in the solid-state storage device. Each NVM chip includes one or more DIEs (DIE) or Logical Units (LUNs). The die or logic units may respond to read and write operations in parallel. Multiple read, write, or erase operations are performed sequentially on the same die or logic unit.

Some solid state storage devices also provide backup power, which provides temporary power to the storage device for backing up metadata and processing commands that have not yet been completed when an unexpected power outage occurs. The standby power supply comprises a super capacitor, an aluminum capacitor, a tantalum polymer capacitor, a lithium battery and the like.

Disclosure of Invention

The write command processing bandwidth of the existing solid-state storage device is limited by the number of flash channels and the amount of power of a standby power supply, so that various IO commands need to be processed with limited bandwidth, and good performance, user experience or service quality can be obtained. When a power down event occurs, there are already issued commands on the solid state storage device, and it is necessary to ensure that these already issued commands are written to the NVM chip within the time that the spare power supply is powered after the power down, so that the number of IO commands on the solid state storage device that have been started but not completed in execution cannot be excessive. Solid state drives typically include multiple flash memory chips, each of which, in serial, processes flash commands (read, program, erase, etc.) for each flash memory chip, die, or LUN, and after power down, it is also ensured that the flash commands to be processed on each flash memory chip cannot be excessive. Solid state storage devices, on the other hand, require high performance to achieve high storage bandwidth, and high IO command concurrency processing capability (evaluated in IOPS, IOPS (IO per Second), the number of IO instructions processed per second). High performance is required while ensuring reliability after power failure.

According to a first aspect of the present application, there is provided a method of first IO command control according to the first aspect of the present application, the method comprising: whether the pending NVM chip command can be submitted is determined based on the energy that the backup power supply can provide to the NVM chip.

According to the method for controlling the first IO command of the first aspect of the application, the method for controlling the second IO command of the first aspect of the application is provided, if page strips need to be allocated for the NVM chip command to be processed, the energy which can be provided for the NVM chip according to the standby power supply is executed, and whether the NVM chip command to be processed can be submitted or not is determined; and assigning a page stripe in response to the NVM chip command that can be submitted for processing.

According to the method for controlling the first or second IO command in the first aspect of the application, the method for controlling the third IO command in the first aspect of the application is provided, if a page stripe is available, the NVM chip command to be processed is submitted to the available page stripe.

According to a method of first or second IO command control of the first aspect of the present application, there is provided a method of fourth IO command control according to the first aspect of the present application, a command queue is provided for each NVM chip, die or logic unit to accommodate NVM chip commands to be processed.

According to the method for controlling the first or second IO command of the first aspect of the application, a fifth method for controlling the IO command of the first aspect of the application is provided, the NVM chip commands to be processed are cached for each NVM chip, and the NVM chip commands are generated according to the NVM chip commands to be processed and sent to the NVM chip.

According to a fifth IO command control method of the first aspect of the present application, there is provided a sixth IO command control method according to the first aspect of the present application, for a pending NVM chip command to access different types of physical pages, specifying different amounts of resource credits depending on a standby power supply capacity.

According to one of the first to sixth IO command control methods of the present application, a seventh IO command control method according to the first aspect of the present application is provided, and a resource credit depending on the amount of power of the backup power is applied according to the type of the physical page to be accessed by the NVM chip command to be processed; and submitting the NVM chip command to be processed in response to the resource credit application success.

According to the seventh IO command control method of the first aspect of the present application, the eighth IO command control method of the first aspect of the present application is provided, if the to-be-processed NVM chip commands access to the physical page of the SLC type memory cell, applying for a first amount of resource credit depending on the amount of the standby power supply; if the NVM chip to be processed is instructed to access the first page of the MLC type memory unit, applying for a second amount of resource credit depending on the power of the standby power supply; and if the NVM chip to be processed commands to access the second page of the MLC type, the resource quota depending on the electric quantity of the standby power supply is not required to be applied.

According to a method of eighth IO command control of the first aspect of the present application, there is provided a method of ninth IO command control according to the first aspect of the present application, the second number being greater than the first number.

According to a method of eighth or ninth IO command control of the first aspect of the present application, there is provided a method of tenth IO command control according to the first aspect of the present application, the second number being twice the first number.

According to one of the methods of eighth to tenth IO command control of the first aspect of the present application, there is provided the method of eleventh IO command control according to the first aspect of the present application, the first page and the second page belonging to the same word line.

According to one of the methods of eighth to eleventh IO command control of the first aspect of the present application, there is provided the method of twelfth IO command control according to the first aspect of the present application, the first page is an MLC LSB page, and the second page is an MLC MSB page.

According to one of the eighth to twelfth IO command control methods of the first aspect of the present application, the thirteenth IO command control method of the first aspect of the present application is provided, after the resource unit is applied for the first NVM chip command to be processed for accessing the first page of the MLC type memory cell, the first NVM chip command to be processed is temporarily cached, after the corresponding NVM chip command to be processed for accessing the second page of the MLC type memory cell is received, the first NVM chip command to be processed and the second NVM chip command to be processed are combined, and the NVM chip command to be processed is generated.

According to one of the eighth to thirteenth IO command control methods of the first aspect of the present application, there is provided the fourteenth IO command control method according to the first aspect of the present application, wherein after the NVM chip command is sent to the NVM chip and the execution on the NVM chip is completed, the resource credit applied for the command of the corresponding NVM chip to be processed is released.

According to one of the methods of eighth to fourteenth IO command control of the first aspect of the present application, there is provided the method of fifteenth IO command control according to the first aspect of the present application, and in response to the application resource line failing, suspending processing of the NVM chip command to be processed.

According to one of the eighth to fifteenth IO command control methods of the first aspect of the present application, there is provided the sixteenth IO command control method according to the first aspect of the present application, and in response to the application resource credit failing, placing the processed NVM chip command into a wait queue.

According to one of the eighth to sixteenth IO command control methods of the first aspect of the present application, there is provided the seventeenth IO command control method according to the first aspect of the present application, wherein the applying for the resource credit is successful if the number of available resource credits is not smaller than the number of applied resource credits.

According to one of the eighth to seventeenth IO command control methods of the first aspect of the present application, there is provided the eighteenth IO command control method according to the first aspect of the present application, wherein after the resource amount is applied successfully, the applied resource amount is subtracted from the number of available resource amounts.

According to one of the eighth to eighteenth IO command control methods of the first aspect of the present application, there is provided the nineteenth IO command control method according to the first aspect of the present application, wherein the applying for the resource credit fails if the number of available resource credits is smaller than the number of applied resource credits.

According to one of the methods of eighth to nineteenth IO command control of the first aspect of the present application, there is provided the method of twentieth IO command control according to the first aspect of the present application, in response to releasing the resource credit, adding the amount of available resources to the amount of released resource credit.

According to one of the methods of eighth through twentieth IO command control of the first aspect of the present application, there is provided the method of twenty-first IO command control according to the first aspect of the present application, in response to all pending NVM chip commands corresponding to the same host command being submitted, sending a confirmation message to the host to indicate that host command execution is complete.

According to a seventh IO command control method of the first aspect of the present application, a twenty-second IO command control method of the first aspect of the present application is provided, if the pending NVM chip commands access a first page of the TLC type memory cell, applying a first amount of spare power supply electric quantity dependent credit; if the NVM chip to be processed is instructed to access the second page of the TLC type memory unit, applying for a second amount of the allowance depending on the electric quantity of the standby power supply; and if the NVM chip to be processed commands to access the third page of the TLC type memory unit, the application of the amount of electricity depending on the standby power supply is not required.

According to a twenty-third IO command control method of the first aspect of the present application, there is provided a twenty-third IO command control method according to the first aspect of the present application, the second number being greater than the first number.

According to a twenty-second or twenty-third IO command control method of the first aspect of the present application, there is provided a twenty-fourth IO command control method according to the first aspect of the present application, the second number being twice the first number.

According to one of the twenty-second to twenty-fourth IO command control methods of the first aspect of the present application, there is provided the twenty-fifth IO command control method according to the first aspect of the present application, the first page and the second page belonging to the same word line.

According to one of the twenty-second to twenty-fifth IO command control methods of the first aspect of the present application, there is provided the twenty-sixth IO command control method according to the first aspect of the present application, the first page is TLC LSB page, the second page is TLC CSB page, and the third page is TLC MSB page.

According to a seventh IO command control method of the first aspect of the present application, a twenty-seventh IO command control method of the first aspect of the present application is provided, if the pending NVM chip commands access the first page of the TLC type memory cell, applying a second amount of the spare power supply-dependent amount of power; if the NVM chip to be processed is instructed to access the second page of the TLC type storage unit, the application of the amount of electricity depending on the standby power supply is not needed; and applying for the first amount of the spare power amount dependent on the third page of the TLC type memory cell if the pending NVM chip commands access to the third page.

According to a twenty-seventh IO command control method of the first aspect of the present application, there is provided a twenty-eighth IO command control method according to the first aspect of the present application, the second number being greater than the first number.

According to a twenty-seventh or twenty-eighth IO command control method of the first aspect of the present application, there is provided a twenty-fourth IO command control method according to the first aspect of the present application, the second number being twice the first number.

According to one of the twenty-seventh to twenty-ninth IO command control methods of the first aspect of the present application, there is provided the thirty-first IO command control method according to the first aspect of the present application, wherein the first page, the second page and the third page belong to the same word line.

According to one of the twenty-seventh to thirty-first IO command control methods of the first aspect of the present application, there is provided the thirty-first IO command control method according to the first aspect of the present application, the first page is TLC LSB page, the second page is TLC CSB page, and the third page is TLC MSB page.

According to one of the twenty-seventh to thirty-first IO command control methods of the first aspect of the present application, the thirty-second IO command control method of the first aspect of the present application is provided, after a resource credit is applied for a first to-be-processed NVM chip command accessing a first page of a memory cell of a TLC type, the first to-be-processed NVM chip command is temporarily cached, after a second to-be-processed NVM chip command accessing a second page of the memory cell of the TLC type corresponding to the first to-be-processed NVM chip command is received, the first to-be-processed NVM chip command and the second to-be-processed NVM chip command are combined, and an NVM chip command is generated.

According to one of the twenty-seventh to thirty-second IO command control methods of the first aspect of the present application, there is provided the thirty-third IO command control method according to the first aspect of the present application, wherein after the resource credit is applied for the third pending NVM chip command accessing the third page of the TLC type memory cell, the NVM chip command is generated.

According to a method for controlling a seventh IO command of the first aspect of the present application, a method for controlling a thirty-fourth IO command of the first aspect of the present application is provided, if the pending NVM chip commands access the first page of the TLC type memory cell, applying a third amount of the spare power supply-dependent amount of power; if the NVM chip to be processed is instructed to access the second page of the TLC type storage unit, the application of the amount of electricity depending on the standby power supply is not needed; and if the NVM chip to be processed commands to access the third page of the TLC type memory unit, the application of the amount of electricity depending on the standby power supply is not required.

According to a thirty-fourth IO command control method of the first aspect of the present application, there is provided a thirty-fifth IO command control method according to the first aspect of the present application, the third number being greater than the second number.

According to a thirty-fourth or thirty-fifth IO command control method of the first aspect of the present application, there is provided a thirty-sixth IO command control method according to the first aspect of the present application, the first page, the second page and the third page belonging to the same word line.

According to one of the thirty-fourth to thirty-sixth IO command control methods of the first aspect of the present application, there is provided the thirty-seventh IO command control method according to the first aspect of the present application, the first page is TLC LSB page, the second page is TLC CSB page, and the third page is TLC MSB page.

According to one of the thirty-fourth to thirty-seventh IO command control methods of the first aspect of the present application, the thirty-eighth IO command control method of the first aspect of the present application is provided, after a resource credit is applied for a first to-be-processed NVM chip command accessing a first page of a memory cell of a TLC type, the first to-be-processed NVM chip command is temporarily cached, after a second to-be-processed NVM chip command accessing a second page of the memory cell of the TLC type and a third to-be-processed NVM chip command accessing a third page of the memory cell of the TLC type corresponding thereto are received, the first to-be-processed NVM chip command, the second to-be-processed NVM chip command and the third to-be-processed NVM chip command are combined, and the NVM chip command is generated.

According to a method of seventh IO command control of the first aspect of the present application, a method of thirty-ninth IO command control according to the first aspect of the present application is provided, if the pending NVM chip commands access a first page of the TLC type memory cell, applying a first amount of the spare power supply-dependent amount of power; if the NVM chip to be processed is instructed to access the second page of the TLC type memory unit, applying for a second amount of the allowance depending on the electric quantity of the standby power supply; and if the NVM chip to be processed commands to access the third page of the TLC type memory unit, the application of the amount of electricity depending on the standby power supply is not required.

According to a thirty-ninth IO command control method of the first aspect of the present application, there is provided a fortieth IO command control method according to the first aspect of the present application, the second number being greater than the first number.

According to a method of forty-first IO command control of the first aspect of the present application, there is provided a method of forty-first IO command control according to the first aspect of the present application, the second number being twice the first number.

According to one of the thirty-ninth to forty-first IO command control methods of the first aspect of the present application, there is provided the forty-second IO command control method according to the first aspect of the present application, wherein the first page, the second page and the third page belong to the same word line.

According to one of the thirty-ninth to forty-second IO command control methods of the first aspect of the present application, there is provided the forty-third IO command control method according to the first aspect of the present application, wherein the first page is a TLC LSB page, the second page is a TLC CSB page, and the third page is a TLC MSB page.

According to one of the thirty-ninth to forty-third IO command control methods of the first aspect of the present application, the forty-fourth IO command control method of the first aspect of the present application is provided, after the resource unit is applied for the second pending NVM chip command accessing the second page of the memory cell of the TLC type is successful, the second pending NVM chip command is temporarily cached, after the third pending NVM chip command accessing the third page of the memory cell of the TLC type corresponding to the second pending NVM chip command is received, the second pending NVM chip command and the third pending NVM chip command are combined, and the NVM chip command is generated.

According to one of the thirty-ninth to forty-fifth IO command control methods of the first aspect of the present application, there is provided the forty-fifth IO command control method according to the first aspect of the present application, wherein after the resource credit is applied for the first NVM chip command to be processed for accessing the first page of the TLC type memory cell, the NVM chip command is generated.

According to one of the methods of the sixth to forty-fifth IO command control according to the first aspect of the present application, there is provided the method of the forty-sixth IO command control according to the first aspect of the present application, wherein if the NVM chip command to be processed is a read command, a fourth amount of spare power supply power dependent credit is applied.

According to a forty-sixth IO command control method of the first aspect of the present application, there is provided a forty-seventh IO command control method according to the first aspect of the present application, the fourth number being smaller than the first number.

According to one of the methods of the sixth to forty-seventh IO command control of the first aspect of the present application, there is provided the method of the forty-eighth IO command control according to the first aspect of the present application, wherein data transmission corresponding to the NVM chip command to be processed from the host to the solid-state storage device is initiated only after the resource amount applied for the NVM chip command to be processed is successful.

According to one of the methods of the sixth to forty-eighth IO command control of the first aspect of the present application, there is provided a method of the forty-ninth IO command control according to the first aspect of the present application, in response to a power-down event occurring, canceling the submitted NVM chip command to be processed indicating an erase operation.

According to a second aspect of the present application, there is provided a first solid state storage device according to the second aspect of the present application, comprising a control unit, an NVM chip and a memory, the control unit being coupled to the NVM chip and the memory, respectively, the control unit comprising a plurality of CPUs therein for performing the method of IO command control according to one of the first to forty-ninth aspects of the present application.

According to a third aspect of the present application, there is provided a first IO command control system according to the third aspect of the present application, including a standby power supply processing module that determines whether a pending NVM chip command can be submitted according to energy that a standby power supply can supply to each NVM chip.

According to a fourth aspect of the present application there is provided a program comprising program code which, when loaded into and executed on a solid state storage device, causes the solid state storage device to carry out a method according to the first aspect of the present application.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following description will briefly introduce the drawings that are required to be used in the embodiments or the description of the prior art, and it is obvious that the drawings in the following description are only some embodiments described in the present application, and other drawings may also be obtained according to these drawings for a person having ordinary skill in the art.

FIG. 1 is a block diagram of a prior art solid state storage device;

FIG. 2 is a flow chart of a command processing method according to an embodiment of the present application;

FIG. 3 is a schematic block diagram of an embodiment of the present application; and

fig. 4 is a flowchart of a command processing method according to an embodiment of the present application.

Detailed Description

The following description of the embodiments of the present application, taken in conjunction with the accompanying drawings, clearly and completely describes the technical solutions of the embodiments of the present application, and it is apparent that the described embodiments are some embodiments of the present application, not all embodiments. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.

For purposes of clarity, commands sent by the host to the solid state storage device are referred to as host commands, while commands sent by the control unit 104 to the NVM chip 105 are referred to as NVM chip commands. In the processing of host commands by control unit 104, there are a variety of intermediate stages, and the commands passed in these intermediate stages are referred to as intermediate commands or NVM chip commands to be processed. The host commands may correspond to one or more intermediate commands or NVM chip commands to be processed, and the host commands may correspond to one or more NVM chip commands. The intermediate command indicates access to a physical page.

Example 1

In response to completion of the host command processing, the control section 104 sends an acknowledgement message to the host. To reduce host-perceived host command processing time, an acknowledgement message is sent to the host before host command processing is complete, and the solid state storage device needs to ensure that the host command corresponding to the sent acknowledgement message is actually completed (e.g., writing the data corresponding to the host command to NVM chip 105).

The NVM chip commands are executed serially at each NVM chip 105 (or die or LUN). To ensure that pending NVM chip commands on each NVM chip 105 can be processed during standby power when the solid state storage device is powered down, it is necessary to control the number of pending NVM chip commands on each NVM chip 105 at any time.

The physical pages of NVM chip 105 include different types, e.g., page SLC (Single Level Cell), page MLC (Multiple Level Cell) MSB (Most Significant Bit), MLC LSB (Least Significant Bit), page TLC (Triple Level Cell) MSB (Most Significant Bit), page TLC (Triple Level Cell) CSB (Central Significant Bit), TLC LSB (Least Significant Bit) page. Each bit of the MLC MSB page is stored in the highest bit of the MLC memory cell, each bit of the MLC LSB page is stored in the lowest bit of the MLC memory cell, each bit of the TLC MSB page is stored in the highest bit of the TLC memory cell, each bit of the TLC CSB page is stored in the middle bit of the TLC memory cell, and each bit of the TLC LSB page is stored in the lowest bit of the TLC memory cell. The time or energy required to write data to different types of physical pages is different, some NVM chips 105 also combine write operations of two or more physical pages on the same memory cell together, and result in such write operations requiring longer time or energy. In a solid state storage device, the type of physical page of the NVM chip 105 being accessed can be identified from the physical address.

As an example, SLC pages of NVM chip 105 may be written with data separately, MLC MSB pages and MLC LSB pages corresponding to the same MLC memory cell need to be written simultaneously, while three physical pages corresponding to the same TLC memory cell need to be written in a combination of one SLC page and two MLC pages, i.e., one of the three physical pages of TLC memory cells (e.g., LSB page) may be written separately, while the other two physical pages (e.g., CSB page and MSB page) need to be written simultaneously. Two physical pages are written simultaneously, meaning that no other commands can be inserted between NVM chips 105 writing data to the two physical pages.

To control the number of NVM chip commands to be processed on each NVM chip 105 at any time and to enable early sending of a confirmation message to the host indicating completion of the host command operation, it is determined whether the NVM chip commands to be processed can be arranged for the NVM chips 105 based on the energy that the backup power supply can provide for each NVM chip 105. Alternatively, if all NVM chip commands corresponding to the host command are scheduled to NVM chip 105, an acknowledgement message may be sent to the host to indicate that the host command operation is complete.

There are various ways to implement the NVM chip commands that arrange for processing to NVM chip 105. For example, a command queue is provided for each NVM chip 105 (or die or LUN) to accommodate NVM chip commands to be processed. As another example, control component 104 provides a media interface controller that receives intermediate commands, caches NVM chip commands pending for each NVM chip 105, and issues NVM chip commands to NVM chips 105. The media interface controller is coupled to the NVM chip 105. The media interface controllers have one or more, each coupled to a respective NVM chip 105.

Fig. 2 is a flowchart of a command processing method according to an embodiment of the present application. As shown in fig. 2, in order to arrange for NVM chip commands to be processed, a reserve power-dependent resource credit allocated to each NVM chip is applied for the intermediate commands (201).

The number of resources needed to access intermediate commands of physical pages of different types of NVM chips 105 varies. For example, the number of resource units allocated to each NVM chip 105 is 30, the number of resource units to be applied by the intermediate command for processing the read physical page is 5, the number of resource units to be applied by the intermediate command for processing the write SLC page is 10, the number of resource units to be applied by the intermediate command for processing the write MLC LSB page is 20, and no unit need be applied when the intermediate command for writing the MLC MSB page is processed. Because the MLC LSB page and the MLC MSB page need to be written in combination, the resource amount is only applied when the intermediate command for writing the MLC LSB page is processed, but the resource amount is not required when the intermediate command for writing the corresponding MLC MSB page is processed, and the resource amount applied for processing the intermediate command for writing the MLC LSB page is used.

For the intermediate command, the physical page type it accesses is identified. If the intermediate command accesses the SLC type physical page (202), a first amount of resource credit is applied (204) based on the amount of resources required to access the SLC type physical page. Only after the resource credit application is successful (206) is the NVM chip command to be processed generated and arranged (208). If the intermediate command accesses the MLC LSB type physical page (203), a second amount of resource credits is applied based on the amount of resources required to access the MLC LSB type physical page (205). If the intermediate command accesses the MLC MSB type physical page (203), no resource credit is required.

Optionally, after applying for a credit for an intermediate command to write an MLC MSB page is successful (206), the intermediate command is temporarily cached, and after receiving the intermediate command corresponding thereto to write an MLC MSB page, the two intermediate commands are combined, generated, and arranged for a pending NVM chip command (208).

Processing of the intermediate commands is continued only after a successful application to the resource credit, e.g., generating and arranging a pending NVM chip command (208), sending the NVM chip command to NVM chip 105 and executing on NVM chip 105 (209), sending an acknowledgement message to the host (2010), and/or freeing the resource credit applied for the corresponding intermediate command (2011). Alternatively, after the NVM chip command is sent to NVM chip 105 and execution on NVM chip 105 is completed, the resources applied for the corresponding intermediate command are released. For example, after the execution of the NVM chip command to write SLC pages is completed, the amount of released resources is 10; after the execution of the NVM chip commands for writing the MLC LSB and the MLC MSB is completed, the amount of released resources is 20.

If the application resource credit fails, processing of the intermediate command is suspended (207). For example, the intermediate command is placed in a waiting queue, and after a sufficient amount of resources appears, the intermediate command is acquired from the waiting queue and processed again.

Applying for a resource credit, for example, if the amount of resource credit allocated to the NVM chip 105 is not less than the amount of resource credit applied, then applying for the resource credit is successful, and subtracting the amount of resource credit applied from the amount of resource credit allocated to the NVM chip 105. If the amount of resource allocated to the NVM chip 105 is smaller than the amount of resource applied, the application of the resource fails and the amount of resource allocated to the NVM chip 105 is kept unchanged.

The resource credit is released (2011), and the amount of resources allocated to NVM chip 105 is added to the released resource credit, for example.

The arranged pending NVM chip commands are sent to NVM chip 105 to execute the NVM chip commands on NVM chip 105 (209). And optionally, when all intermediate commands corresponding to the same host command are processed and a corresponding pending NVM chip command is arranged (208), sending an acknowledgement message (2010) to the host to indicate that host command execution is complete.

Optionally, if the method further includes an intermediate command for writing the TLC page, the intermediate command for writing the TLC LSB page is processed according to the intermediate command for writing the SLC page, the intermediate command for writing the TLC CSB page is processed according to the intermediate command for writing the MLC LSB page, and the intermediate command for writing the TLC MSB page is processed according to the intermediate command for writing the MLC MSB page.

Still alternatively, if an intermediate command to write the TLC page is further included, the intermediate command to write the TLC LSB page is treated as an intermediate command to write the MLC LSB page, the intermediate command to write the TLC CSB page is treated as an intermediate command to write the MLC MSB page, and the intermediate command to write the TLC MSB page is treated as an intermediate command to write the SLC page.

Still alternatively, if the intermediate command to write the TLC page is also included, the amount of resource credit to be applied by the intermediate command to process the write TLC LSB page is 30, and no credit need be applied when processing the intermediate command to write the TLC CSB page or TLC MSB page. When the intermediate command to write the TLC LSB page is received, a third amount of resource credit (e.g., 30) is applied for the intermediate command to write the TLC LSB page, and the intermediate command to write the TLC LSB page is cached, and when the intermediate command to write the TLC CSB page is received, the intermediate command to write the TLC CSB page is continued to be cached without applying credit, and when the intermediate command to write the TLC MSB page is received, the intermediate command to write the TLC MSB page is combined with the cached intermediate command to write the TLC LSB page and the intermediate command to write the TLC CSB page, and a pending NVM chip command is generated and arranged (208).

If the intermediate command is a read command, then a pending NVM chip command is generated and arranged for the intermediate command only after the fourth amount (e.g., 5) of resource credit has been applied for the intermediate command (208).

Still alternatively, for an intermediate command to write a physical page, a DMA transfer from the host to the solid state storage device is initiated to obtain the data to be written after the application of the resource credit is successful.

Due to garbage collection or other operations, NVM chip commands to be processed that indicate an erase operation may be arranged or NVM chip commands that indicate an erase operation may be issued to NVM chip 105. In response to a power down event occurring, canceling the scheduled pending NVM chip commands indicating an erase operation, if an NVM chip command indicating an erase operation has been issued to NVM chip 105 and execution of the NVM chip command indicating an erase operation has not been completed, issuing an erase cancel command or an erase pause command to NVM chip 105 and then issuing other scheduled pending NVM chip commands to NVM chip 105.

Still alternatively, the command processing method shown in FIG. 2 may be implemented for each NVM chip 105 in the solid-state storage device while processing intermediate commands that access the NVM chip. For example, a resource credit is maintained for each NVM chip 105, the resource credits of the respective NVM chips being independent of each other.

Example two

Fig. 3 is a schematic block diagram of an embodiment of the present application. As shown in fig. 3, a large block includes a physical block from each of a plurality of logical units. Preferably, each logic unit (or die or NVM chip 105) provides a physical block for a large block. By way of example, a large block is constructed on every 16 Logical Units (LUNs). Each chunk includes 16 physical blocks, from each of 16 Logical Units (LUNs). In the example of FIG. 2, chunk 0 includes physical chunk 0 from each of the 16 Logical Units (LUNs), while chunk 1 includes physical chunk 1 from each Logical Unit (LUNs). There are a number of other ways to construct a chunk, for example, each logical unit provides 2 or more physical blocks for the chunk. All logical units that provide physical blocks for a large block are referred to as a logical unit group.

As an alternative, page stripes are constructed in large blocks, with physical pages of the same physical address in each Logical Unit (LUN) constituting a "page stripe". In FIG. 3, physical pages 0-0, 0-1, … … and 0-x form page stripe 0, where physical pages 0-0, 0-1, … … are used to store user data and physical pages 0-15 are used to store parity data calculated from all user data within the stripe. Similarly, in FIG. 3, physical pages 2-0, physical pages 2-1 … …, and physical pages 2-x constitute page stripe 2. Alternatively, the physical page used to store the parity data may be located anywhere in the page stripe. Depending on the types of physical pages that make up the page stripe, the page stripe may have different types, e.g., SLC type, MLC LSB type, MLC MSB type, TLC LSB type, TLC, CSB type, and/or TLC MSB type.

To write data to the page stripe, a control unit 104 (see FIG. 1) of the solid state storage device provides a check data calculation unit. Taking the example of calculating the parity data using an exclusive-or operation, for a page stripe including n+1 physical pages, an exclusive-or (e.g., (P0-0) XOR (P0-1) XOR (P0-2) XOR … XOR (P0-14)) is calculated for the user data of the N physical pages, and the calculation result is written to the physical page (e.g., P0-X) storing the parity data for the page stripe. Alternatively, a plurality of check data calculation units (e.g., M) are provided in the control section 104 to write data to M page stripes at the same time.

A resource credit is maintained for the logical unit group that depends on the amount of power of the backup power source. The plurality of pages included in the page stripe are of the same type. The energy or time required to access individual pages on a page stripe is substantially uniform. Furthermore, when using the page stripe, different amounts of resource credits are applied according to the type of the physical page of the page stripe.

To process an intermediate command to write data, a page stripe is allocated for the intermediate command and the available physical pages are retrieved from the page stripe to generate the NVM chip command to be processed. The page stripe includes a plurality of physical pages, and after the page stripe is allocated, for a subsequent intermediate command to write data, the available physical pages are obtained from the allocated page stripe until the available physical pages of the page stripe are exhausted, and then a new page stripe is allocated for the intermediate command.

When allocating page stripes, different amounts of resource credits are applied according to the type of physical pages of the page stripes. And the allocation of page stripes is successful only if the resource credit application is successful.

Fig. 4 is a flowchart of a command processing method according to an embodiment of the present application. As shown in fig. 4, in response to receiving an intermediate command to be processed (401), if there is an allocated page stripe and there is a physical page available in the allocated page stripe (402), generating an NVM chip command to be processed according to the intermediate command and arranging the NVM chip command to be processed to the NVM chip (4010).

If there is no page stripe available (e.g., the physical pages available on the allocated page stripe are exhausted) (402), then a page stripe is allocated for the intermediate command. To allocate a page stripe, a resource credit needs to be applied according to the type of page stripe accessed by the intermediate command (or the physical page types constituting the page stripe).

For example, when a page stripe needs to be allocated, the amount of resource to be applied by the intermediate command to write the SLC page is 10, the amount of resource to be applied by the intermediate command to write the MLC LSB page is 20, and when the intermediate command to write the MLC MSB page is processed, the application of the amount is not required. Since the MLC LSB page and the MLC MSB page need to be written in combination, the resource amount is applied only when the intermediate command to write the MLC LSB page is processed, and the resource amount is not applied when the intermediate command to write the corresponding MLC MSB page is processed, but the resource amount applied when the page stripe is allocated for processing the intermediate command to write the MLC LSB page is used.

As a further example, when a page stripe needs to be allocated, the intermediate command to write TLC LSB page is processed as the intermediate command to write SLC page (the amount of resource to be applied is 10), the intermediate command to write TLC CSB page is processed as the intermediate command to write MLC LSB page (the amount of resource to be applied is 20), and the intermediate command to write TLC MSB page is processed as the intermediate command to write MLC MSB page (no resource amount to be applied).

As yet another example, when a page stripe needs to be allocated, the middle command to write the TLC LSB page is treated as a middle command to write the MLC LSB page (the amount of resource to be applied is 20), the middle command to write the TLC CSB page is treated as a middle command to write the MLC MSB page (no resource amount to be applied is required), and the middle command to write the TLC MSB page is treated as a middle command to write the SLC page (the amount of resource to be applied is 10).

As yet another example, when a page stripe needs to be allocated, the number of resource credits to be applied by an intermediate command to write a TLC LSB page is 30, while when an intermediate command to write a TLC CSB page or TLC MSB page is processed, no credits need to be applied. When the intermediate command of the write TLC LSB page is received, the resource limit with the application number of 30 is applied for the intermediate command of the write TLC LSB page, when the intermediate command of the write TLC CSB page is received, the intermediate command of the write TLC CSB page is continuously cached without applying the limit, when the intermediate command of the write TLC MSB page is received, the application of the limit is not required, and the intermediate command of the write TLC MSB page, the cached intermediate command of the write TLC LSB page and the intermediate command of the write TLC CSB page are combined to generate and arrange the NVM chip command to be processed.

If the intermediate command is a read command, applying for a resource amount of 5 for each read command, without considering the page stripe accessed by the read command, generating and arranging an NVM chip command to be processed for the intermediate command after the resource amount is successfully applied.

Referring back to FIG. 4, for the intermediate command, the page stripe type it accesses is identified. If the intermediate command accesses the SLC type page stripe (403), a first amount of resource credit is applied (405) based on the amount of resources required to access the SLC type page stripe. Only after the resource credit application is successful (407), a page stripe is allocated for the intermediate command (409), and the pending NVM chip command is generated and arranged according to the allocated page stripe (4010). If the intermediate command accesses the MLC LSB type page stripe (404), a second amount of resource credits is applied based on the amount of resources required to access the MLC LSB type page stripe (405). If the intermediate command accesses the MLC MSB type page stripe (404), the resource allocation for the corresponding MLC LSB type page stripe is used without applying for the resource allocation.

After applying for a credit for an intermediate command to write an MLC LSB page (407), allocating a page stripe for the intermediate command to write an MLC LSB page (409), and temporarily caching the intermediate command, after receiving the intermediate command to write an MLC MSB page corresponding thereto, combining the two intermediate commands, generating and arranging an NVM chip command to be processed (4010).

In response to scheduling the NVM chip command to be processed (4010), the NVM chip command is sent to NVM chip 105 and the NVM chip command is executed on NVM chip 105 (4011), and an acknowledgement message is sent to the host (4012). The resources applied for the page stripe are released (4013) in response to the complete SLC page stripe being written with data, and/or the resource credit applied for the page stripe is released (4013) in response to the complete MLC LSB page stripe and the corresponding MLC MSB page stripe being written with data.

If the application resource credit fails, processing of the intermediate command is suspended (408). For example, the intermediate command is placed in a waiting queue, and after a sufficient amount of resources appears, the intermediate command is acquired from the waiting queue and processed again.

The arranged NVM chip commands to be processed are sent to NVM chip 105 to execute the NVM chip commands on NVM chip 105 (4011). And optionally, when all intermediate commands corresponding to the same host command are processed and a corresponding pending NVM chip command is arranged (4010), sending a confirmation message to the host (4012) to indicate that the host command execution is complete.

While preferred embodiments of the present application have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiments and all such alterations and modifications as fall within the scope of the application. It will be apparent to those skilled in the art that various modifications and variations can be made in the present application without departing from the spirit or scope of the application. Thus, if such modifications and variations of the present application fall within the scope of the claims and the equivalents thereof, the present application is intended to cover such modifications and variations.

Claims (9)

1. A method of IO command control, comprising:

determining whether to submit an NVM chip command to be processed according to energy provided by the standby power supply for the NVM chip;

in order to arrange the NVM chip command to be processed, applying for the resource amount which is allocated to the NVM chip and depends on the electric quantity of the standby power supply according to the type of physical pages which form page stripes accessed by the NVM chip command to be processed or the type of page stripes accessed by the NVM chip command, and maintaining the resource amount for each NVM chip;

submitting an NVM chip command to be processed in response to successful resource credit application;

the method comprises the steps that an NVM chip command to be processed is a command transmitted by a control component in an intermediate stage of a host command processing process, wherein the host command corresponds to one or more NVM chip commands to be processed, and the host command corresponds to one or more NVM chip commands;

further comprises:

and caching the NVM chip commands to be processed for each NVM chip, combining the NVM chip commands to be processed to generate an NVM chip command, and transmitting the NVM chip command to the NVM chip.

2. The method of IO command control according to claim 1, wherein if a page stripe is allocated for the NVM chip command to be processed, performing the step of determining whether to submit the NVM chip command to be processed based on energy provided by the standby power supply to the NVM chip; and

In response to submitting a pending NVM chip command, a page stripe is allocated.

3. The method of IO command control according to claim 1 or 2, wherein,

if the NVM chip to be processed commands to access the physical page of the SLC type memory unit, applying for a first amount of resource credit depending on the electric quantity of the standby power supply;

if the NVM chip to be processed is instructed to access the first page of the MLC type memory unit, applying for a second amount of resource credit depending on the power of the standby power supply; and

if the NVM chip to be processed is instructed to access the second page of the MLC type, the resource amount depending on the electric quantity of the standby power supply is not required to be applied.

4. The method of IO command control according to claim 3, wherein after applying for a resource amount for a first NVM chip command to be processed for accessing a first page of a memory cell of MLC type is successful, caching the first NVM chip command to be processed, and after receiving a NVM chip command to be processed for accessing a second page of a memory cell of MLC type corresponding thereto, combining the first NVM chip command to be processed with the second NVM chip command to be processed to generate the NVM chip command.

5. The method of IO command control according to claim 1 or 2, wherein,

If the NVM chip to be processed is instructed to access the first page of the TLC type memory unit, applying a third amount of the allowance depending on the electric quantity of the standby power supply;

if the NVM chip to be processed is instructed to access the second page of the TLC type storage unit, the application of the amount of electricity depending on the standby power supply is not needed; and

if the NVM chip to be processed is instructed to access the third page of the TLC type memory cell, the application of the amount of power dependent on the standby power is not required.

6. The method of IO command control according to claim 1 or 2, wherein data transfer corresponding to the NVM chip command to be processed from the host to the solid state storage device is initiated only after the resource credit applied for the NVM chip command to be processed is successful.

7. The method of IO command control of claim 1 or 2, wherein in response to a power down event occurring, canceling the submitted NVM chip command to be processed indicating an erase operation.

8. A solid state storage device comprising a control unit, an NVM chip and a memory, the control unit being coupled to the NVM chip and the memory, respectively, the control unit comprising a plurality of CPUs therein for performing the method according to one of claims 1-7.

9. An IO command control system, comprising:

the standby power supply processing module is used for determining whether to submit an NVM chip command to be processed according to the energy provided by the standby power supply for each NVM chip;

in order to arrange the NVM chip command to be processed, applying for the resource amount which is allocated to the NVM chip and depends on the electric quantity of the standby power supply according to the type of physical pages which form page stripes accessed by the NVM chip command to be processed or the type of page stripes accessed by the NVM chip command, and maintaining the resource amount for each NVM chip;

submitting an NVM chip command to be processed in response to successful resource credit application;

the method comprises the steps that an NVM chip command to be processed is a command transmitted by a control component in an intermediate stage of a host command processing process, wherein the host command corresponds to one or more NVM chip commands to be processed, and the host command corresponds to one or more NVM chip commands;

further comprises:

and caching the NVM chip commands to be processed for each NVM chip, combining the NVM chip commands to be processed to generate an NVM chip command, and transmitting the NVM chip command to the NVM chip.