CN108647368A - Partially dynamical reconfiguration system and method based on FPGA - Google Patents
Partially dynamical reconfiguration system and method based on FPGA Download PDFInfo
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Abstract
The present invention provides a kind of partially dynamical reconfiguration system and method based on FPGA, including reconstruction task development model, ICAP controllers and storage subsystem；Reconstruction task development model includes software task, hardware task and committal charge；Software task is the exploitation based on Linux multithreadings, and hardware task is the logic circuit realized by VHDL for having interface specification, and committal charge is the Linux threads of lightweight, can be as the identically controlled hardware task of control software task by committal charge；ICAP controllers are made of dma controller and ICAP control logics；Storage subsystem is made of additional controller, memory management unit, Memory Controller Hub, task moderator and burst access length transition device.The present invention is realized carries out data interaction for hardware task and system software layer, reduces the difficulty of reconstruction applications exploitation, reduces direct operation of the user to device bottom hardware, accelerate the development rate of reconstruction applications.
Description
(1) technical field：
The present invention is based on FPGA, { FPGA is Field Programmable Gate Array (field programmable gate array)
Abbreviation partially dynamical reconfiguration system, be a kind of embedded OS of the dynamic restructuring technology based on FPGA, especially
It is a kind of dynamic restructuring technology development platform based on embedded Linux system, realizes that the quick of dynamic restructuring technology secondary opens
Hair and application, belong to field of computer technology.
(2) background technology：
Advantage of the dynamic restructuring technology in terms of Design of Digital Circuit all has in many research fields to be worth, but due to
It is closely bound up with the logical resource of FPGA device bottom, at the same the collection of current FPGA on a large scale up to more than million gate leves and
The type of Resources on Chip is also more and more, thus, which faces following problem in popularization and application：
(1) flexibility is poor, real-time is low
Dynamic restructuring technology relies heavily on the development kit and tool of FPGA manufacturers offer, and these are not propped up
It holds user and secondary development is carried out according to functional requirement, while corresponding software and hardware programming interface not being provided, user can only be according to finger
Fixed development process carries out simple reconstitution experiments, this weakens the flexibility of reconfiguration system.Further, since FPGA suppliers carry
The development kit of confession can not carry out Real-Time Scheduling to restructuring procedure, so that reconstruct inefficiency, reconfiguration technique lack real-time
Property.
(2) the communication mechanism of reconstruct hardware and upper layer software (applications) is lacked
In Design of Digital Circuit, it is the necessary of large scale digital circuit that bottom hardware carries out data interaction with upper layer software (applications)
Road.In dynamic restructuring technology application process, the Configuration design of bottom hardware is distributed in due to a lack of the communication with upper layer software (applications)
Mechanism so that reconstruction applications are often detached from software progress, this largely reduces the characteristic of reconfiguration technique secondary development, with
And the possibility of reconfiguration technique and embedded system connected applications.
(3) invention content：
The present invention provides a partially dynamical reconfiguration system based on FPGA, the purpose is to：It provides to the user and is appointed by hardware
The programming model that business, software task and committal charge are constituted, and the dynamic of hardware task is added by the realization of dynamic restructuring technology
It carries, has designed and Implemented the storage subsystem for carrying out data interaction with system software layer for hardware task.The system drops
The difficulty of low reconstruction applications exploitation, reduces direct operation of the user to device bottom hardware, accelerates opening for reconstruction applications
Send out speed.
The present invention provides a partially dynamical reconfiguration system based on FPGA, and technical solution is：In built-in Linux system
On the multi-thread programming model basis of system, in conjunction with the partial dynamic reconstruction property of FPGA, devise based on hardware task, software
The reconstruct development model of task and the task of commission, and dynamic load of the High Speed ICs AP controllers for hardware task is devised,
Realize that the software upper layer of hardware task and reconfiguration system carries out data interaction finally by the storage subsystem of exploitation.
A kind of framework of the partially dynamical reconfiguration system based on FPGA of the present invention is divided into three parts：Referring to Fig. 1, by
Reconstruction task development model 1 on linux kernel, the ICAP controllers 2 positioned at fpga logic resource area and storage subsystem
3 composition of system；ICAP { ICAP is the abbreviation of (the inside configuration port) Internal Configuration Access Port } control
Device 2 processed is by DMA { DMA is the abbreviation of Direct Memory Access (direct memory access) } controllers 4 and ICAP controllers 5
Composition；Storage subsystem 3 is by additional controller 6, memory management unit 7, Memory Controller Hub 8, task moderator 9 and burst access
Length transition device 10 forms；
Dma controller 4 in ICAP controllers by receiving the request of processor system PS, complete bit configuration file from
It is inside stored to the load of ICAP controllers, while configuration file is loaded into transition state machine in place.Additional control in storage subsystem
Device 6 processed realizes the interconnection with processor system by AXI buses, and the status information of storage subsystem 3 is returned to processor
System, while access address is sent to memory management unit 7, memory management unit 7 controls Memory Controller Hub 8 and realizes that access is empty
To the conversion of physical address, task president device 9 selects hardware task under the control of Memory Controller Hub 8, prominent for quasi- address
Hair accesses length transition device 10 and converts and transmit to memory management unit 7 to the access address that task moderator 9 transmits.
Linux semaphores interface, dynamic memory management, module drive, multithreading lock mechanism and other library texts in Fig. 1
Part uses the software program that open source linux kernel is provided, application software layer tune by way of headers and libraries file
With linux kernel, the calling to port and bottom controller is realized.
Reconstruction task development model 1, including software task, hardware task and committal charge；Software task is to be based on Linux
The exploitation of multithreading, hardware task are the logic circuits realized by VHDL for having interface specification, and committal charge is lightweight
Linux threads, can be as the identically controlled hardware task of control software task by committal charge；
ICAP controllers 2 are as follows to external port connection：
ICAP controllers 2, which are realized, to be stored in external partial bit configuration file dynamic load, by reconfiguration system
The control port on upper layer is defined as follows：Referring to Fig. 2, reconfiguration system is interconnected based on AXI buses, in order to make full use of
AXI bus resources, ICAP controllers 2 are communicated with CPU by two AXI interfaces, and port S_AXI_HP 201 is used for from CPU
End reads bit configuration fileinfo and is loaded into the ports ICAP, and port M_AXI_GP 202 is an AXI4LITE interface, uses
In the order for receiving processor system PS and the configuration being reconstructed and initialization operation.The user logic region parts PL of Fig. 2
It is made of AXI bus bars, dma controller, position transition state machine and ICAP controllers.AXI bus bars are by processor system
PS and user logic region PL are attached, to realize the transmission of instruction and data.Dma controller control port S_AXI_HP
1, it will be in the configuration file load of memory in place transition state machine；Position transition state machine be used for the configuration information of configuration file into
Line position is overturn, to ensure being normally carried out for configuration；Realize the dynamic load to configuration file in the ports ICAP.
Storage subsystem 3 is as follows to external port connection：
Referring to Fig. 3, port 306 is task moderator 301 reads fifo, task moderator for controlling hardware task
301 read data, end from hardware task fifo { fifo is the abbreviation of first in first out (First Input First Output) }
Mouthfuls 307 be that task moderator 301 is written data into hardware task fifo, and port 308 is task moderator 301 to burst access
Unconverted virtual address is written in converter 305, and port 309 is that number is written to task moderator 301 in Memory Controller Hub 302
According to port 3010 is the data that task moderator 301 is written that hardware task is written to Installed System Memory to Memory Controller Hub 302, end
Mouthfuls 3011 be memory management unit 304 to 302 writing commands of Memory Controller Hub and address, and port 3012 is memory management unit
304 are written page table walks result address to Memory Controller Hub 302, and port 3013 is memory management unit 304 to Memory Controller Hub
302 write-in physical address, port 3014 are that additional controller 303 sends base address to memory management unit 304, and port 3015 is
Additional controller 303 obtains 304 erroneous address information of memory management unit, and port 3016 is that additional controller 303 obtains memory
Administrative unit 304TLB { TLB is the abbreviation of Translation Lookaside Buffer (transition detection buffering area) } hit letters
Breath, port 3017 are that additional controller 303 obtains memory management unit 304TLB to find number, and port 3018 is additional control
Device 303 sends reset signal to hardware task fifo, and port 3019 is that additional controller 303 is sent to memory management unit 304
Signal is retried, port 3020 is that additional controller 303 sends translation table base address to memory management unit 304, and port 3021 is
Transformed virtual address is written to memory management unit 304 in burst access converter 305, and port 3022 is controller to memory
Controller 302 is written data and page table information, port 3023 be processor to additional controller 303 be written processor instruction and into
Journey base address.Include port 306-3010 in task moderator 301；Memory Controller Hub 302 includes port 3011-3013；It is additional
Controller 303 includes port 3014-3020；Memory management unit 304 includes port 3011-3013,3019,3020 and 3021；
Burst access converter 305 includes port 308 and 3021.
In reconfiguration system operational process, carried out according to following reconstructing method：
User proposes reconstruction task request to reconfiguration system, and request content includes this reconstruct hardware task for including and soft
Part task number, the hardware task quantity that reconfiguration system is asked according to user are matched hardware task bit by ICAP controllers
File is set to be reconfigured to inside FPGA from external storage；Corresponding bit configuration file is the PlanAhead by Xilinx
Too development simultaneously generates, and is stored in external memory；While hardware task is established, system is that each hardware task is built
Corresponding committal charge is found, carries out the interaction of data and instruction with upper-level system for hardware task；At the same time, it establishes corresponding
The software task of quantity is used to execute calculating task parallel with hardware task.In restructuring procedure, hardware task is in local completion
Then treated data forwarding is arrived system software upper layer, so as to other software times by the processing of data by storage subsystem
Business or hardware task are called, and overall calculating task is finally completed.
The present invention is based on the partially dynamical reconfiguration system of FPGA, have the advantages that following good effect and：
1. by the partially dynamical reconfiguration system of FPGA, system-level application and development is provided using reconfiguration technique for user
Platform reduces the development difficulty brought by user's operation bottom hardware, shortens the period of reconfiguration technique exploitation；
2. providing the reconstruct development model of task based access control, user is facilitated to carry out secondary development using dynamic restructuring technology；
3. developing the storage subsystem that hardware task carries out data interaction with system upper layer, hardware task data are shortened
The interactive time improves the real-time of reconfiguration system；
4. devise take up less resources, the ICAP controllers that configuration speed is fast, improve the configuration speed of hardware task.
(4) it illustrates：
Fig. 1 is the partially dynamical reconfiguration overall system architecture the present invention is based on FPGA.
Fig. 2 is ICAP controller architectures figure of the present invention.
Fig. 3 is storage subsystem IP kernel of the present invention organisational chart.
Fig. 4 is the partially dynamical reconfiguration working-flow figure the present invention is based on FPGA.
Fig. 5 is present invention reconstruct hardware task structure chart.
Fig. 6 is the schematic diagram of sequencer procedure.
Fig. 7 is the result figure of 7 hardware tasks operation.
(5) specific implementation mode：
The present invention provides a partially dynamical reconfiguration system based on FPGA, the purpose is to：It provides to the user and is appointed by hardware
The programming model that business, software task and committal charge are constituted, and the dynamic of hardware task is added by the realization of dynamic restructuring technology
It carries, has designed and Implemented the storage subsystem for carrying out data interaction with system software layer for hardware task.The system drops
The difficulty of low reconstruction applications exploitation, reduces direct operation of the user to device bottom hardware, accelerates opening for reconstruction applications
Send out speed.
The present invention provides a partially dynamical reconfiguration system based on FPGA, and technical solution is：In built-in Linux system
On the multi-thread programming model basis of system, in conjunction with the partial dynamic reconstruction property of FPGA, devise based on hardware task, software
The reconstruct development model of task and the task of commission, and dynamic load of the High Speed ICs AP controllers for hardware task is devised,
Realize that the software upper layer of hardware task and reconfiguration system carries out data interaction finally by the storage subsystem of exploitation.
The framework of dynamic reconfiguration system is divided into three parts：By on linux kernel reconstruct development task model 1, be located at
The ICAP controllers 2 and storage subsystem 3 of fpga logic resource area form；ICAP controllers 2 are by dma controller 4 and ICAP
Controller logic 5 forms；Storage subsystem is by additional controller 6, memory management unit 7, Memory Controller Hub 8, task moderator 9
It is formed with burst access converter 10；
Reconstruction task development model, including software task, hardware task and committal charge, software task is to be based on Linux
The exploitation of multithreading, hardware task are the logic circuits realized by VHDL for having interface specification, and committal charge is lightweight
Linux threads, can be as the identically controlled hardware task of control software task by committal charge；
Fig. 5 please be read, hardware task is made of a data synchronous state machine 501 and user logic 502.Data synchronous regime
Machine is for synchronization hardware task and system interface and the data exchange process of storage system interface.First hardware task pass through to
The order of data address is read in write-in in o_osif504, and waits until that data address is put into i_osif 503 by system always
In, hardware task reads i_osif, and enters next state.The virtual address got is written to o_ by hardware task
In memif 506, then waits for storage system to access Installed System Memory and write data into i_memif 505, from i_memif
Hardware task local is read in 505, is handled accordingly.After waiting for that user logic completes data processing, final data
Synchronous state machine writes data into o_memif 506, completes corresponding data interaction.Data synchronous state machine 501 is from interior
Deposit after obtaining data, to user logic transmission data and executing instruction, for logic 502 locally complete data processing it
Instruction is completed in backward data synchronous state machine transmission data processing, and is transmitted data in data synchronous state machine 501.
ICAP controllers 2 are as follows to external port connection：
ICAP controllers 2, which are realized, to be stored in external partial bit configuration file dynamic load, by reconfiguration system
The control on upper layer, port definition are as follows：Reconfiguration system is interconnected based on AXI buses, in order to make full use of AXI buses to provide
Source, ICAP controllers 2 are communicated with system CPU by two AXI interfaces, and port 201S_AXI_HP is used to read from the ends CPU
Bit configuration fileinfo is simultaneously loaded into the ports ICAP, and the port ports M_AXI_GP 202 are an AXI4LITE interfaces, for connecing
Receive the order of PS and the configuration being reconstructed and initialization operation.
Storage subsystem 3 is as follows to external port connection：
Referring to Fig. 3, port 306 is task arbitration, 301 read data from hardware task fifo, and port 307 is task
Data are written into hardware task fifo for moderator 301, and port 308 is that task moderator 301 is written to burst access converter
Unconverted virtual address, port 309 are that data are written to task moderator 301 in Memory Controller Hub 302, and port 3010 is to appoint
The data that hardware task is written to Installed System Memory are written to Memory Controller Hub 302 for business moderator 301, and port 3011 is memory management
For unit 304 to 302 writing commands of Memory Controller Hub and address, port 3012 is memory management unit 304 to Memory Controller Hub 302
Page table walks result address is written, port 3013 is that physical address, end is written to Memory Controller Hub 302 in memory management unit 304
Mouth 3014 is that additional controller 303 sends base address to memory management unit 304, and port 3015 is that additional controller 303 obtains
304 erroneous address information of memory management unit, port 3016 are that additional controller 303 obtains memory management unit 304TLB hits
Information, port 3017 are that additional controller 303 obtains memory management unit 304TLB to find number, and port 3018 is additional control
Device 303 processed sends reset signal to hardware task fifo, and port 3019 is that additional controller 303 is sent out to memory management unit 304
It send and retries signal, port 3020 is that additional controller 303 sends translation table base address, port 3021 to memory management unit 304
It is that transformed virtual address is written to memory management unit 304 in burst access converter 305, port 3022 is that controller is inside
Memory controller 302 is written data and page table information, port 3023 be processor to additional controller 303 be written processor instruction and
Process base address.
In reconfiguration system operational process, carried out according to following reconstructing method：
As shown in figure 4, user proposes that reconstruction task request, request content include the hardware times that this reconstruct includes to system
Business and software task number, the hardware task quantity that reconfiguration system is asked according to user, by ICAP controllers by hardware task
Bit configuration file is reconfigured to from external storage inside FPGA；Corresponding bit configuration file is by Xilinx
PlanAhead too developments simultaneously generate, and are stored in external memory；While hardware task is established, system is each
Hardware task establishes corresponding committal charge, carries out the interaction of data and instruction with upper-level system for hardware task；It is same with this
When, the software task for establishing respective numbers is used to execute calculating task parallel with hardware task.In restructuring procedure, hardware task
In the processing for locally completing data, then by storage subsystem will treated data forwarding to system software upper layer, so as to
Other software task or hardware task are called, and overall calculating task is finally completed.
In reconfiguration system operational process, storage subsystem executes according to the following steps：
During hardware task reads data to storage system, after arbitration, task moderator 301 will read data
Address and reading length are sent to burst access converter 305, and burst access converter 305 is according to the size of current page to reading
It takes address to be converted, converts the address into short address to adapt to the size of memory page.Burst access converter 305 will be converted
Address afterwards is sent to memory management unit 304, and memory management unit 304 is obtained by additional controller 303 from CPU current living
Benchmark of the translation table base address of dynamic process as following address conversion.Memory management unit 304 is examined in local conversion first
It surveys in buffer area and searches corresponding address information, if finding corresponding address information in TLB, the address found is believed
Breath generates logic back to physical address, if not finding corresponding information in TLB, memory management unit 304 will
It entrusts Memory Controller Hub 302 to inquire address information to CPU, and is returned the intermediate address information that physical address relies on is generated, so
Corresponding physical address is generated in memory management unit 4 afterwards, and physical address is sent to Memory Controller Hub 302, by interior
Memory controller 302 reads the data in physical address to CPU, and data are returned to hardware task by AXI buses.
During data are written in hardware task storage system, after arbitration, task moderator 301 will be with will writing data
It location and writes data length and is sent to burst access converter 305, burst access converter 305 is according to the size of current page to writing
Address is converted, and converts the address into short address to adapt to the size of memory page.The address translation process of write operation and reading
What is operated is consistent.Memory Controller Hub 302 will write physical address and be sent to CPU, and it is ready that CPU replys Memory Controller Hub write address
Signal, then hardware task data are written by physical address of the task moderator 301 into Installed System Memory.
Functional verification is carried out to system using " software task+hardware task+bubble sort+merger sequence " algorithm.First
The quantity of software task and hardware task that a certain number of out of order data are specified according to user is grouped, and is generated corresponding
Software and hardware bubble sort task, these tasks complete packet sequencing after, reconfiguration system utilize MERGING/SORTING ALGORITHM pair
Grouped data merges, and then completes the sequence of total data, and Fig. 6 is the schematic diagram of sequencer procedure.
In verification process, user is sent out by host computer serial ports to the reconfiguration system run on FPGA system plate first
RECONFIGURATION REQUEST is sent, which includes to reconstruct included hardware Sorting task and software Sorting task quantity, and reconfiguration system receives
The sequencing requests of user, and according to the quantity of specified software and hardware Sorting task, read and stored by Network File System
Host computer specified path reconstruction task configuration file and dynamic recognition is completed by ICAP controllers, and to system Shen
Please specified quantity software task, utilize software and hardware bubble sort task, complete grouped data sequence；Secondly grouping is arranged
Sequence result is transmitted to system upper layer by storage subsystem, and is sorted by software merger the whole of paired data that sorted, so
The data completed afterwards to sequence verify, and export the temporal information in sequencer procedure finally by serial ports, Fig. 77
The result figure of a hardware task operation.
Claims (7)
1. a kind of partially dynamical reconfiguration system based on FPGA, the system are divided into three parts：Appointed by the reconstruct on linux kernel
Business development model, ICAP controllers and the storage subsystem composition positioned at fpga logic resource area；It is characterized in that：
The reconstruction task development model, including software task, hardware task and committal charge；Software task is to be based on Linux
The exploitation of multithreading, hardware task are the logic circuits realized by VHDL for having interface specification, and committal charge is lightweight
Linux threads, can be as the identically controlled hardware task of control software task by committal charge；
The internal configuration port ICAP controllers are made of direct memory access dma controller and ICAP control logics；
The storage subsystem is long by additional controller, memory management unit, Memory Controller Hub, task moderator and burst access
Spend converter composition；
Shown dma controller completes bit configuration file and is stored to ICAP controls from interior by the request of reception processor system PS
The load of device, while configuration file is loaded into transition state machine in place；Additional controller is realized and processor system by AXI buses
The interconnection of system, and the status information of storage subsystem is returned into processor system, while access address is sent to memory pipe
Unit is managed, memory management unit controls Memory Controller Hub and realizes access virtual address to the conversion of physical address, task president's device
Hardware task is selected under the control of Memory Controller Hub, the visit that burst access length transition device transmits task moderator
Ask that address converts and transmit to memory management unit.
2. the partially dynamical reconfiguration system according to claim 1 based on FPGA, it is characterised in that：ICAP controllers 2 are right
External port connection is：ICAP controllers, which are realized, to be stored in external partial bit configuration file dynamic load, by
The control port on reconfiguration system upper layer is defined as follows：Reconfiguration system is interconnected based on AXI buses, in order to make full use of AXI
Bus resource, ICAP controllers are communicated with CPU by two AXI interfaces, and port S_AXI_HP is used to read ratio from the ends CPU
Special profile information is simultaneously loaded into the ports ICAP, and port M_AXI_GP is an AXI4LITE interface, for receiving processor
The order of system PS and the configuration being reconstructed and initialization operation；The parts user logic region PL are by AXI bus bars, DMA
Controller, position transition state machine and ICAP controllers are constituted；AXI bus bars are by processor system PS and user logic region PL
It is attached, to realize the transmission of instruction and data；Dma controller control port S_AXI_HP, the configuration file of memory is added
It is downloaded in a transition state machine；Position transition state machine is used to carry out bit flipping to the configuration information of configuration file, ensures configuration
It is normally carried out；Realize the dynamic load to configuration file in the ports ICAP.
3. the partially dynamical reconfiguration system according to claim 1 based on FPGA, it is characterised in that：Storage subsystem is external
Port connection is：First port is task moderator reads fifo for controlling hardware task, and task moderator is from hardware
Data are read in task First Input First Output fifo, second port is that data are written into hardware task fifo in task moderator,
Third port is that unconverted virtual address is written to burst access converter for task moderator, and the 4th port is Memory control
Data are written to task moderator in device, and fifth port is that task moderator is written to system to Memory Controller Hub write-in hardware task
The data of memory, the 6th port are memory management units to Memory Controller Hub writing commands and address, and the 7th port is memory pipe
It manages unit and page table walks result address is written to Memory Controller Hub, the 8th port is that memory management unit is written to Memory Controller Hub
Physical address, the 9th port are that additional controller sends base address to memory management unit, and the tenth port is that additional controller obtains
It is that additional controller obtains memory management unit transition detection buffering to take memory management unit erroneous address information, the tenth Single port
Area's TLB hit information, the tenth Two-port netwerk are that additional controller obtains memory management unit TLB to find number, the 13rd port
It is that additional controller sends reset signal to hardware task fifo, the 14th port is that additional controller is sent out to memory management unit
It send and retries signal, the 15th port is that additional controller sends translation table base address to memory management unit, and the 16th port is
Transformed virtual address is written to memory management unit in burst access converter, and the 17th port is controller to Memory control
Data and page table information is written in device, and the 18th port is that processor instruction and process base is written to additional controller in processor
Location.
4. the partially dynamical reconfiguration system according to claim 1 based on FPGA, it is characterised in that：Hardware task is by one
Data synchronous state machine and user logic are constituted；Data synchronous state machine is for synchronization hardware task and system interface and storage
The data exchange process of system interface；Hardware task reads the order of data address, and one by being written into o_osif first
Directly wait until that data address is put into i_osif by system, hardware task reads i_osif, and enters next state；Firmly
The virtual address got is written in o_memif by part task, and storage system is then waited for access Installed System Memory and by data
It is written in i_memif, hardware task local is read from i_memif, is handled accordingly；Wait for user logic to data
After processing is completed, final data synchronous state machine writes data into o_memif, completes corresponding data interaction；Data
Synchronous state machine to user logic transmission data and executes instruction after obtaining data in memory, for logic local complete
Instruction is completed at the backward data synchronous state machine transmission data processing of data processing, and transmits data to data synchronous regime
In machine.
5. a kind of partially dynamical reconfiguration method based on FPGA, it is characterised in that：User proposes that reconstruction task is asked to reconfiguration system
It asks, request content includes that the hardware task that this reconstruct includes and software task number, reconfiguration system are asked hard according to user
Hardware task bit configuration file is reconfigured to from external storage inside FPGA by part task quantity by ICAP controllers；
Corresponding bit configuration file is the PlanAhead too developments by Xilinx and generates, and is stored in external memory；
While hardware task is established, system is that each hardware task establishes corresponding committal charge, is used for hardware task and upper layer
System carries out the interaction of data and instruction；At the same time, the software task of respective numbers is established for being held parallel with hardware task
Row calculating task；In restructuring procedure, then hardware task will be handled in the processing for locally completing data by storage subsystem
Data forwarding afterwards is finally completed overall calculating to system software upper layer so that other software task or hardware task are called
Task.
6. the partially dynamical reconfiguration method according to claim 5 based on FPGA, it is characterised in that：Storage subsystem according to
Following step executes：During hardware task reads data to storage system, after arbitration, task moderator will be read
Data address and reading length are sent to burst access converter, and burst access converter is according to the size of current page to reading
Address is converted, and converts the address into short address to adapt to the size of memory page；Burst access converter will be transformed
Address is sent to memory management unit, and memory management unit obtains the conversion of current active process by additional controller from CPU
Benchmark of the table base address as following address conversion；Memory management unit searches phase in local transition detection buffer area first
The address information found is returned to physical address by the address information answered if finding corresponding address information in TLB
Logic is generated, if not finding corresponding information in TLB, memory management unit will entrust Memory Controller Hub to CPU
Address information is inquired, and is returned the intermediate address information that physical address relies on is generated, is then generated in memory management unit
Corresponding physical address, and physical address is sent to Memory Controller Hub, it is read in physical address to CPU by Memory Controller Hub
Data, and by data by AXI buses return to hardware task.
7. the partially dynamical reconfiguration method according to claim 5 based on FPGA, it is characterised in that：It is stored in hardware task
During data are written in system, after arbitration, task moderator, which will write data address and write data length, is sent to burst
Converter is accessed, burst access converter is converted write address according to the size of current page, converted the address into shortly
Location is to adapt to the size of memory page；The address translation process of write operation and read operation it is consistent；Memory Controller Hub will write physics
Address is sent to CPU, and CPU replys Memory Controller Hub write address standby ready signal, and then hardware task passes through task moderator
Data are written in physical address into Installed System Memory.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810203023.0A CN108647368B (en) | 2018-03-13 | 2018-03-13 | Dynamic partial reconstruction system and method based on FPGA |
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| CN111314227A (en) * | 2020-03-16 | 2020-06-19 | 优刻得科技股份有限公司 | Programmable method and system architecture for service path |
| CN111813370A (en) * | 2020-07-08 | 2020-10-23 | 上海雪湖科技有限公司 | Multi-path parallel merging and sorting system based on FPGA |
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| CN112433982A (en) * | 2020-11-27 | 2021-03-02 | 天津七所精密机电技术有限公司 | FPGA dynamic reconstruction method for ship public computing service terminal |
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| CN112631968A (en) * | 2020-12-22 | 2021-04-09 | 无锡江南计算技术研究所 | Dynamic evolvable intelligent processing chip structure |
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