CN112631968A - Dynamic evolvable intelligent processing chip structure - Google Patents
Dynamic evolvable intelligent processing chip structure Download PDFInfo
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- CN112631968A CN112631968A CN202011524240.3A CN202011524240A CN112631968A CN 112631968 A CN112631968 A CN 112631968A CN 202011524240 A CN202011524240 A CN 202011524240A CN 112631968 A CN112631968 A CN 112631968A
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- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
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Abstract
The invention discloses a dynamic evolvable intelligent processing chip structure, which comprises: general purpose processor, intelligent processing unit, memory controller and memory interface, programmable logic area, programmable logic controller, programmable logic area further includes: the system comprises a dynamic system bus, a dynamic IO controller and a dynamic intelligent computing unit; dynamic system bus: the topological structure, the number and the specification of interfaces, an arbitration mechanism and the like can be reconstructed according to requirements, and the dynamic IO controller comprises: the dynamic intelligent computing unit is used for reconstructing the system into one or more IO controllers of different types according to different IO requirements of the system: the method is used for reconstructing a specific hardware structure according to the requirement and realizing the customization acceleration of calculation, memory access and IO. The invention can optimize the performance and efficiency of the whole system in the aspects of calculation, access, IO and the like, improve the calculation efficiency of intelligent application and realize the full-stack customization acceleration of the intelligent application.
Description
Technical Field
The invention relates to a dynamic evolvable intelligent processing chip structure, and belongs to the technical field of deep learning.
Background
At present, mainstream artificial intelligence application is mainly realized based on a deep neural network, the calculated amount of a network model in the application is very huge, great requirements are provided for the calculation capacity, the traditional general processor cannot meet the calculation capacity requirements, the intelligent processing acceleration is generally realized through a special acceleration component or chip, at present, the most mainstream artificial intelligence processing chip mainly comprises an Kviada GPU and an inference acceleration card, and manufacturers of Huantian, Baidu, Hanjiu and the like also have special artificial intelligence chips, so that the strong calculation capacity is provided for the intelligent processing in the deep learning.
The existing artificial intelligence processing chip is based on a fixed ASIC structure, the adaptability of the hardware structure can only meet the requirements of a part of specific types of applications, and the efficiency is very low for the applications with poor structural adaptability, so that the computing performance of the chip can not be fully exerted. Taking the GPU as an example, the form of the GPU is generally a PCIe card, and data communication between the GPU and the processor can only be realized through a PCIe interface, so all operation data and calculation results in the intelligent application can only be realized through the PCIe interface, and a PCIe interface protocol and a communication bandwidth may become bottlenecks, and the computational capability of calculating the GPU cannot be fully exerted. In addition, because the hardware structures of the chips such as the GPU are fixed, for some processing tasks with poor structural adaptability, processing can be performed only on the CPU or other acceleration components, and it is difficult to match the processing capability of the artificial intelligent chips such as the GPU.
Disclosure of Invention
The invention aims to provide a dynamic evolvable intelligent processing chip structure which can realize the performance and efficiency optimization of the aspects of calculation, access, IO and the like in the whole system, improve the calculation efficiency of intelligent application and realize the full-stack customization acceleration of the intelligent application.
In order to achieve the purpose, the invention adopts the technical scheme that: there is provided a dynamically evolvable intelligent processing chip architecture, comprising:
a general-purpose processor: the system is used for providing general computing resources and software running environment, supporting the running of basic system software such as an operating system and application programs, and managing and controlling the normal running of each functional module in the chip;
the intelligent processing unit: the method is applied to mainstream artificial intelligence, and provides main calculation force support for a typical artificial intelligence calculation model and an operator through a calculation component;
memory controller and memory interface: the memory controller is externally connected with an external memory chip through a memory interface, internally provides a system bus interface, and provides memory resources for each functional module in the chip through connection with the system bus;
it is characterized by also comprising:
programmable logic area: the method is realized by adopting programmable hardware logic resources, is used for reconstructing and configuring a hardware structure in the area according to requirements, and further comprises the following steps: the system comprises a dynamic system bus, a dynamic IO controller and a dynamic intelligent computing unit;
dynamic system bus: the bus interface is used for connecting each functional module, reconstructing the topological structure, the interface number and specification and the arbitration mechanism of each functional module according to the requirements of each functional module, providing one or more bus interfaces, and reconstructing the data bit width, the interface frequency and the arbitration level of each bus interface according to the hardware interface;
dynamic IO controller: the system is used for reconstructing one or more IO controllers of different types according to different IO requirements of the system, providing various types of required external IO interfaces for the general processor through a dynamic system bus, customizing and optimizing the IO controllers according to actual requirements, or providing a directly connected data interface for the dynamic intelligent computing unit to reduce the occupation of bus resources;
dynamic intelligent computing unit: the system is used for reconstructing a specific hardware structure as required, realizing customization acceleration of calculation, memory access and IO under the control of a general processor, directly accessing data in a memory through a dynamic system bus, and receiving data from a dynamic IO controller through a direct interface for processing;
the programmable logic controller: the method is used for realizing the configuration and control of the programmable logic in the programmable logic area in the chip: when the chip is powered on, loading basic programmable logic configuration from an external memory, and after the chip is started, reconstructing a programmable logic area into a specific customized hardware structure under the control of a general processor; the programmable logic configuration comprises the basic bus and the IO interface which are necessary for supporting the startup and the operation of a general processor, a memory controller and an intelligent processing unit in the static logic of the chip, and the programmable logic configuration of a dynamic intelligent computing unit, a dynamic system bus and a dynamic IO controller.
The further improved scheme in the technical scheme is as follows:
1. in the above scheme, the external IO interface includes a network interface, a storage interface, a USB interface, a serial port, and a PCIe interface.
2. In the above scheme, the dynamic intelligent computing unit may be reconfigured to be a dedicated hardware structure in terms of computing.
3. In the above scheme, in the aspect of access and storage, the dynamic intelligent computing unit can be used for sorting the data read from the memory, and converting the data format into the format most suitable for the intelligent processing unit.
4. In the above scheme, in the aspect of IO, the dynamic intelligent computing unit may directly receive IO data from the IO controller, and perform protocol processing and data filtering operations on the IO data.
Due to the application of the technical scheme, compared with the prior art, the invention has the following advantages:
the invention discloses a dynamically evolvable intelligent processing chip structure, which integrates an intelligent processing unit and a programmable hardware logic in the same chip in a tight coupling mode, wherein the programmable hardware logic can dynamically reconstruct the hardware logic structure according to the requirements of specific intelligent processing application, and dynamically configures the hardware logic of a programmable logic area by tightly coupling with the intelligent processing unit in the aspects of calculation, access, IO and the like, so that the performance and efficiency optimization in the aspects of calculation, access, IO and the like in the whole system is realized, the calculation efficiency of intelligent application is improved, and the full-stack customization acceleration of the intelligent application is realized.
Drawings
FIG. 1 is a schematic diagram of a dynamically evolvable intelligent processing chip structure according to the present invention.
Detailed Description
Example (b): the invention provides a dynamic evolvable intelligent processing chip structure, which changes the static structure of the existing intelligent processing chip, realizes a system bus and an IO controller in a programmable logic region, can dynamically update and customize the hardware structure and function of the intelligent processing chip, improves the structural adaptability of the intelligent processing chip, simultaneously benefits from the introduction of the programmable logic region, can flexibly realize a customized dynamic intelligent computing unit, not only can be used as an independent special accelerating component, but also can be reconstructed into an accelerating component with access and IO processing, assists the intelligent processing unit in the static region to realize higher computing efficiency, and improves the performance and the adaptability of the whole application;
the method specifically comprises the following steps:
a general-purpose processor: the system is used for providing general computing resources and software running environment, supporting the running of basic system software such as an operating system and application programs, and managing and controlling the normal running of each functional module in the chip;
the intelligent processing unit: the method is applied to mainstream artificial intelligence, and provides main calculation force support for a typical artificial intelligence calculation model and an operator through a calculation component;
memory controller and memory interface: the memory controller is externally connected with an external memory chip through a memory interface, internally provides a system bus interface, and provides memory resources for each functional module in the chip through connection with the system bus;
it is characterized by also comprising:
programmable logic area: the method is realized by adopting programmable hardware logic resources, is used for reconstructing and configuring a hardware structure in the area according to requirements, and further comprises the following steps: the system comprises a dynamic system bus, a dynamic IO controller and a dynamic intelligent computing unit;
dynamic system bus: the system is used for connecting each function module, reconstructing the topological structure, the interface quantity and specification and the arbitration mechanism of each function module according to the requirement of each function module, providing one or more bus interfaces, reconstructing the data bit width, the interface frequency and the arbitration level of each bus interface according to the hardware interface of each bus interface, namely selecting the interface bit width and the frequency suitable for the data transmission requirement of each function module through the connection of a dynamic system bus, and realizing the corresponding connection topology, cache and arbitration mechanism according to the characteristic of a data transmission mode;
dynamic IO controller: the system is used for reconstructing one or more IO controllers of different types according to different IO requirements of the system, providing various types of required external IO interfaces such as network, storage and peripheral interfaces for the general processor through a dynamic system bus, and also performing customized optimization on the IO controllers according to actual requirements, for example, received IO data can be preprocessed in the dynamic IO controllers, or a directly connected data interface can be provided for the dynamic intelligent computing unit to reduce the occupation of bus resources;
dynamic intelligent computing unit: the system is used for reconstructing a specific hardware structure as required, realizing customization acceleration of calculation, memory access and IO under the control of a general processor, directly accessing data in a memory through a dynamic system bus, and receiving data from a dynamic IO controller through a direct interface for processing;
the programmable logic controller: the method is used for realizing the configuration and control of the programmable logic in the programmable logic area in the chip: when the chip is powered on, loading basic programmable logic configuration from an external memory, and after the chip is started, reconstructing a programmable logic area into a specific customized hardware structure under the control of a general processor; the programmable logic configuration comprises the basic bus and the IO interface which are necessary for supporting the startup and the operation of a general processor, a memory controller and an intelligent processing unit in the static logic of the chip, and the programmable logic configuration of a dynamic intelligent computing unit, a dynamic system bus and a dynamic IO controller.
The above embodiments are further explained as follows:
the structure of the intelligent processing chip provided by the invention is shown in the following figure, besides static logics such as a general processor, an intelligent processing unit, a memory controller, a system bus and the like, a programmable logic area is integrated, the programmable logic area is directly connected with the system bus in the chip, the hardware structure of the intelligent processing chip supports dynamic reconstruction, can be reconstructed into a special dynamic intelligent computing unit, a dynamic data processing unit and a dynamic IO controller according to the requirements of practical application, realizes customization acceleration on the aspects of computation, memory access, IO and the like, and improves the whole application efficiency of the chip.
The functions of the components within the chip are as follows:
a general-purpose processor: providing general computing resources and software running environment, supporting the running of basic system software such as an operating system and application programs, and managing and controlling the normal running of each functional module in the chip;
the intelligent processing unit: the intelligent processing unit is applied to mainstream artificial intelligence, and provides main computational force support for a typical artificial intelligence computation model and an operator through a high-performance computation component;
memory controller and memory interface: the memory controller is externally connected with an external memory chip through a memory interface of the chip, internally provides a system bus interface, and provides memory resources for each part in the chip through connection with the system bus;
programmable logic area: the programmable logic area is realized by adopting programmable hardware logic resources, the hardware structure in the area can be reconstructed and configured according to requirements, and the logic function of the programmable logic area mainly comprises three parts:
(1) dynamic system bus
Different from the traditional fixed structure bus, because the system bus is realized by using programmable logic resources and has the capability of hardware programming, the functions of the bus, such as the topological structure, the interface quantity and specification, the arbitration mechanism and the like, can be reconstructed according to the requirements, for example, for a dynamic intelligent computing unit, one or more bus interfaces can be provided according to the specific requirements, and the data bit width, the interface frequency and the arbitration level of each bus interface can be reconstructed according to the hardware interface.
(2) Dynamic IO controller
The dynamic IO controller can be reconstructed into one or more IO controllers of different types according to different IO requirements of the system, various types of required external IO interfaces such as a network interface, a storage interface, a USB interface, a serial port, PCIe and the like are provided for the system, due to the fact that the dynamic IO controller is realized in a reconfigurable area, customization and optimization can be carried out on the IO controller according to actual requirements, a directly connected data interface can be provided for the dynamic intelligent computing unit, and the overall application efficiency is improved.
(3) Dynamic intelligent computing unit
The dynamic intelligent computing unit can be reconstructed into a specific hardware structure according to the needs, so that customization acceleration on the aspects of computing, memory access, IO and the like is realized, for example, in the aspect of computing, aiming at a model or algorithm with lower processing efficiency in the intelligent processing unit, the dynamic intelligent computing unit can be reconstructed into a special hardware structure, and the processing performance of the model or algorithm is improved; in the aspect of access and storage, the data read from the memory can be firstly sorted by using the dynamic intelligent computing unit, the data format is converted into the format most suitable for the intelligent processing unit, and the data processing overhead in the whole operation process is reduced; in the aspect of IO, the dynamic intelligent computing unit can directly receive IO data from the IO controller, and performs operations such as protocol processing and data filtering on the IO data, so that the load of other components such as a general processor is reduced, the processing delay is reduced, and the overall computing efficiency is improved.
The programmable logic controller: the programmable logic controller realizes the configuration and control of the programmable logic in the programmable logic area of the chip, and the main functions of the programmable logic controller comprise two aspects, namely, when the chip is powered on, basic programmable logic configuration is loaded from an external storage, wherein the basic programmable logic configuration comprises hardware modules such as a basic bus and an IO interface which are necessary for supporting the starting and the operation of a general processor, a memory controller and an intelligent processing unit in the static logic of the chip, and the normal power-on boot starting of the chip is supported; secondly, after the chip is started, the programmable logic area is reconstructed into a specific customized hardware structure under the control of the general processor, and the dynamic evolution of the chip functional structure is realized.
When the structure of the dynamically evolvable intelligent processing chip is adopted, the intelligent processing unit and the programmable hardware logic are integrated in the same chip in a tight coupling mode, the programmable hardware logic can dynamically reconstruct the hardware logic structure according to the requirements of specific intelligent processing application, and the hardware logic of the programmable logic area is dynamically configured by being tightly coupled with the intelligent processing unit in the aspects of calculation, access, IO and the like, so that the performance and efficiency optimization in the aspects of calculation, access, IO and the like in the whole system is realized, the calculation efficiency of intelligent application is improved, and the full-stack customization acceleration of the intelligent application is realized.
The above embodiments are merely illustrative of the technical ideas and features of the present invention, and the purpose thereof is to enable those skilled in the art to understand the contents of the present invention and implement the present invention, and not to limit the protection scope of the present invention. All equivalent changes and modifications made according to the spirit of the present invention should be covered within the protection scope of the present invention.
Claims (5)
1. A dynamically evolvable intelligent processing chip architecture, comprising:
a general-purpose processor: the system is used for providing general computing resources and software running environment, supporting the running of basic system software such as an operating system and application programs, and managing and controlling the normal running of each functional module in the chip;
the intelligent processing unit: the method is applied to mainstream artificial intelligence, and provides main calculation force support for a typical artificial intelligence calculation model and an operator through a calculation component;
memory controller and memory interface: the memory controller is externally connected with an external memory chip through a memory interface, internally provides a system bus interface, and provides memory resources for each functional module in the chip through connection with the system bus;
it is characterized by also comprising:
programmable logic area: the method is realized by adopting programmable hardware logic resources, is used for reconstructing and configuring a hardware structure in the area according to requirements, and further comprises the following steps: the system comprises a dynamic system bus, a dynamic IO controller and a dynamic intelligent computing unit;
dynamic system bus: the bus interface is used for connecting each functional module, reconstructing the topological structure, the interface number and specification and the arbitration mechanism of each functional module according to the requirements of each functional module, providing one or more bus interfaces, and reconstructing the data bit width, the interface frequency and the arbitration level of each bus interface according to the hardware interface;
dynamic IO controller: the system is used for reconstructing one or more IO controllers of different types according to different IO requirements of the system, providing various types of required external IO interfaces for the general processor through a dynamic system bus, customizing and optimizing the IO controllers according to actual requirements, or providing a directly connected data interface for the dynamic intelligent computing unit to reduce the occupation of bus resources;
dynamic intelligent computing unit: the system is used for reconstructing a specific hardware structure as required, realizing customization acceleration of calculation, memory access and IO under the control of a general processor, directly accessing data in a memory through a dynamic system bus, and receiving data from a dynamic IO controller through a direct interface for processing;
the programmable logic controller: the method is used for realizing the configuration and control of the programmable logic in the programmable logic area in the chip: when the chip is powered on, loading basic programmable logic configuration from an external memory, and after the chip is started, reconstructing a programmable logic area into a specific customized hardware structure under the control of a general processor; the programmable logic configuration comprises the basic bus and the IO interface which are necessary for supporting the startup and the operation of a general processor, a memory controller and an intelligent processing unit in the static logic of the chip, and the programmable logic configuration of a dynamic intelligent computing unit, a dynamic system bus and a dynamic IO controller.
2. The dynamically evolvable intelligent processing chip architecture as claimed in claim 1, wherein: the external IO interface comprises a network interface, a storage interface, a USB interface, a serial port and a PCIe interface.
3. The dynamically evolvable intelligent processing chip architecture as claimed in claim 1, wherein: in terms of computation, the dynamic intelligent computing unit can be reconstructed into a special hardware structure.
4. The dynamically evolvable intelligent processing chip architecture as claimed in claim 1, wherein: in the aspect of access and storage, the dynamic intelligent computing unit can be used for sorting the data read from the memory and converting the data format into the format most suitable for the intelligent processing unit.
5. The dynamically evolvable intelligent processing chip architecture as claimed in claim 1, wherein: in the aspect of IO, the dynamic intelligent computing unit may directly receive IO data from the IO controller, and perform protocol processing and data filtering operations on the IO data.
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