CN108630538A - A kind of semiconductor devices and its manufacturing method and electronic device - Google Patents
A kind of semiconductor devices and its manufacturing method and electronic device Download PDFInfo
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- CN108630538A CN108630538A CN201710161177.3A CN201710161177A CN108630538A CN 108630538 A CN108630538 A CN 108630538A CN 201710161177 A CN201710161177 A CN 201710161177A CN 108630538 A CN108630538 A CN 108630538A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 88
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 29
- 229910052723 transition metal Inorganic materials 0.000 claims abstract description 89
- 238000000034 method Methods 0.000 claims abstract description 63
- 239000000758 substrate Substances 0.000 claims abstract description 56
- 238000000137 annealing Methods 0.000 claims abstract description 55
- 239000010410 layer Substances 0.000 claims description 322
- 150000003624 transition metals Chemical class 0.000 claims description 36
- 239000011241 protective layer Substances 0.000 claims description 15
- 239000002344 surface layer Substances 0.000 claims description 15
- 238000000576 coating method Methods 0.000 claims description 9
- 239000011247 coating layer Substances 0.000 claims description 3
- 230000007704 transition Effects 0.000 claims description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 2
- 229910052737 gold Inorganic materials 0.000 claims description 2
- 239000010931 gold Substances 0.000 claims description 2
- 238000002425 crystallisation Methods 0.000 abstract description 11
- 230000008025 crystallization Effects 0.000 abstract description 11
- 239000000463 material Substances 0.000 description 42
- 238000009792 diffusion process Methods 0.000 description 23
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 21
- 238000005229 chemical vapour deposition Methods 0.000 description 21
- 230000008569 process Effects 0.000 description 20
- 229910052751 metal Inorganic materials 0.000 description 16
- 238000000231 atomic layer deposition Methods 0.000 description 15
- 239000002184 metal Substances 0.000 description 15
- 238000000151 deposition Methods 0.000 description 13
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 12
- 239000011229 interlayer Substances 0.000 description 11
- 229910052581 Si3N4 Inorganic materials 0.000 description 9
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 8
- 239000012212 insulator Substances 0.000 description 8
- 229910052710 silicon Inorganic materials 0.000 description 8
- 239000010703 silicon Substances 0.000 description 8
- 239000000377 silicon dioxide Substances 0.000 description 8
- 239000013078 crystal Substances 0.000 description 7
- 230000008021 deposition Effects 0.000 description 7
- MWUXSHHQAYIFBG-UHFFFAOYSA-N Nitric oxide Chemical compound O=[N] MWUXSHHQAYIFBG-UHFFFAOYSA-N 0.000 description 6
- 239000011248 coating agent Substances 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 6
- 238000002347 injection Methods 0.000 description 6
- 239000007924 injection Substances 0.000 description 6
- 125000006850 spacer group Chemical group 0.000 description 6
- 239000000126 substance Substances 0.000 description 6
- 238000002955 isolation Methods 0.000 description 5
- MRELNEQAGSRDBK-UHFFFAOYSA-N lanthanum(3+);oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[La+3].[La+3] MRELNEQAGSRDBK-UHFFFAOYSA-N 0.000 description 5
- 230000003647 oxidation Effects 0.000 description 5
- 238000007254 oxidation reaction Methods 0.000 description 5
- 229910052814 silicon oxide Inorganic materials 0.000 description 5
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 4
- 229910004490 TaAl Inorganic materials 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 4
- 229910021417 amorphous silicon Inorganic materials 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 229910000449 hafnium oxide Inorganic materials 0.000 description 4
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 4
- 238000009413 insulation Methods 0.000 description 4
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 4
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 description 4
- 238000005240 physical vapour deposition Methods 0.000 description 4
- 238000001020 plasma etching Methods 0.000 description 4
- IATRAKWUXMZMIY-UHFFFAOYSA-N strontium oxide Chemical compound [O-2].[Sr+2] IATRAKWUXMZMIY-UHFFFAOYSA-N 0.000 description 4
- 229910052719 titanium Inorganic materials 0.000 description 4
- 239000010936 titanium Substances 0.000 description 4
- 229910001928 zirconium oxide Inorganic materials 0.000 description 4
- 230000009471 action Effects 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 230000006835 compression Effects 0.000 description 3
- 238000007906 compression Methods 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 3
- 238000011049 filling Methods 0.000 description 3
- 229910052732 germanium Inorganic materials 0.000 description 3
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 239000000047 product Substances 0.000 description 3
- 239000000243 solution Substances 0.000 description 3
- 238000001039 wet etching Methods 0.000 description 3
- -1 LDD ion Chemical class 0.000 description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- WUNIMIODOAGQAW-UHFFFAOYSA-N [O-2].[Ba+2].[Ti+4] Chemical compound [O-2].[Ba+2].[Ti+4] WUNIMIODOAGQAW-UHFFFAOYSA-N 0.000 description 2
- CEPICIBPGDWCRU-UHFFFAOYSA-N [Si].[Hf] Chemical compound [Si].[Hf] CEPICIBPGDWCRU-UHFFFAOYSA-N 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 2
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- 230000000694 effects Effects 0.000 description 2
- 238000000227 grinding Methods 0.000 description 2
- PDKGWPFVRLGFBG-UHFFFAOYSA-N hafnium(4+) oxygen(2-) silicon(4+) Chemical compound [O-2].[Hf+4].[Si+4].[O-2].[O-2].[O-2] PDKGWPFVRLGFBG-UHFFFAOYSA-N 0.000 description 2
- 238000010884 ion-beam technique Methods 0.000 description 2
- 238000005224 laser annealing Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910052750 molybdenum Inorganic materials 0.000 description 2
- 239000011733 molybdenum Substances 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- CZXRMHUWVGPWRM-UHFFFAOYSA-N strontium;barium(2+);oxygen(2-);titanium(4+) Chemical compound [O-2].[O-2].[O-2].[O-2].[Ti+4].[Sr+2].[Ba+2] CZXRMHUWVGPWRM-UHFFFAOYSA-N 0.000 description 2
- 229910003468 tantalcarbide Inorganic materials 0.000 description 2
- 229910052715 tantalum Inorganic materials 0.000 description 2
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 2
- 229910001936 tantalum oxide Inorganic materials 0.000 description 2
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- GFQYVLUOOAAOGM-UHFFFAOYSA-N zirconium(iv) silicate Chemical compound [Zr+4].[O-][Si]([O-])([O-])[O-] GFQYVLUOOAAOGM-UHFFFAOYSA-N 0.000 description 2
- QGZKDVFQNNGYKY-UHFFFAOYSA-O Ammonium Chemical compound [NH4+] QGZKDVFQNNGYKY-UHFFFAOYSA-O 0.000 description 1
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 description 1
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 229910010038 TiAl Inorganic materials 0.000 description 1
- 229910017817 a-Ge Inorganic materials 0.000 description 1
- 239000000908 ammonium hydroxide Substances 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 230000001427 coherent effect Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- QZQVBEXLDFYHSR-UHFFFAOYSA-N gallium(III) oxide Inorganic materials O=[Ga]O[Ga]=O QZQVBEXLDFYHSR-UHFFFAOYSA-N 0.000 description 1
- 229910002804 graphite Inorganic materials 0.000 description 1
- 239000010439 graphite Substances 0.000 description 1
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 1
- 229910052736 halogen Inorganic materials 0.000 description 1
- 150000002367 halogens Chemical class 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000003384 imaging method Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(III) oxide Inorganic materials [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 description 1
- 239000013067 intermediate product Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- KTUFCUMIWABKDW-UHFFFAOYSA-N oxo(oxolanthaniooxy)lanthanum Chemical compound O=[La]O[La]=O KTUFCUMIWABKDW-UHFFFAOYSA-N 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 229910052707 ruthenium Inorganic materials 0.000 description 1
- 238000004062 sedimentation Methods 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 238000002230 thermal chemical vapour deposition Methods 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
A kind of semiconductor devices of present invention offer and its manufacturing method and electronic device, the method includes：Semiconductor substrate is provided, forms high k dielectric layer on the semiconductor substrate；The containing transition metal element in the high k dielectric layer；Carry out the first annealing.Manufacturing method according to the invention, the containing transition metal element in the high k dielectric layer, the transition metal element inhibits the crystallization of high k dielectric layer during first anneals, cubic phase and smaller crystallite dimension are formed in high k dielectric layer, therefore, the method of the present invention can reduce electric leakage of the grid, improve the performance and yield of device.
Description
Technical field
The present invention relates to technical field of semiconductors, in particular to a kind of semiconductor devices and its manufacturing method and electronics
Device.
Background technology
With the continuous development of semiconductor technology, the raising of performance of integrated circuits is mainly by constantly reducing integrated circuit
The size of device is realized with improving its speed.Currently, due in pursuing high device density, high-performance and low cost half
Conductor industry has advanced to that nanotechnology process node, the preparation of semiconductor devices are limited by various physics limits.
Due to the continuous diminution of technology node, can increase in the case where keeping gate capacitance constant using high k dielectric layer
The physical thickness of gate dielectric layer film, to achieve the purpose that reduce gate dielectric leakage, improve device reliability.It is right
In FinFET, deposition anneal (PDA) is carried with improving the quality of high k dielectric layer after usually being executed after high k dielectric layer deposition
Positive bias temperature instability (Positive Bias Temperature Instability, the abbreviation of high NMOS device
PBTI), since oxygen vacancies can be reduced in annealing process.But in annealing process, high k dielectric layer is (for example, HfO2) can be from
Top surface is gradually crystallized to bottom, if grain size (crystal size) is too big, it will there is the leakage path along crystal boundary
(leakage path), for example, when crystallite dimension increases to more than 5nm, electric leakage of the grid significantly increases.Therefore, how to move back
It is one of the problem faced at present to control the crystallization of high k dielectric layer during fire.
Therefore, it is necessary to propose a kind of manufacturing method of new semiconductor devices, to solve the above technical problems.
Invention content
A series of concept of reduced forms is introduced in Summary, this will in the detailed description section into
One step is described in detail.The Summary of the present invention is not meant to attempt to limit technical solution claimed
Key feature and essential features do not mean that the protection domain for attempting to determine technical solution claimed more.
In view of the deficiencies of the prior art, the present invention provides a kind of on the one hand manufacturing method of semiconductor devices, the method
Including：
Semiconductor substrate is provided, forms high k dielectric layer on the semiconductor substrate；
The containing transition metal element in the high k dielectric layer；
Carry out the first annealing.
Further, it is formed with gate trench on the semiconductor substrate, the high k dielectric layer is formed in the grid ditch
In the bottom and side wall of slot.
Further, the method that the transition metal element is adulterated in the high k dielectric layer includes the following steps：
Transition metal layer is formed on the surface of the high k dielectric layer, the transition metal layer includes the transition metal member
Element；
Carry out the second annealing, wherein second annealing makes the gold of the transition in the transition metal layer
Belong to elements diffusion to enter in the high k dielectric layer；
Remove the transition metal layer.
Further, further include forming insulating layer on the surface of the high k dielectric layer before forming the transition metal layer
The step of, it is removed after the removal transition metal layer and before first annealing by the insulating layer.
Further, described transition metal element doped in the surface layer of the high k dielectric layer.
Further, the transition metal element includes Mo and/or Ta.
Further, the thickness range of the transition metal layer is 20 angstroms~80 angstroms, and/or, the thickness model of the insulating layer
Enclose is 5 angstroms~20 angstroms.
Further, the temperature range of first annealing is 700 DEG C~900 DEG C, and/or, second annealing
Temperature range is 60 DEG C~150 DEG C.
Further, further comprising the steps of after first annealing：
Coating and protective layer are formed on the surface of the high k dielectric layer successively conformal deposited；
Carry out third annealing；
Remove the protective layer.
Another aspect of the present invention provides a kind of semiconductor devices, including：
Semiconductor substrate is formed with high k dielectric layer on the semiconductor substrate；
Doped with transition metal element in the high k dielectric layer.
Further, it is formed with gate trench on the semiconductor substrate, the high k dielectric layer is formed in the grid ditch
In the bottom and side wall of slot.
Further, described transition metal element doped in the surface layer of the high k dielectric layer.
Further, the transition metal element includes Mo and/or Ta.
Further aspect of the present invention provides a kind of electronic device, and the electronic device includes semiconductor devices above-mentioned.
Manufacturing method according to the invention, in the high k dielectric layer containing transition metal element (such as Mo and/or
Ta), the transition metal element inhibits the crystallization of high k dielectric layer during first anneals, and is formed in high k dielectric layer vertical
Square phase (cubic phase) and smaller crystallite dimension, therefore, method of the invention can reduce electric leakage of the grid, improve device
Performance and yield.
Description of the drawings
The following drawings of the present invention is used to understand the present invention in this as the part of the present invention.Shown in the drawings of this hair
Bright embodiment and its description, principle used to explain the present invention.
In attached drawing：
Figure 1A to Fig. 1 D shows the correlation step institute of the manufacturing method of the semiconductor devices of one embodiment of the present invention
The structural schematic diagram of the device of acquisition；
Fig. 2 shows the process flow charts of the manufacturing method of the semiconductor devices of one embodiment of the present invention；
Fig. 3 shows the schematic diagram of the electronic device in one embodiment of the invention.
Specific implementation mode
In the following description, a large amount of concrete details are given in order to provide more thorough understanding of the invention.So
And it is obvious to the skilled person that the present invention may not need one or more of these details and be able to
Implement.In other examples, in order to avoid with the present invention obscure, for some technical characteristics well known in the art not into
Row description.
It should be understood that the present invention can be implemented in different forms, and should not be construed as being limited to propose here
Embodiment.Disclosure will be made thoroughly and complete on the contrary, providing these embodiments, and will fully convey the scope of the invention to
Those skilled in the art.In the accompanying drawings, for clarity, the size and relative size in the areas Ceng He may be exaggerated.From beginning to end
Same reference numerals indicate identical element.
It should be understood that when element or layer be referred to as " ... on ", " with ... it is adjacent ", " being connected to " or " being coupled to " it is other
When element or layer, can directly on other elements or layer, it is adjacent thereto, be connected or coupled to other elements or layer, or
There may be elements or layer between two parties by person.On the contrary, when element is referred to as " on directly existing ... ", " with ... direct neighbor ", " directly
It is connected to " or " being directly coupled to " other elements or when layer, then element or layer between two parties is not present.It should be understood that although can make
Various component, assembly units, area, floor and/or part are described with term first, second, third, etc., these component, assembly units, area, floor and/
Or part should not be limited by these terms.These terms be used merely to distinguish a component, assembly unit, area, floor or part with it is another
One component, assembly unit, area, floor or part.Therefore, do not depart from present invention teach that under, first element discussed below, portion
Part, area, floor or part are represented by second element, component, area, floor or part.
Spatial relationship term for example " ... under ", " ... below ", " below ", " ... under ", " ... it
On ", " above " etc., herein can for convenience description and being used describe an elements or features shown in figure with
The relationship of other elements or features.It should be understood that other than orientation shown in figure, spatial relationship term intention further includes making
With the different orientation with the device in operation.For example, if the device in attached drawing is overturn, then, it is described as " under other elements
Face " or " under it " or " under it " elements or features will be oriented in other elements or features "upper".Therefore, exemplary art
Language " ... below " and " ... under " it may include upper and lower two orientations.Device can additionally be orientated (be rotated by 90 ° or its
It is orientated) and spatial description language as used herein correspondingly explained.
The purpose of term as used herein is only that description specific embodiment and not as the limitation of the present invention.Make herein
Used time, " one " of singulative, "one" and " described/should " be also intended to include plural form, unless context is expressly noted that separately
Outer mode.It is also to be understood that term " composition " and/or " comprising ", when being used in this specification, determines the feature, whole
The presence of number, step, operations, elements, and/or components, but be not excluded for one or more other features, integer, step, operation,
The presence or addition of component, assembly unit and/or group.Herein in use, term "and/or" includes any of related Listed Items and institute
There is combination.
It describes to send out herein with reference to the cross-sectional view of the schematic diagram of the desirable embodiment (and intermediate structure) as the present invention
Bright embodiment.As a result, it is contemplated that due to caused by such as manufacturing technology and/or tolerance from the variation of shown shape.Therefore,
The embodiment of the present invention should not necessarily be limited to the specific shape in area shown here, but include due to for example manufacturing caused shape
Shape deviation.For example, be shown as the injection region of rectangle its edge usually there is circle or bending features and/or implantation concentration ladder
Degree, rather than the binary from injection region to non-injection regions changes.Equally, the disposal area can be led to by injecting the disposal area formed
Some injections in area between the surface passed through when injection progress.Therefore, the area shown in figure is substantially schematic
, their shape is not intended the true form in the area of display device and is not intended to limit the scope of the present invention.
In order to thoroughly understand the present invention, detailed step and structure will be proposed in following description, to illustrate this
Invent the technical solution proposed.Presently preferred embodiments of the present invention is described in detail as follows, however other than these detailed descriptions, this hair
It is bright to have other embodiment.
Embodiment one
In order to solve aforementioned technical problem, the performance of device is improved, a kind of semiconductor device is provided in the embodiment of the present invention
The manufacturing method of part, as described in Figure 2, the method includes mainly：
Step S1, provides semiconductor substrate, forms high k dielectric layer on the semiconductor substrate；
Step S2, the containing transition metal element in the high k dielectric layer；
Step S3 carries out the first annealing.
Manufacturing method according to the invention, in the high k dielectric layer containing transition metal element (such as Mo and/or
Ta), the transition metal element inhibits the crystallization of high k dielectric layer during first anneals, and is formed in high k dielectric layer vertical
Square phase (cubic phase) and smaller crystallite dimension, therefore, method of the invention can reduce electric leakage of the grid, improve device
Performance and yield.
Specifically, the manufacturing method of the semiconductor devices of the present invention is described in detail below with reference to Figure 1A-Fig. 1 D,
In, Figure 1A to Fig. 1 D shows what the correlation step of the manufacturing method of the semiconductor devices of one embodiment of the present invention was obtained
The structural schematic diagram of device.
First, step 1 is executed, semiconductor substrate is provided, forms gate trench on the semiconductor substrate.
Specifically, as shown in Figure 1A, the semiconductor substrate 100 can be at least one in the following material being previously mentioned
Kind：Silicon, silicon-on-insulator (SOI), stacking silicon (SSOI) on insulator, stacking SiGe (S-SiGeOI), insulation on insulator
SiGe (SiGeOI) and germanium on insulator (GeOI) etc. on body.
Illustratively, the semiconductor substrate includes at least one of NMOS device area and PMOS device area.
In one example, the semiconductor substrate includes NMOS device area and PMOS device area, wherein in the NMOS
It is formed with gate trench 1021 in device region, gate trench 1022 is formed in the PMOS device area.
Illustratively, semiconductor devices of the invention is FinFET, then the semiconductor in the NMOS device area
It is formed with the first fin structure on substrate, the second fin knot is formed in the semiconductor substrate in each PMOS device area
Structure, the surface of the first fin structure described in 1021 exposed portion of the gate trench, described in 1022 exposed portion of gate trench
The surface of two fin structures.
In one example, by taking FinFET as an example, in order to obtain structure as shown in Figure 1A, following step can be executed
Rapid A1 to A5：
First, step A1 is executed, multiple fin structures are formed on a semiconductor substrate, for example, in the semiconductor substrate
On the NMOS device area and the PMOS device area in be respectively formed with the first fin structure and the second fin structure, fin
The width of structure is all identical or fin is divided into multiple fin structure groups with different in width, the length of fin structure
It can differ.
Specifically, the forming method of the fin structure is not limited to a certain kind, and a kind of illustrative shape is given below
At method：Hard mask layer (not shown) is formed on a semiconductor substrate, forms the hard mask layer and this field may be used
The various suitable techniques that technical staff is familiar with, such as chemical vapor deposition method, the hard mask layer can be from lower and
The oxide skin(coating) and silicon nitride layer of upper stacking；The hard mask layer is patterned, is formed for etch semiconductor substrates on it
The multiple masks being isolated from each other for forming fin, in one embodiment, using self-aligned double patterning case (SADP) process implementing institute
State patterning process；Etch semiconductor substrates are to be formed on fin structure.
Then, step A2, depositing isolation material layer, to cover all fin structures above-mentioned be can also carry out.
Specifically, depositing isolation material layer, to be filled up completely the gap between fin structure.In one embodiment, it adopts
Implement the deposition with the chemical vapor deposition method with flowability.The material of spacer material layer can with selective oxidation object,
Such as high-aspect-ratio technique (HARP) oxide, it is specifically as follows silica.
Then it is etched back to the spacer material layer, until the object height of the fin structure, described to form isolation structure
The top surface of isolation structure is less than the top surface of the first fin structure and second fin structure.Specifically, it is etched back to the isolation
Material layer with fin structure described in exposed portion, and then forms the fin structure with certain height.
Then, step A3 is executed, is developed across the first dummy gate structure of first fin structure and across the second fin
Second dummy gate structure of chip architecture, wherein dummy gate structure include dummy grid dielectric layer and dummy grid material layer.
It should be pointed out that the term " across " used in the present invention, such as across fin structure (such as the first fin
Structure, second fin structure etc.) dummy gate structure, refer to being each formed with puppet in the upper surface of the part of fin structure and side
Gate structure, and the dummy gate structure is also formed on the part surface of semiconductor substrate.
In one example, it first can be sequentially depositing to form dummy grid dielectric layer and dummy grid material on a semiconductor substrate
Layer.
Wherein, the dummy grid dielectric layer can select common oxide, such as SiO2, the dummy grid material layer can
To select semi-conducting material commonly used in the art, such as polysilicon can be selected etc., it is not limited to it is a certain, it is not another herein
One enumerate,
The deposition method of the dummy grid material layer can select the methods of chemical vapor deposition or atomic layer deposition.
Then the dummy grid dielectric layer and dummy grid material layer are patterned, to form first dummy gate structure and
Two dummy gate structures.Specifically, photoresist layer is formed in the dummy grid material layer, then exposure imaging, to form opening,
Then using the photoresist layer as dummy grid material layer described in mask etching, photoresist layer is finally removed.
Later, also optionally, it is formed on the side wall of first dummy gate structure and the second dummy gate structure inclined
Move side wall (Spacer).
Specifically, the offset side wall can be a kind of in silica, silicon nitride, silicon oxynitride or they combine structure
At.As embodiment in the one of the present embodiment, the offset side wall is that silica, silicon nitride collectively constitute, and concrete technology is：
The first silicon oxide layer, the first silicon nitride layer and the second silicon oxide layer are formed on a semiconductor substrate, then use lithographic method
Form offset side wall.It can also be respectively formed on spacer material layer in the top surface of dummy gate structure and side wall, in the steps afterwards
By the method for planarization, such as chemical mechanical grinding, the spacer material layer on top surface is removed, formation is located only on side wall
Offset side wall.
Optionally, LDD ion implantings step and work are executed to the first dummy gate structure and the second dummy gate structure both sides
Change.
Optionally, clearance wall is formed on the offset side wall of the dummy gate structure.
Specifically, on being formed by offset side wall formed clearance wall (Spacer), the clearance wall can be silica,
A kind of or their combinations are constituted in silicon nitride, silicon oxynitride.As embodiment in the one of the present embodiment, the clearance wall is
Silica, silicon nitride collectively constitute, and concrete technology is：The first silicon oxide layer, the first silicon nitride layer are formed on a semiconductor substrate
And second silicon oxide layer, then lithographic method is used to form clearance wall.
Then, step A4 is executed, executes source and drain injection, and in the first fin of the both sides of the first dummy gate structure above-mentioned
The source/drain that NMOS device is formed in structure, forms PMOS devices in the second fin structure of the both sides of the second dummy gate structure
The source/drain of part.
In one example, further include step：In the first dummy gate structure and the second dummy gate structure both sides source/drain
Region growing stressor layers usually form the stressor layers with tensile stress, in PMOS on the nmos transistors in CMOS transistor
Form the stressor layers with compression on transistor, the performance of cmos device can by by the action of pulling stress in NMOS,
Action of compressive stress is improved in PMOS.Usually select SiC as tensile stress layer in NMOS transistor in the prior art, in PMOS
Usually select SiGe as compressive stress layer in transistor.
Preferably, when growing the SiC as tensile stress layer, can epitaxial growth over the substrate, in ion implanting
Lifting source and drain is formed afterwards and usually forms groove in the substrate when forming the SiGe layer, is then sunk in the groove
Product forms SiGe layer.It is further preferred that forming " ∑ " connected in star in the substrate.
Then, step A5 is executed, interlevel dielectric deposition 101 simultaneously planarizes, to fill between each dummy gate structure
Gap.
Specifically, it interlevel dielectric deposition 101 and planarizes, planarization is described to the pseudo- grid of interlayer dielectric layer 101 to the first
The top of pole structure and the second dummy gate structure.
Wherein, the interlayer dielectric layer 101 can select dielectric material commonly used in the art, such as various oxides
Deng interlayer dielectric layer can select SiO in this embodiment2, thickness is not limited to a certain numerical value.
The non-limiting examples of the planarization process include mechanical planarization method and chemically mechanical polishing planarization side
Method.
Later, the first dummy gate structure and the second dummy gate structure are removed, including removes dummy grid dielectric layer and puppet successively
Gate material layers, to form gate trench 1021 in the semiconductor substrate 100 in NMOS device area, in partly leading for PMOS device area
Gate trench 1022 is formed in body substrate 100, extension of the gate trench in the NMOS device area in first fin structure
First fin structure described in exposed portion on direction, the gate trench in PMOS device area is in the extension side of second fin structure
Second fin structure described in upward exposed portion.
Illustratively, gate trench 1021 and grid are formed in the interlayer dielectric layer 101 on 100 surface of semiconductor substrate
Groove 1022.
It completes above-mentioned steps and then obtains structure as shown in Figure 1A.
Then, step 2 is executed, forms high k dielectric layer in the bottom and side wall of the gate trench.
Specifically, as shown in Figure 1B, in the grid ditch of the gate trench 1021 in NMOS device area and the PMOS device area
The side wall of slot 1022 and bottom are respectively formed high k dielectric layer 104, further, the high k dielectric layer covering interlayer dielectric layer 101
Surface.
The k values (dielectric constant) of high k dielectric layer 104 are usually 3.9 or more, and constituent material includes hafnium oxide, hafnium oxide
Silicon, nitrogen oxidation hafnium silicon, lanthana, zirconium oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, strontium barium oxide titanium, barium monoxide titanium, strontium oxide strontia
Titanium, aluminium oxide etc., preferably hafnium oxide, zirconium oxide or aluminium oxide.Chemical vapour deposition technique (CVD), atomic layer may be used
The suitable technique such as sedimentation (ALD) or physical vaporous deposition (PVD) forms high k dielectric layer 104.
Optionally, the thickness range of high k dielectric layer 104 is 10 angstroms to 30 angstroms, or other suitable thickness, herein
It is not specifically limited.
In one example, before forming the high k dielectric layer 104, interface is formed in the bottom of the gate trench
Layer 103.Illustratively, in the gate trench 1022 in the PMOS device area and the gate trench in NMOS device area
1021 bottoms are respectively formed boundary layer 103, form boundary layer (IL)) 103 effect be improve high k dielectric layer and semiconductor substrate it
Between interfacial characteristics.
IL layers can be thermal oxide layer, nitrogen oxide layer, chemical oxide layer or other suitable film layers.It can be with
Using thermal oxide, chemical oxidation, chemical vapor deposition (CVD), atomic layer deposition (ALD) or physical vapour deposition (PVD) (PVD) etc.
Suitable technique forms boundary layer.
The thickness of boundary layer 103 can need to carry out reasonable set according to actual process, for example, the thickness model of boundary layer 103
Enclosing can be 5 angstroms to 10 angstroms.
Then, step 3 is executed, insulating layer is formed on the surface of the high k dielectric layer.
Illustratively, as shown in Figure 1 C, insulating layer 105 is formed in the surface conformal deposited of the high k dielectric layer 104.
The material of the insulating layer 105 can be any suitable material well known to those skilled in the art, and insulating layer can
Using such as inorganic insulation layer of silicon oxide layer, silicon nitride layer or silicon oxynitride layer, in the present embodiment, the insulating layer 105
Material is preferably comprised silica.
Chemical vapor deposition (CVD), atomic layer deposition (ALD) or physical vapour deposition (PVD) (PVD) etc. can be used
Suitable depositing operation forms the insulating layer.In the present embodiment, the insulation is deposited preferably with Atomic layer deposition method
Layer.
Wherein, the thickness of the insulating layer 105 can be any suitable thickness, such as the thickness of the insulating layer 105
Ranging from 5 angstroms~20 angstroms, for example, 5 angstroms, 10 angstroms, 15 angstroms, 20 angstroms etc..
Then, step 4 is executed, transition metal layer, the transition metal layer packet are formed on the surface of the high k dielectric layer
Include the transition metal element.
In one example, transition metal layer is formed on the surface of the high k dielectric layer, the transition metal layer includes institute
State transition metal element.
In another example, continue as shown in Figure 1 C, the conformal deposited formation transition on the surface of the insulating layer 105
Metal layer 106, wherein the transition metal layer includes transition metal element.
Optionally, the transition metal element can be any suitable transition metal member well known to those skilled in the art
Element, in the present embodiment, preferably, the transition metal element includes (molybdenum) Mo and/or tantalum (Ta).
Illustratively, the transition metal layer is Mo layers, alternatively, the transition metal layer is Ta layers.
Transition metal layer can pass through low-pressure chemical vapor deposition (LPCVD), plasma auxiliary chemical vapor deposition
(PECVD), metal organic chemical vapor deposition (MOCVD) and atomic layer deposition (ALD) or other advanced deposition techniques are formed.
Optionally, the thickness range of the transition metal layer 106 can be 20 angstroms~80 angstroms, for example, 20 angstroms, 30 angstroms, 40
Angstrom, 50 angstroms, 60 angstroms, 70 angstroms etc..
Then, step 5 is executed, is made annealing treatment, wherein the annealing makes the mistake in the transition metal layer
It crosses metallic element to diffuse into the high k dielectric layer, with the containing transition metal element in the high k dielectric layer.
Illustratively, the transition metal element in the transition metal layer is made to diffuse by the annealing of this step
In the high k dielectric layer, further, the transition metal element diffuses into downwards the surface layer of high k dielectric layer, makes the height
The surface layer containing transition metal element of k dielectric layer.
Wherein, insulating layer is set between the transition metal layer and the high k dielectric layer, the presence of the insulating layer can be with
Control transition metal element diffuses into the depth in high k dielectric layer, and high k Jie is diffused into control transition metal element
The surface layer of electric layer, and make process window bigger.
In one example, the annealing of this step is preferably process annealing processing, and annealing region can be with
It it is 60 DEG C~150 DEG C, for example, 60 DEG C, 80 DEG C, 100 DEG C, 120 DEG C etc..
Further, the time of annealing can be any suitable time, and what which also should be sufficient makes high k be situated between
There is transition metal element to diffuse into electric layer, illustratively, the time of the annealing can be 1min~20min, example
Such as, 5min, 10min, 15min etc..
It is handled using process annealing in this step, is mainly used for that transition metal element is made to diffuse into high k dielectric downwards
Layer, and since problem is relatively low, high k dielectric layer will not be made the problem of crystallization and crystal grain are grown up occur.
Make to be doped with transition metal element in high k dielectric layer by the annealing of this step, such as Mo and/or Ta.
Wherein, others well known to those skilled in the art can be made in high k dielectric layer doped with transition metal member
The method of element is equally applicable to the present invention, it is, for example, possible to use the method for ion implanting.
Then, step 6 is executed, removes the transition metal layer and the insulating layer successively
Specifically, as shown in figure iD, the transition metal layer and the insulating layer are removed successively, are situated between with exposing the high k
Electric layer 104.
The lithographic method of dry etching or wet etching can be used to remove transition metal layer and the insulating layer successively.
Dry etch process includes but not limited to：Reactive ion etching (RIE), ion beam etching, plasma etching or
Person is cut by laser.Dry etching is carried out preferably by one or more RIE step.
Illustratively, erodable transition metal layer can be also used first, but does not corrode the etchant removal of insulating layer
Transition metal layer reuses erodable insulating layer, but does not corrode the etchant removal insulating layer of high k dielectric layer.
Then, step 7 is executed, is made annealing treatment.
The annealing of this step can be any suitable method for annealing well known to those skilled in the art, such as quickly
Thermal annealing, furnace anneal, peak value annealing (spike anneal) etc..Such as annealing region is 700 DEG C~900 DEG C, for example,
700 DEG C, 750 DEG C, 800 DEG C, 850 DEG C, 900 DEG C etc., annealing time 30s~600s, the annealing is referred to as rear deposition anneal
(PDA)。
Wherein, since transition metal element (Mo and/or Ta) diffuses into high k dielectric layer, high k is especially diffused into
The surface layer of dielectric layer, therefore, in the annealing process of this step, transition metal element can inhibit the crystallization of high k dielectric layer,
Cubic phase (cubic phase) and smaller crystallite dimension are formed in high k dielectric layer, it can be to avoid production in crystallite dimension smaller
The raw leakage path along crystal boundary, therefore electric leakage of the grid can be reduced.
Illustratively, when transition metal element (Mo and/or Ta) is only entrained in the surface layer of the high k dielectric layer 104,
In annealing process, transition metal element can inhibit the crystallization on high k dielectric layer surface layer, be formed in the surface layer of high k dielectric layer vertical
Square phase (cubic phase) and smaller crystallite dimension, and be also possible to make the high k of surface layer undoped transition metal element below
Dielectric layer crystallizes in annealing process and obtains pure crystal orientation.
Then, B1 can also be followed the steps below to B3：
First, step B1 is executed, coating and protective layer are formed on the surface of the high k dielectric layer successively conformal deposited.
In one example, also optionally conformal deposited forms coating (not on the surface of high k dielectric layer 104
Show), wherein formed coating the step of can also after removal protective layer the step of after carry out.
The material of coating can be La2O3、AL2O3、Ga2O3、In2O3、MoO、Pt、Ru、TaCNO、Ir、TaC、MoN、WN、
TixN1-x or other suitable film layers.
The material of protective layer is amorphous semiconductor material.Wherein, the amorphous semiconductor material includes amorphous silicon
(a-Si) or amorphous Germanium (a-Ge), or other suitable amorphous semiconductor materials, in the present embodiment, protective layer
Material be preferably comprised a-Si.
The method for forming protective layer includes chemical vapour deposition technique (CVD), such as low temperature chemical vapor deposition (LTCVD), low
Pressure chemical vapor deposition (LPCVD), fast thermal chemical vapor deposition (LTCVD), plasma activated chemical vapour deposition (PECVD),
The general similar method such as sputter and physical vapour deposition (PVD) (PVD) can be used.
Wherein, the thickness range of the protective layer of formation is 40 angstroms to 120 angstroms, or other suitable thickness, herein
It is not specifically limited.
Then, step B2 is executed, is made annealing treatment.
The effect of the annealing is to improve the quality of the film layers such as high k dielectric layer and boundary layer.
Optionally, the temperature range of the annealing is 900 DEG C~1100 DEG C, or other suitable temperature.
The annealing can use any suitable method for annealing, such as furnace anneal, peak value annealing (spike
Anneal), laser annealing (laser anneal), pulsed electron beam short annealing, ion beam short annealing, continuous wave laser are fast
Fast annealing and non-coherent broad band light source (such as halogen lamp, arc lamp, graphite heating) short annealing.In the present embodiment, preferably, moving back
Fire processing uses peak value annealing or laser annealing.
Then, step B3 is executed, the protective layer is removed.
Any suitable method well known to those skilled in the art can be used to remove the protective layer, including but not limited to
The method of dry etching or wet etching.
In one example, the material of the protective layer includes amorphous silicon, then it includes tetramethyl hydroxide that can use
The etching agent wet etching of ammonium or ammonium hydroxide removes the protective layer.
Illustratively, when removing the protective layer, the temperature range of the etching agent is 25 DEG C~75 DEG C.
Finally, conventional metal gate structure technique is carried out, in one example, carries out processing step C1 to step C5：
Step C1, in the bottom and side wall of the gate trench in the NMOS device area and the PMOS device area
Form the first diffusion impervious layer；
Specifically, the first diffusion impervious layer also alternative setting, the material of the first diffusion impervious layer can be selected as but
It is not limited to TaN, Ta, TaAl or other suitable film layers.In the present embodiment, the materials'use TaN of the first diffusion impervious layer.
The suitable technique such as CVD, ALD or PVD may be used and form the first diffusion impervious layer.The thickness range of first diffusion impervious layer
It is 0 angstrom to 20 angstroms.
In one example, conformal deposited forms the first diffusion impervious layer in the cover surface.
Step C2 forms P-type workfunction layer in the bottom and side wall of the gate trench in the PMOS device area,
The P-type workfunction layer is located in the first diffusion barrier layer surface；
Specifically, its material of P-type workfunction layer can be selected as but be not limited to TixN1-x, TaC, MoN, TaN or they
Combination or other suitable film layers.In the present embodiment, P-type workfunction layer selects TiN.May be used CVD, ALD or
Technique suitable PVD etc. forms P-type workfunction layer.The thickness range of P-type workfunction layer is 10 angstroms to 580 angstroms, but is not limited to
The numberical range.
Step C3, in the bottom and side wall of the gate trench in the NMOS device area and the PMOS device area
Form N-type workfunction layer (not shown), wherein the N-type workfunction layer is located at the first diffusion resistance in NMOS device area
On barrier surface, the N-type workfunction layer is located on the P-type workfunction layer surface in the PMOS device area；
The material of N-type workfunction layer can be selected as but be not limited to TaAlC, TaC, Ti, Al, TixAl1-x or other are suitable
The film layer of conjunction.The material of N-type workfunction layer is preferably TiAl.The suitable technique shape such as CVD, ALD or PVD may be used
At N-type workfunction layer.The thickness range of N-type workfunction layer can be 10 angstroms to 80 angstroms.
Step C4, in the bottom and side wall of the gate trench in the NMOS device area and the PMOS device area
The second diffusion impervious layer is formed, second diffusion impervious layer is located on the N-type workfunction layer surface.
Also alternative setting, the material of the second diffusion impervious layer can be selected as but be not limited to second diffusion impervious layer
TaN, Ta, TaAl or other suitable film layers.
After forming above-mentioned film layer, flatening process can be also carried out, such as chemical mechanical grinding etc. stops at interlayer dielectric layer
Surface on, extra film layer on the surface of interlayer dielectric layer is removed.
Step C5 fills gate electrode in the gate trench in the NMOS device area and the PMOS device area
Layer, finally to form the first metal gate structure in PMOS device area and form the second metal gate structure in NMOS device area.
Illustratively, the full gate trench of gate electrode layer filling, and the surface of interlayer dielectric layer 101 is covered, then carry out flat
Change the surface that step stops at interlayer dielectric layer.
The material of gate electrode layer can be selected as but be not limited to Al, W or other suitable film layers.May be used CVD,
Technique suitable ALD or PVD etc. forms gate electrode layer.
So far the detailed description for completing the manufacturing method of the semiconductor devices to the present invention, for the system of complete device
Other processing steps are it may also be desirable to, this will not be repeated here.
In conclusion manufacturing method according to the invention, in the high k dielectric layer containing transition metal element (such as
Mo and/or Ta), the transition metal element inhibits the crystallization of high k dielectric layer during PDA anneals, in high k dielectric layer
Cubic phase (cubic phase) and smaller crystallite dimension are formed, therefore, method of the invention can reduce electric leakage of the grid, carry
The performance and yield of high device.
Embodiment two
The present invention also provides a kind of semiconductor devices, the semiconductor devices is by the manufacturing method in embodiment one above-mentioned
It prepares.
The structure of the semiconductor devices of the present invention is described in detail below with reference to Fig. 1 D.Wherein, main in the present embodiment
By taking FinFET as an example.
Specifically, semiconductor devices of the invention includes semiconductor substrate 100.
Specifically, as shown in Figure 1A, the semiconductor substrate 100 can be at least one in the following material being previously mentioned
Kind：Silicon, silicon-on-insulator (SOI), stacking silicon (SSOI) on insulator, stacking SiGe (S-SiGeOI), insulation on insulator
SiGe (SiGeOI) and germanium on insulator (GeOI) etc. on body.
Illustratively, the semiconductor substrate includes at least one of NMOS device area and PMOS device area.
In one example, the semiconductor substrate includes NMOS device area and PMOS device area, wherein in the NMOS
It is formed with gate trench 1021 in device region, gate trench 1022 is formed in the PMOS device area.
Illustratively, semiconductor devices of the invention is FinFET, then the semiconductor in the NMOS device area
It is formed with the first fin structure on substrate, the second fin knot is formed in the semiconductor substrate in each PMOS device area
Structure, the surface of the first fin structure described in 1021 exposed portion of the gate trench, described in 1022 exposed portion of gate trench
The surface of two fin structures.
In one example, the first metal gate structure (not shown) is formed in gate trench 1021, in the grid
The first metal gate structure (not shown) is formed in pole groove 1022.
In one example, first metal gate structure is across the first fin structure, the second metal gates knot
Structure is across the second fin structure.
In one example, interlayer dielectric layer 101, the grid are formed on the surface of the semiconductor substrate 100
Groove is formed in the interlayer dielectric layer 101.
In one example, it is formed on the side wall of first metal gate structure and second metal gate structure
There is clearance wall.
The clearance wall can be a kind of in silica, silicon nitride, silicon oxynitride or they combine and constitute.
In one example, it is given birth in the region of the first metal gate structure and the second metal gate structure both sides source/drain
Long stressor layers usually form the stressor layers with tensile stress, in PMOS transistor on the nmos transistors in CMOS transistor
It is upper to form the stressor layers with compression, the performance of cmos device can by by the action of pulling stress in NMOS, compression
PMOS is acted on to improve.Usually select SiC as tensile stress layer in NMOS transistor in the prior art, in PMOS transistor
In usually select SiGe as compressive stress layer.
Preferably, when growing the SiC as tensile stress layer, can epitaxial growth over the substrate, in ion implanting
Lifting source and drain is formed afterwards and usually forms groove in the substrate when forming the SiGe layer, is then sunk in the groove
Product forms SiGe layer.It is further preferred that forming " ∑ " connected in star in the substrate.
Illustratively, it is formed with high k dielectric layer 104 in the semiconductor substrate.
In one example, it is formed with gate trench on the semiconductor substrate, the high k dielectric layer is formed in described
In the bottom and side wall of gate trench, for example, high k dielectric layer be formed in gate trench 1021 and gate trench 1022 bottom and
On side wall.
The k values (dielectric constant) of high k dielectric layer 104 are usually 3.9 or more, and constituent material includes hafnium oxide, hafnium oxide
Silicon, nitrogen oxidation hafnium silicon, lanthana, zirconium oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, strontium barium oxide titanium, barium monoxide titanium, strontium oxide strontia
Titanium, aluminium oxide etc., preferably hafnium oxide, zirconium oxide or aluminium oxide.
Optionally, the thickness range of high k dielectric layer 104 is 10 angstroms to 30 angstroms, or other suitable thickness, herein
It is not specifically limited.
In one example, it is additionally provided with boundary layer 103 between the high k dielectric layer 104 and semiconductor substrate 100.
IL layers can be thermal oxide layer, nitrogen oxide layer, chemical oxide layer or other suitable film layers.It can be with
Using thermal oxide, chemical oxidation, chemical vapor deposition (CVD), atomic layer deposition (ALD) or physical vapour deposition (PVD) (PVD) etc.
Suitable technique forms boundary layer.
The thickness of boundary layer 103 can need to carry out reasonable set according to actual process, for example, the thickness model of boundary layer 103
Enclosing can be 5 angstroms to 10 angstroms.
Further, doped with transition metal element in the high k dielectric layer 104.Further, the transition metal
Element doping is in the surface layer of the high k dielectric layer.
Optionally, the transition metal element can be any suitable transition metal member well known to those skilled in the art
Element, in the present embodiment, preferably, the transition metal element includes (molybdenum) Mo and/or tantalum (Ta).
Wherein, due in high k dielectric layer doped with transition metal element (Mo and/or Ta), in annealing process,
Transition metal element can inhibit the crystallization of high k dielectric layer, formd in high k dielectric layer cubic phase (cubic phase) and
Smaller crystallite dimension, can be to avoid the leakage path generated along crystal boundary in crystallite dimension smaller, therefore can reduce grid
Electric leakage.
Illustratively, when transition metal element (Mo and/or Ta) is only entrained in the surface layer of the high k dielectric layer 104,
In annealing process, transition metal element can inhibit the crystallization of high k dielectric layer, and cubic phase is formed in the surface layer of high k dielectric layer
(cubic phase) and smaller crystallite dimension.
In one example, first metal gate structure include be sequentially formed at 1021 bottom of the gate trench and
High k dielectric layer 104, coating, the first diffusion impervious layer, N-type workfunction layer, the second diffusion impervious layer on side wall and filling
The gate electrode layer of the gate trench, and form the boundary layer between the high k dielectric layer 104 and semiconductor substrate 100
103。
In one example, second metal gate structure include be sequentially formed at 1022 bottom of the gate trench and
High k dielectric layer 104, coating, the first diffusion impervious layer, P-type workfunction layer, N-type workfunction layer, the second diffusion resistance on side wall
The gate electrode layer of barrier and the filling gate trench, and formed the high k dielectric layer 104 and semiconductor substrate 100 it
Between boundary layer 103.
Specifically, the first diffusion impervious layer also alternative setting, the material of the first diffusion impervious layer can be selected as but
It is not limited to TaN, Ta, TaAl or other suitable film layers.The thickness range of first diffusion impervious layer is 0 angstrom to 20 angstroms.
Its material of P-type workfunction layer can be selected as but be not limited to TixN1-x, TaC, MoN, TaN or combination thereof
Or other suitable film layers.In the present embodiment, P-type workfunction layer selects TiN.The thickness range of P-type workfunction layer is 10
Angstrom to 580 angstroms, but it is not limited to the numberical range.
The material of N-type workfunction layer can be selected as but be not limited to TaAlC, TaC, Ti, Al, TixAl1-x or other are suitable
The film layer of conjunction.The thickness range of N-type workfunction layer can be 10 angstroms to 80 angstroms.
Also alternative setting, the material of the second diffusion impervious layer can be selected as but be not limited to second diffusion impervious layer
TaN, Ta, TaAl or other suitable film layers.
The material of gate electrode layer can be selected as but be not limited to Al, W or other suitable film layers.
Due to the present invention semiconductor devices in high k dielectric layer doped with transition metal element (such as Mo and/or Ta),
It can inhibit the crystallization of high k dielectric layer in annealing process, form cubic phase and smaller crystallite dimension, it is therefore, of the invention
The leakage path in crystal boundary in high k dielectric layer significantly reduces, and effectively prevent electric leakage of the grid, has higher performance and yield.
Embodiment three
The present invention also provides a kind of electronic device, including the semiconductor devices described in embodiment two, the semiconductor devices
Part is prepared according to one the method for embodiment.
The electronic device of the present embodiment can be mobile phone, tablet computer, laptop, net book, game machine, TV
Any electronic product such as machine, VCD, DVD, navigator, Digital Frame, camera, video camera, recording pen, MP3, MP4, PSP is set
Standby or any intermediate products for including circuit.The electronic device of the embodiment of the present invention, due to the use of above-mentioned semiconductor
Device, thus there is better performance.
Wherein, Fig. 3 shows the example of mobile phone handsets.Mobile phone handsets 300, which are equipped with, to be included in shell 301
Display portion 302, operation button 303, external connection port 304, loud speaker 305, microphone 306 etc..
The wherein described mobile phone handsets include the semiconductor devices described in embodiment two, and the semiconductor devices includes：
Semiconductor substrate is formed with high k dielectric layer on the semiconductor substrate；
Doped with transition metal element in the high k dielectric layer.
The present invention is illustrated by above-described embodiment, but it is to be understood that, above-described embodiment is only intended to
The purpose of citing and explanation, and be not intended to limit the invention within the scope of described embodiment.In addition people in the art
It is understood that the invention is not limited in above-described embodiment, introduction according to the present invention can also be made more kinds of member
Variants and modifications, these variants and modifications are all fallen within scope of the present invention.Protection scope of the present invention by
The appended claims and its equivalent scope are defined.
Claims (14)
1. a kind of manufacturing method of semiconductor devices, which is characterized in that the method includes：
Semiconductor substrate is provided, forms high k dielectric layer on the semiconductor substrate；
The containing transition metal element in the high k dielectric layer；
Carry out the first annealing.
2. manufacturing method as described in claim 1, which is characterized in that it is formed with gate trench on the semiconductor substrate,
The high k dielectric layer is formed in the bottom and side wall of the gate trench.
3. manufacturing method as claimed in claim 1 or 2, which is characterized in that adulterate the transition gold in the high k dielectric layer
The method for belonging to element includes the following steps：
Transition metal layer is formed on the surface of the high k dielectric layer, the transition metal layer includes the transition metal element；
Carry out the second annealing, wherein second annealing makes the member of the transition metal in the transition metal layer
Element diffuses into the high k dielectric layer；
Remove the transition metal layer.
4. manufacturing method as claimed in claim 3, which is characterized in that before forming the transition metal layer, further include
The surface of the high k dielectric layer forms the step of insulating layer, after the removal transition metal layer and described first
The insulating layer is removed before annealing.
5. manufacturing method as described in claim 1, which is characterized in that described transition metal element doped in the high k dielectric
In the surface layer of layer.
6. manufacturing method as described in claim 1, which is characterized in that the transition metal element includes Mo and/or Ta.
7. manufacturing method as claimed in claim 4, which is characterized in that the thickness range of the transition metal layer is 20 angstroms~80
Angstrom, and/or, the thickness range of the insulating layer is 5 angstroms~20 angstroms.
8. manufacturing method as claimed in claim 3, which is characterized in that the temperature range of first annealing is 700 DEG C~900
DEG C, and/or, the temperature range of second annealing is 60 DEG C~150 DEG C.
9. manufacturing method as claimed in claim 1 or 2, which is characterized in that it is described first annealing after, further include with
Lower step：
Coating and protective layer are formed on the surface of the high k dielectric layer successively conformal deposited；
Carry out third annealing；
Remove the protective layer.
10. a kind of semiconductor devices, which is characterized in that including：
Semiconductor substrate is formed with high k dielectric layer on the semiconductor substrate；
Doped with transition metal element in the high k dielectric layer.
11. semiconductor devices as claimed in claim 10, which is characterized in that be formed with grid ditch on the semiconductor substrate
Slot, the high k dielectric layer are formed in the bottom and side wall of the gate trench.
12. semiconductor devices as claimed in claim 11, which is characterized in that described transition metal element doped in the high k
In the surface layer of dielectric layer.
13. semiconductor devices as claimed in claim 10, which is characterized in that the transition metal element includes Mo and/or Ta.
14. a kind of electronic device, which is characterized in that including the semiconductor devices described in one of claim 10 to 13.
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