CN102856377A - N-type semiconductor device and manufacturing method thereof - Google Patents
N-type semiconductor device and manufacturing method thereof Download PDFInfo
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Abstract
The invention discloses an n-type semiconductor device and a manufacturing method thereof. The n-type semiconductor device comprises a semiconductor substrate, a channel region, a gate stack and a source/drain region, wherein the channel region is located on the semiconductor substrate, the gate stack is located on the channel region, the gate stack comprises a gate dielectric layer and a gate electrode, the gate dielectric layer is located on the channel region, the gate electrode is located on the gate dielectric layer, the source/drain region is located on two sides of the channel region and embedded in the semiconductor substrate, and combination of one or a variety of Hf, La, Er, Y or Ta is distributed on at least one of the upper and lower surfaces of the gate dielectric layer and the lower surface of the gate electrode. The embodiment of the n-type semiconductor device and the manufacturing method thereof is suitable for manufacturing the metal oxide semiconductor field effect transistor (MOSFET).
Description
Technical field
The present invention relates to a kind of semiconductor device and manufacture method thereof, relate in particular to a kind of high-k gate dielectric/metal gate semiconductor device and manufacture method, it introduces aluminium element by upper and lower interface and metal gate electrode lower surface at high-k gate dielectric, helps the adjusting of N-shaped metal gate work function.
Background technology
Over more than 40 year, integrated circuit technique is by the sustainable development of mole law, and characteristic size is constantly dwindled, and integrated level improves constantly, and function is more and more stronger.At present, the characteristic size of mos field effect transistor (MOSFET) has entered inferior 50nm.Follow constantly reducing of device feature size, if the grid that still adopt traditional gate silicon oxide medium/polysilicon to form are stacking, gate medium electric leakage meeting exponentially rule sharply increases, and poly-Si depletion effect is more and more serious, and polysilicon resistance also can increase thereupon.In order to overcome above difficulty, it is stacking that industrial quarters begins to adopt high-k gate dielectric and metal gate electrode to form the traditional grid of novel grid stacked structure replacement.High-k gate dielectric has under the prerequisite of identical equivalent oxide thickness in maintenance, have higher physical thickness, thereby effectively reduced the gate medium electric leakage, and metal gate electrode can fundamentally be eliminated poly-Si depletion effect.
In order to obtain suitable threshold voltage, usually require the work function of nMOSFET metal gate material near 4.2eV, yet have the metal material poor chemical stability of low work function like this, easy and gate medium reacts, and causes the degeneration of device performance.Therefore adopt this metal material to regulate the work function of N-shaped device very unrealistic.
Therefore be necessary to introduce a kind of novel N-shaped semiconductor device and manufacture method thereof, in order to effectively regulate the work function of nMOSFET, improve performance of devices.
Summary of the invention
In order to solve the problems of the technologies described above, the present invention proposes a kind of novel N-shaped semiconductor device and manufacture method thereof, the work function that can effectively regulate nMOSFET is improved performance of devices.
According to an aspect of the present invention, provide a kind of semiconductor device, having comprised: Semiconductor substrate; Channel region is positioned on the Semiconductor substrate; Grid are stacking, are positioned on the channel region, and stacking gate dielectric layer and the gate electrode layer of comprising of grid, wherein, gate dielectric layer is positioned on the channel region, and gate electrode layer is positioned on the gate dielectric layer; Source/drain region is arranged in the channel region both sides and embeds Semiconductor substrate; Wherein, at least one surface distributed in the lower surface of upper surface, lower surface and the described gate electrode of gate dielectric layer has one or more the combination among Hf, La, Er, Y or the Ta.
Preferably, Hf, La, Er, Y, Ta element are combined with O and are formed Hf-O, La-O, Er-O, Y-O, Ta-O electric dipole.
Alternatively, described gate dielectric layer comprises the high-k gate dielectric layer that contains Hf, La, Er, Y or Ta; Perhaps gate dielectric layer can comprise first medium layer and second medium layer, and wherein, the first medium layer is high-k gate dielectric layer, and the second medium layer is oxide or the nitride layer that contains Hf, La, Er, Y or Ta, and thickness is 2-15
And be arranged in upper surface and at least one place of lower surface of first medium layer.
In such scheme, described high-k gate dielectric layer comprises: HfON, HfLaON, HfSiON, HfTaON, La
2O
3, Er
2O
3, Y
2O
3In any one or more combination.
Alternatively, described gate electrode layer comprises and contains the first metal layer, and described the first metal layer is the metal nitride layer that contains Hf or Ta, for example can comprise: the combination of any one or more among HfN, the TaN.
Alternatively, described gate electrode layer further comprises the second metal level that is positioned on the described the first metal layer, and described the second metal level can comprise Mo, W or its combination.
Preferably, further comprise oxide skin(coating) between gate dielectric layer and Semiconductor substrate, this oxide skin(coating) is conducive to form Hf-O, La-O, Er-O, Y-O, Ta-O electric dipole at the lower surface of gate dielectric layer.
According to another aspect of the present invention, provide a kind of preparation method of semiconductor device, having comprised: Semiconductor substrate is provided; Form grid in Semiconductor substrate stacking, stacking gate dielectric layer and the gate electrode layer of comprising of grid, gate dielectric layer is formed on the channel region, and gate electrode layer is formed on the gate dielectric layer; The both sides stacking at grid form side wall; Embed Semiconductor substrate in the stacking both sides of grid and form source/drain region; Wherein, in the upper surface of gate dielectric layer and at least one surface distributed in the lower surface one or more combination among Hf, La, Er, Y or the Ta is arranged.
Preferably, describedly form the stacking step of grid in Semiconductor substrate and comprise: form gate dielectric layer in described Semiconductor substrate; Form gate electrode layer at described gate dielectric layer; Described gate electrode layer and gate dielectric layer are carried out the patterning etching, stacking to form grid.
Wherein, the step at described Semiconductor substrate formation gate dielectric layer can comprise: form successively the gate dielectric layer that comprises first medium layer and second medium layer on described Semiconductor substrate; Described gate dielectric layer is carried out thermal anneal process in oxygenous nitrogen, the content of Oxygen in Nitrogen is 1%-10%; Wherein, the first medium layer is high-k gate dielectric layer, and the second medium layer is oxide or the nitride layer that contains Hf, La, Er, Y or Ta, and is arranged at least one place of upper surface and the lower surface of first medium layer.Behind the thermal annealing, the Hf in the gate dielectric layer, La, Er, Y, Ta are combined with O and are formed Hf-O, La-O, Er-O, Y-O, Ta-O electric dipole.
Preferably, the step at gate dielectric layer formation gate electrode layer comprises: form the first metal layer at gate dielectric layer, the first metal layer is the metal nitride layer that contains Hf, La, Er, Y or Ta; Form the second metal level at the first metal layer.
Wherein, the second metal level can comprise Mo, W or its combination.
Preferably, before the formation grid were stacking, the method further comprised: form oxide layer in Semiconductor substrate.
Preferably, behind formation source/drain region, the method further comprises: carry out thermal anneal process so that Hf, La, Er, Y, the Ta element of described grid in stacking forms Hf-O, La-O, Er-O, Y-O, Ta-O electric dipole to described grid are stacking.
This semiconductor structure provided by the invention and preparation method thereof, because the introducing of Hf, La, Er, Y or Ta element, through high annealing gate dielectric layer and gate electrode at the interface and the at the interface formation electric dipole between gate dielectric layer and the Semiconductor substrate, cause the at the interface variation of energy level, the flat band voltage of metal gate is moved to negative sense, be conducive to the adjusting of NMOS metal gate work function.
Description of drawings
By referring to the description of accompanying drawing to the embodiment of the invention, above-mentioned and other purposes of the present invention, feature and advantage will be more clear, in the accompanying drawings:
Fig. 1-4 shows the structural representation of the semiconductor device that obtains according to the embodiment of the invention;
Fig. 5-9 shows the sectional view according to device architecture corresponding to each step in the flow process of embodiment of the invention manufacturing semiconductor device.
Shown in Figure 10 is flat band voltage and the equivalent oxide layer (V that adopts the semiconductor device of the present invention's preparation
FB-EOT) relation curve is 4.3eV by calculating the work function that can obtain metal gate.
Be the electrology characteristic that adopts the nMOSFET of the present invention's preparation shown in Figure 11 and 12, threshold voltage is 0.24V, and saturation current is from 1.17 * 10
-4A/ μ m (| V
GS|=| V
DS|=1.5V).
Description of reference numerals:
1000, Semiconductor substrate; 1002, channel region; 1004, the second medium layer; 1006, first grid dielectric layer; 1008, the second medium layer; 1010, the first metal layer; 1012, the second metal levels; 1014, polysilicon; 1016, side wall; 1018, source/drain region; 1020, metal silicide; 1022, shallow trench isolation from; 102, gate dielectric layer; 104, gate electrode layer.
Embodiment
Below, by the specific embodiment shown in the accompanying drawing the present invention is described.But should be appreciated that, these descriptions are exemplary, and do not really want to limit the scope of the invention.In addition, in the following description, omitted the description to known configurations and technology, to avoid unnecessarily obscuring concept of the present invention.
Layer structural representation according to the embodiment of the invention shown in the drawings.These figure draw in proportion, wherein for purpose clearly, have amplified some details, and may omit some details.The shape of the various zones shown in the figure, layer and the relative size between them, position relationship only are exemplary, may be because manufacturing tolerance or technical limitations and deviation to some extent in the reality, and those skilled in the art according to reality required can design in addition have difformity, the regions/layers of size, relative position.
Fig. 1 shows the semiconductor device that obtains according to one embodiment of present invention.Wherein, this semiconductor device comprises: Semiconductor substrate 1000; Channel region 1002 is positioned on the Semiconductor substrate 1000; Grid are stacking, are positioned on the channel region 1002, and stacking gate dielectric layer 102 and the gate electrode layer 104 of comprising of grid, gate dielectric layer 102 is positioned on the channel region 1002, and gate electrode 104 is positioned on the gate dielectric layer 102; Source/drain region 1018 is arranged in channel region 1002 both sides and embeds Semiconductor substrate; Wherein, in the upper surface of gate dielectric layer 102 and at least one surface distributed in the lower surface one or more combination among Hf, La, Er, Y or the Ta is arranged, be preferably in this embodiment the Hf element.
Preferably, the upper surface in gate electrode layer 104 and source/drain region 1018 also comprises metal silicide 1020.Wherein, the both sides of device also include isolation structure 1022, for example can be shallow trench isolation from or other isolation structures.
Preferably, gate dielectric layer 102 is Hf base high K medium material, for example can comprise among HfON, HfLaON, HfSiON, the HfTaON any or several, be preferably in this embodiment HfSiON; Comprise the metal nitride layer that contains Hf or Ta in the gate electrode layer 104, be preferably in this embodiment TaN, and be preferably the laminated construction of metal nitride/polysilicon; At the upper surface of gate dielectric layer 102 and at least one surface distributed in the lower surface Hf element is arranged.
With reference to Fig. 2, can see the enlarged diagram that element distributes in gate dielectric layer 102 and the gate electrode layer 104.That is, in a preferred embodiment of the invention, all be distributed with the Hf element at gate dielectric layer 102 upper surfaces and lower surface, and formed the Hf-O electric dipole; Be distributed with the Ta element at gate electrode layer 104 lower surfaces, and formed the Ta-O electric dipole.
Be illustrated in figure 3 as the semiconductor device that obtains according to another embodiment of the present invention.With upper first difference of an embodiment be that wherein gate dielectric layer 102 has comprised second medium layer 1004, first medium layer 1006 and second medium layer 1008.Second medium layer 1004 is identical with the material of second medium layer 1008, for example can comprise the oxide of Hf, La, Er, Y or Ta or in the nitride layer any or several, thickness is 2-15
First medium layer 1006 is high-k gate dielectric layer.In the present embodiment, second medium layer 1004 is preferably HfNx with second medium layer 1008, and first medium layer 1006 is preferably HfSiON.With reference to figure 4, wherein the Hf element is distributed in the lower surface of second medium layer 1004 and the upper surface of second medium layer 1008.
Further preferably, in the present embodiment, gate electrode layer 104 has comprised the first metal layer 1010, the second metal level 1012 and polysilicon layer 1014, wherein, the first metal layer 1010 can comprise the metal nitride layer that contains Hf or Ta, and the second metal level 1012 can comprise Mo or W and combination thereof.In the present embodiment, the first metal layer 1010 is preferably the metal nitride layer of TaNx, and the second metal level 1012 is preferably W.With reference to figure 4, the Ta element is distributed in the lower surface of the first metal layer 1010.
Semiconductor device in embodiments of the present invention is N-shaped MOSFET.
In an embodiment of the present invention, between the Hf at Semiconductor substrate and gate dielectric layer interface and O element, can form chemical valence, between the Ta at gate electrode layer and gate dielectric layer interface and O element, also can form chemical valence, because its electronegativity is different, thereby forming at the interface Hf-O and Ta-O electric dipole, cause the at the interface variation of energy level, its performance is that the Fermi level of metal gate moves to the conduction band direction, gate work function reduces, thereby helps the adjustment of N-shaped metal oxide semiconductor device metal gate work function.
In one embodiment of the invention, further comprise the thin oxide layer (not shown) between gate dielectric layer 102 or second medium layer 1004 and the channel region 1002, help the formation of Hf-O electric dipole, can improve interface performance simultaneously.
Fig. 5～9 show in detail the sectional view of making each step in the semiconductor device flow process according to the embodiment of the invention.Below, come each step according to the embodiment of the invention is described in detail with reference to these accompanying drawings.
At first, as shown in Figure 5, provide Semiconductor substrate 1000.Substrate 1000 can comprise any suitable semiconductor substrate materials, specifically can be but is not limited to silicon, germanium, SiGe, SOI (semiconductor-on-insulator), carborundum, GaAs or any III/V compound semiconductor etc.In addition, Semiconductor substrate 1000 can comprise epitaxial loayer alternatively, can be by stress changes to strengthen the property.For embodiments of the invention, the preferred Si substrate that adopts the N-shaped impurity that mixed.
Then, form isolation structure in Semiconductor substrate 1000, preferably adopt shallow trench isolation from (Shallow Trench Isolation, STI).Also can adopt other isolation structures in an embodiment of the present invention, isolation structure and purport of the present invention are irrelevant, repeat no more here.
Alternatively, can form oxide skin(coating) (not shown among Fig. 5) in Semiconductor substrate 1000, can improve interface performance.Particularly, can be in containing the nitrogen of trace oxygen, and under 600-800 ℃ of temperature, Semiconductor substrate is carried out rapid thermal oxidation 30-120S, generate 5-8
Oxide skin(coating).
Then, form gate dielectric layer at oxide skin(coating).Particularly, at first form second medium layer 1004, be preferably HfN
XThen form first medium layer 1006 at second medium layer 1004, first medium layer 1006 is Hf base high-k gate dielectric layer, is preferably HfSiON; Then, form second medium layer 1008 at first medium layer 1006, the material of second medium layer 1008 is identical with the material of second medium layer 1004.Then, gate dielectric layer is carried out annealing in process in containing the nitrogen of trace oxygen, as shown in Figure 4, the Hf element is distributed in upper surface and the lower surface of gate dielectric layer, is specially the lower surface of second medium layer 1004 and the upper surface of second medium layer 1008.
The following specifically describes the formation of gate dielectric layer according to a preferred embodiment of the present invention.At first form oxide skin(coating) in Semiconductor substrate 1000, then form gate dielectric layer at oxide skin(coating), gate dielectric layer can be for comprising the lamination of HfNx/HfSiON/HfNx, wherein, HfNx can adopt reactive magnetron sputtering technique to be prepared as the second medium layer, and sputtering atmosphere is the mist of argon gas and nitrogen, sputtering power is 200-500W, can regulate the content of the N in the HfNx film by regulating nitrogen flow; The high k film of HfSiON can adopt magnetron sputtering technique or atomic layer deposition technique to form as the first medium layer.Then the HfNx/HfSiON/HfNx laminated gate medium is carried out quick thermal annealing process in containing the nitrogen of trace oxygen, preferred oxygen content is 1-10%, and preferred annealing temperature is 700-1000 ℃, and the time can be 10-50S.As shown in Figure 4, wherein, the O of the Hf in the second medium layer 1004 in oxide layer is combined and formed the Hf-O electric dipole; The O of Hf in the second medium layer 1008 in surrounding atmosphere is combined and formed the Hf-O electric dipole.
Then, as shown in Figure 6, continue to form gate electrode layer at gate dielectric layer.Particularly, at first form the first metal layer 1010 and the second metal level 1012 at second medium layer 1008.Wherein, the first metal layer 1010 is preferably TaN, and the second metal level 1012 is preferably W.Then, the embodiment of the invention also preferably forms polysilicon (Poly) layer 1014 again on the second metal level.
In a preferred embodiment of the invention, form the stack gate electrode structure of TaN/W/Poly, wherein TaN is as the first metal layer, and W is as the second metal level.Concrete formation method is, at first, adopts reactive magnetron sputtering technique to prepare TaN, and sputtering atmosphere is the mist of argon gas and nitrogen, and sputtering power is 200-1000W, and operating pressure is (2-8) * 10
-3Torr, the sputter tantalum target, deposit forms the TaN metal gate; Then, adopt reactive magnetron sputtering technique to prepare W, sputtering atmosphere is argon gas, and sputtering power is 200-1000W, and operating pressure is (2-8) * 10
-3Torr, the sputter tungsten target, deposit forms the W metal gate; At last, further adopt low-pressure vapor phase deposit (LPCVD) technique deposit 1000-2000 on the second metal level 1012
Polysilicon membrane 1014.
Then, can carry out the patterning etching to form the grid stacked structure.Particularly, spin coating photoresist on polysilicon layer 1014, the pattern stacking according to the grid that will form carries out patterning to photoresist, and then the photoresist behind the patterning forms as shown in Figure 7 grid stacked structure as mask etching.
Below will finish according to common process the source/drain region of device.
At first, whole semiconductor device structure being carried out source/drain extension region injects.Because need to form nMOSFET, can inject As or P ion.Alternatively, further carry out halo (Halo) and inject, for example can inject BF
2Or B, thereby below grid are stacking, form halo injection region (not shown) in corresponding channel region 1002 or the substrate 1000 below the channel region 1002.
Then as shown in Figure 8, around the stacking formation side wall of grid.Particularly, can adopt PECVD (Plasma-Enhanced Chemical Vanor Denosition, plasma-reinforced chemical vapor deposition) mode to form Si
3N
4Layer, thickness can be 500-900
Then adopting dry etch process, for example is that RIE (Reactive-Ion Etching, reactive ion etching) anti-carves formation Si
3N
4Side wall.
As shown in Figure 9, carry out source/leakage and inject, for example inject As or P, formation source/drain region 1018.
Different from routine techniques is, in order to form the Ta-O electric dipole, behind formation source/drain region, need to anneal, and annealing temperature can be 800-1200 ℃, and annealing time can be 3-10S.At this moment, as shown in Figure 4, the lower surface of the first metal layer 1010 is concentrated a large amount of O atom of Ta in gate dielectric layer to be combined and is formed the Ta-O electric dipole.
Such as Fig. 9, according to the formation method of conventional device, in source/drain region 1018 and the upper surface of polysilicon layer 1014 form metal silicide 1020.The step that forms metal silicide 1020 also can superincumbent annealing steps before.
At last, the device formation method according to routine forms interlayer dielectric layer at whole semiconductor device structure, and in interlayer dielectric layer the contacting of formation and grid and source/leakage.
Embodiments of the invention, by in gate dielectric layer, introducing the hafnium element and in gate electrode layer, introducing tantalum element, after source/leakage activates annealing process, the Hf element that is arranged in Semiconductor substrate and high-k gate dielectric interface can form chemical valence with the O element of gate medium, the Hf and the Ta element that are arranged in gate electrode and high-k gate dielectric interface can form chemical valence with the O element of gate medium, because its electronegativity is different, thereby forming at the interface Hf-O and Ta-O electric dipole, cause the at the interface variation of energy level, the flat band voltage of metal gate is moved to forward, its performance is that the metal gate Fermi level moves to the conduction band direction, gate work function reduces, thereby helps the adjustment of N-type metal oxide semiconductor device metal gate work function.Simultaneously, by increasing the thickness contain at the interface HfNx and TaN film, can increase the at the interface content of Hf and Ta element, form more electric dipole, increase the work function regulating power.
Experimental result shows, the thickness of second medium layer (HfNx) 1004,1008 is 5.5
And the thickness of the first metal layer (TaN) 1010 is 500
The time, the work function of nMOSFET is 4.3eV.
In addition, the employing of high-k gate dielectric has higher physical thickness in the less equivalent oxide thickness of maintenance, be conducive to reduce the gate medium Leakage Current; The employing of metal gate can solve poly-Si depletion effect and the serious problem that increases of gate resistance brought along with reducing of small size device characteristic size.
In above description, do not make detailed explanation for ins and outs such as the composition of each layer, etchings.Can be by various means of the prior art but it will be appreciated by those skilled in the art that, form layer, zone of required form etc.In addition, in order to form same structure, those skilled in the art can also design and the not identical method of method described above.
Abovely with reference to embodiments of the invention the present invention has been given explanation.But these embodiment only are for illustrative purposes, and are not in order to limit the scope of the invention.Scope of the present invention is limited by claims and equivalent thereof.Do not depart from the scope of the present invention, those skilled in the art can make a variety of substitutions and modifications, and these substitutions and modifications all should fall within the scope of the present invention.
Claims (17)
1. N-shaped semiconductor device comprises:
Semiconductor substrate;
Channel region is positioned on the described Semiconductor substrate;
Grid are stacking, are positioned on the described channel region, and stacking gate dielectric layer and the gate electrode layer of comprising of described grid, described gate dielectric layer is positioned on the described channel region, and described gate electrode layer is positioned on the gate dielectric layer;
Source/drain region is arranged in described channel region both sides and embeds described Semiconductor substrate;
Wherein, at least one surface distributed in the lower surface of upper surface, lower surface and the described gate electrode of described gate dielectric layer has one or more the combination among Hf, La, Er, Y or the Ta.
2. semiconductor device according to claim 1, wherein, described gate dielectric layer comprises the high-k gate dielectric layer that contains Hf, La, Er, Y or Ta.
3. semiconductor device according to claim 1, wherein, described gate dielectric layer comprises first medium layer and second medium layer;
Wherein, the first medium layer is high-k gate dielectric layer, and described second medium layer is oxide or the nitride layer that contains Hf, La, Er, Y or Ta, and is arranged in top or following at least one place of described first medium layer.
4. semiconductor device according to claim 3, wherein, the thickness of described second medium layer is 2-15
5. semiconductor device according to claim 1, wherein, described Hf, La, Er, Y, Ta element with the formal distribution of Hf-O, La-O, Er-O, Y-O, Ta-O electric dipole on described any surface.
6. according to claim 2 or 3 described semiconductor device, wherein, described high-k gate dielectric layer comprises: HfON, HfLaON, HfSiON, HfTaON, La
2O
3, Er
2O
3, Y
2O
3In any one or more combination.
7. semiconductor device according to claim 1, described gate electrode layer comprises the first metal layer, described the first metal layer is the metal nitride layer that contains Hf or Ta.
8. semiconductor device according to claim 7, described gate electrode layer further comprises the second metal level that is positioned on the described the first metal layer.
9. semiconductor device according to claim 8, wherein, described the second metal level comprises Mo, W or its combination.
10. each described semiconductor device in 6 according to claim 1 wherein, further comprises oxide skin(coating) between described gate dielectric layer and Semiconductor substrate.
11. the manufacture method of a N-shaped semiconductor device comprises:
Semiconductor substrate is provided;
Form grid in described Semiconductor substrate stacking, stacking gate dielectric layer and the gate electrode layer of comprising of described grid, described gate dielectric layer is formed on the described channel region, and described gate electrode layer is formed on the gate dielectric layer;
The both sides stacking at described grid form side wall;
Embed described Semiconductor substrate in the stacking both sides of described grid and form source/drain region;
Wherein, at least one surface distributed in the lower surface of upper surface, lower surface and the described gate electrode of described gate dielectric layer has Hf, La, Er, Y or Ta element.
12. method according to claim 11 wherein, describedly forms the stacking step of grid in Semiconductor substrate and comprises:
Form gate dielectric layer in described Semiconductor substrate;
Form gate electrode layer at described gate dielectric layer;
Described gate electrode layer and gate dielectric layer are carried out the patterning etching, stacking to form grid.
13. method according to claim 12, wherein, the step that forms gate dielectric layer in described Semiconductor substrate comprises:
Form the gate dielectric layer that comprises first medium layer and second medium layer in described Semiconductor substrate;
Described gate dielectric layer is carried out thermal anneal process so that the Hf in the described gate dielectric layer, La, Er, Y, Ta form Hf-O, La-O, Er-O, Y-O, Ta-O electric dipole in oxygenous nitrogen;
Wherein, the first medium layer is high-k gate dielectric layer, and described second medium layer is oxide or the nitride layer that contains Hf, La, Er, Y or Ta, and is arranged in top or following at least one place of described first medium layer.
14. method according to claim 13, wherein, the content of described Oxygen in Nitrogen is 1%-10%.
15. method according to claim 12, wherein, described step at described gate dielectric layer formation gate electrode layer comprises:
Form the first metal layer at described gate dielectric layer, described the first metal layer is the metal nitride layer that contains Hf or Ta;
Form the second metal level at described the first metal layer, described the second metal level is for containing Mo, W or its combination.
16. method according to claim 11, wherein, before the formation grid were stacking, described method further comprised: form oxide layer in described Semiconductor substrate.
17. each described method in 16 according to claim 11, wherein, behind formation source/drain region, described method further comprises: carry out thermal anneal process so that Hf, La, Er, Y, the Ta of described grid in stacking forms Hf-O, La-O, Er-O, Y-O, Ta-O electric dipole to described grid are stacking.
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| TWI779380B (en) * | 2019-10-31 | 2022-10-01 | 台灣積體電路製造股份有限公司 | A semiconductor device and a method of fabricating the same |
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| CN104377236A (en) * | 2013-08-16 | 2015-02-25 | 中国科学院微电子研究所 | Gate stack and manufacturing method thereof |
| CN105097901A (en) * | 2015-07-16 | 2015-11-25 | 中国科学院微电子研究所 | Composite gate dielectric layer applied to III-V substrate and fabrication method of composite gate dielectric layer |
| CN105097901B (en) * | 2015-07-16 | 2018-05-08 | 中国科学院微电子研究所 | Composite gate dielectric layer applied to iii-v substrate and preparation method thereof |
| CN108630538A (en) * | 2017-03-17 | 2018-10-09 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and its manufacturing method and electronic device |
| TWI779380B (en) * | 2019-10-31 | 2022-10-01 | 台灣積體電路製造股份有限公司 | A semiconductor device and a method of fabricating the same |
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