CN105097901B - Composite gate dielectric layer applied to iii-v substrate and preparation method thereof - Google Patents

Composite gate dielectric layer applied to iii-v substrate and preparation method thereof Download PDF

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CN105097901B
CN105097901B CN201510418996.2A CN201510418996A CN105097901B CN 105097901 B CN105097901 B CN 105097901B CN 201510418996 A CN201510418996 A CN 201510418996A CN 105097901 B CN105097901 B CN 105097901B
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passivation layer
substrate
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interface
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CN105097901A (en
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王盛凯
刘洪刚
孙兵
常虎东
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Institute of Microelectronics of CAS
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28264—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being a III-V compound
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate

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Abstract

The invention discloses a kind of composite gate dielectric layer applied to III V races substrate and preparation method thereof, which includes：It is formed at the Al of III V races substratexY2‑xO3Interface passivation layer；And it is formed at the AlxY2‑xO3High dielectric insulation layer on interface passivation layer；Wherein 1.2≤x≤1.9.The composite gate dielectric layer is by adjusting AlxY2‑xO3The Al/Y ratios of interface passivation layer, change AlxY2‑xO3Average atom ligancy in interface passivation layer, reduces the III V races substrate interface density of states and bound trap density, adds MOS channel mobilities；Pass through AlxY2‑xO3The cooperation of interface passivation layer and high dielectric insulation layer, reduces gate leak current, and improves the voltage endurance capability of dielectric layer, improves the quality of III V races substrate MOS capacitance and enhances its reliability.

Description

Composite gate dielectric layer applied to iii-v substrate and preparation method thereof
Technical field
The present invention relates to the gate stack structure applied to iii-v substrate, especially a kind of iii-v that is applied to serves as a contrast The composite gate dielectric layer at bottom and preparation method thereof.
Background technology
With the continuous development of microelectric technique, the iii-v with InGaAs, InP, InAs, GaAs, GaSb etc. for representative Compound semiconductor has the electron mobility or hole mobility better than silicon because of it, it is considered to be as rear mole of Age of Technology Substituted for silicon raceway groove makes the important candidate materials of Metal-oxide-semicondutor (MOS) field-effect transistor.
Iii-v substrate, in the prevalence of substantial amounts of interface defect density, usually compares SiO with gate medium interface2The boundary of/Si The high 1-2 order of magnitude of face trap density, high interface trap density can substantially reduce the mobility of carrier, cause conducting resistance Increase, power consumption increase.At present, industry scientific research scholar is by using the surface A l based on technique for atomic layer deposition2O3Passivation, interface The methods of vulcanizing and is surfaces nitrided, the interface quality and overall permanence of gate medium/iii-v substrate have certain lifting, But and SiO2/ Si interface qualities, which are compared, still no small gap.
In addition, in terms of device reliability and device power consumption, iii-v substrate is also faced with many choose with gate dielectric structure War.The shortcomings that most of gate dielectric structure so far leaks electricity greatly in the prevalence of gate medium, poor reliability.How in III- V races substrate surfaces prepares high reliability, the gate dielectric structure of low defect interface state density and ultralow oxide thickness of equal value into To realize key technology that iii-v substrate is applied in rear mole of Age of Technology logical device.
The content of the invention
(1) technical problems to be solved
In view of this, it is a primary object of the present invention to the deficiency for above-mentioned prior art, there is provided one kind is applied to Composite gate dielectric layer of iii-v substrate and preparation method thereof, to reduce interface state density and bound trap density, increases III- V races MOS channel mobilities, reduce gate leak current, and further improve the voltage endurance capability of dielectric layer, improve iii-v substrate MOS Quality and strengthen its reliability.
(2) technical solution
To reach above-mentioned purpose, the present invention provides a kind of composite gate dielectric layer applied to iii-v substrate, including： It is formed at the Al of iii-v substratexY2-xO3Interface passivation layer；And it is formed at the AlxY2-xO3On interface passivation layer High dielectric insulation layer；Wherein 1.2≤x≤1.9.
In such scheme, the iii-v substrate include GaAs substrates, InP substrate, GaSb substrates, InAs substrates or InGaAs substrates and its epitaxial wafer, its doping concentration are more than or equal to 1 × 1015cm-3And less than or equal to 5 × 1017cm-3。
In such scheme, the AlxY2-xO3The thickness of interface passivation layer is more than or equal to 0.4nm and is less than or equal to 4nm.
In such scheme, the high dielectric insulation layer includes HfO2、ZrO2、La2O3Or Y2O3, and pass through above-mentioned four kinds of materials Expect ternary or the multi-element compounds being obtained by mixing, which is more than or equal to 0nm and is less than or equal to 4nm。
To reach above-mentioned purpose, present invention also offers a kind of system of the composite gate dielectric layer applied to iii-v substrate Make method, including：
Step 1：Iii-v substrate is cleaned, grows Al in the iii-v substrate2OmPassivation layer, wherein 2.5≤m≤ 3；
Step 2：In the Al2OmY is grown on passivation layer2OnStrengthening layer, wherein 2.5≤n≤3；
Step 3：To Al2OmPassivation layer and Y2OnStrengthening layer carries out situ heat treatment, realizes Al2OmPassivation layer and Y2OnStrengthen The mixing of layer, obtains AlxY2-xO3Interface passivation layer, wherein 1.2≤x≤1.9；
Step 4：In the AlxY2-xO3High dielectric insulation layer is grown on interface passivation layer.
In such scheme, Al is grown in iii-v substrate described in step 12OmPassivation layer, including：Utilize atomic layer The method of deposit, in iii-v substrate growth thickness is d under the conditions of 200 DEG C -400 DEG C1The Al of nanometer2OmPassivation layer, Wherein 0.2nm≤d1≤3.8nm。
In such scheme, this method adjusts Al by adjusting 200 DEG C of -400 DEG C of atomic layer deposition temperature2OmIn passivation layer The content of oxygen, wherein 200 DEG C of Al for tending to form low oxygen content2OmPassivation layer, m=2.5；400 DEG C are tended to form hyperoxia and contain The Al of amount2OmPassivation layer, m=3；Al2OmRelatively low oxygen content in passivation layer, it is possible to increase Al2OmAl-O tetrahedrons in passivation layer The flexibility of network, increases Al2OmThe rotatable characteristic of Al-O tetrahedrons in passivation layer, so as to fulfill for iii-v substrate The passivation of surface defect；Al2OmHigher oxygen content in passivation layer, can reduce the electric leakage of composite gate dielectric layer and be lifted reliable Property.
In such scheme, in Al described in step 22OmY is grown on passivation layer2OnStrengthening layer, including：Utilize atomic layer The method of deposit, in Al under the conditions of 200 DEG C -400 DEG C2OmGrowth thickness is d on passivation layer2The Y of nanometer2OnStrengthening layer, its Middle 0.4nm≤d1+d2≤4nm。
In such scheme, this method adjusts Y by adjusting 200 DEG C of -400 DEG C of atomic layer deposition temperature2OnOxygen in strengthening layer Content, wherein 200 DEG C of Y for tending to form low oxygen content2OnStrengthening layer, n=2.5；400 DEG C are tended to form elevated oxygen level Y2OnStrengthening layer, n=3.
In such scheme, to Al described in step 32OmPassivation layer and Y2OnStrengthening layer carries out situ heat treatment, is by Al2Om Passivation layer and Y2OnStrengthening layer carries out in-situ annealing processing under the conditions of 200 DEG C -400 DEG C in atomic layer deposition apparatus.
In such scheme, this method realizes Al by adjusting the temperature of situ heat treatment2OmPassivation layer and Y2OnStrengthening layer Mixing according to a certain percentage, mixing ratio is by Al2OmPassivation layer thickness d1With Y2OnStrengthening layer thickness d2Ratio d1:d2Determine, wherein 19:1≤d1:d2≤1:19；This method passes through Al2OmPassivation layer and Y2OnStrengthening layer is mixed to get AlxY2-xO3Interface passivation layer, Realize AlxY2-xO3The regulation and control of the average coordination number 2.8 to 4.2 of interface passivation layer, and then meet that various devices are close to boundary defect The demand of degree and reliability, wherein, average coordination number 2.8 is in d1:d2Equal to 19:1st, obtained under conditions of m=3 and n=3 's；Average coordination number 4.2 is in d1:d2Equal to 1:19th, obtained under conditions of m=2.5 and n=2.5.
In such scheme, the AlxY2-xO31.2≤x≤1.9 are the more excellent knots as interface passivation layer in interface passivation layer Fruit, the AlxY2-xO3The average coordination number of interface passivation layer is between 3.28 to 2.86, and average coordination number is during wherein x=1.2 Average coordination number is 2.86 when 3.28, x=1.9.
In such scheme, in Al described in step 4xY2-xO3High dielectric insulation layer is grown on interface passivation layer, is to utilize original The method of sublayer deposit, in Al under the conditions of 200 DEG C -400 DEG CxY2-xO3On interface passivation layer deposition thickness be more than or equal to 0nm and High dielectric insulation layer less than or equal to 4nm.
(3) beneficial effect
It can be seen from the above technical proposal that the invention has the advantages that：
1st, composite gate dielectric layer provided by the invention applied to iii-v substrate and preparation method thereof, using AlxY2-xO3 Interface passivation layer, by adjusting Al2OmIn oxygen concentration and mix Y thereto2On, softened Al2OmNetwork, makes Al-O tetra- There is more twisting frees degree, Al between the body of facexY2-xO3Be more easy to iii-v substrate surface defect bonding, realize that interface lacks Sunken passivation.
2nd, composite gate dielectric layer provided by the invention applied to iii-v substrate and preparation method thereof, using AlxY2-xO3 Interface passivation layer, by adjusting Al2OmIn oxygen concentration and mix Y thereto2On, improve AlxY2-xO3Average coordination number, Make wherein Al-O tetrahedrons although it can twist still in the Y of seven coordinations3+It is attracted under ionization in Y3+Nearby so as to Become finer and close, which has lower Gibbs system free energys, is also less likely to occur under the effect of larger electric stress Ion scission of link, so as to reduce gate leak current, improves reliability.
3rd, composite gate dielectric layer provided by the invention applied to iii-v substrate and preparation method thereof, using AlxY2-xO3 Interface passivation layer, with single Al2O3Interface passivation layer compares (dielectric constant k is about 8), the Al that the present invention usesxY2-xO3Boundary Face passivation layer dielectric constant higher (dielectric constant k is about 12), while coordinate the HfO for possessing high-k2,ZrO2, La2O3,Y2O3, and the ternary or diversification and thing being obtained by mixing by above-mentioned four kinds of materials, help to realize smaller Oxide thickness of equal value.
Brief description of the drawings
Fig. 1 is the structure diagram of the composite gate dielectric layer provided by the invention applied to iii-v substrate；
Fig. 2 is the process flow chart of the composite gate dielectric layer shown in making Fig. 1 provided by the invention；
Fig. 3 is the method flow diagram of the composite gate dielectric layer shown in making Fig. 1 provided by the invention.
Embodiment
For the object, technical solutions and advantages of the present invention are more clearly understood, below in conjunction with specific embodiment, and reference Attached drawing, the present invention is described in more detail.
As shown in Figure 1, Fig. 1 is the structural representation of the composite gate dielectric layer provided by the invention applied to iii-v substrate Figure, the composite gate dielectric layer include：The Al being formed on iii-v substrate 1xY2-xO3Interface passivation layer 23；And it is formed at The AlxY2-xO3High dielectric insulation layer 24 on interface passivation layer 23；Wherein 1.2≤x≤1.9, AlxY2-xO3Interface passivation layer 23 and HfO2High dielectric insulation layer 24 forms composite gate dielectric layer 2.
In Fig. 1, the iii-v substrate 1 can be GaAs substrates, InP substrate, GaSb substrates, InAs substrates or InGaAs substrates and its epitaxial wafer, its doping concentration are more than or equal to 1 × 1015cm-3And less than or equal to 5 × 1017cm-3。AlxY2-xO3 The thickness of interface passivation layer 23 is more than or equal to 0.4nm and is less than or equal to 4nm.High dielectric insulation layer 24 can be HfO2、ZrO2、 La2O3Or Y2O3, and the ternary or multi-element compounds being obtained by mixing by above-mentioned four kinds of materials, the high dielectric insulation The thickness of layer 24 is more than or equal to 0nm and is less than or equal to 4nm.
Fig. 2 is the process flow chart of the composite gate dielectric layer shown in making Fig. 1 provided by the invention, as can be seen from FIG. 2, shape Into the Al on iii-v substrate 1xY2-xO3Interface passivation layer 23 is handled, made by situ heat treatment, i.e. in-situ annealing Al2OmPassivation layer 21 and Y2On22 counterdiffusion of strengthening layer obtains.
By AlxY2-xO3Interface passivation layer 23 and HfO2The gate dielectric layer that high dielectric insulation layer 24 forms is that a composite grid is situated between Matter layer, to reduce interface state density and bound trap density, increases MOS channel mobilities, reduces gate leak current, and further carry The voltage endurance capability of high dielectric layer, improves the q＆r of MOS.
Fig. 3 is the method flow diagram of the composite gate dielectric layer shown in making Fig. 1 provided by the invention, and this method includes following Step：
Step 1：Iii-v substrate is cleaned, grows Al in the iii-v substrate2OmPassivation layer, wherein 2.5≤m≤ 3；
In this step, Al is grown in iii-v substrate2OmPassivation layer, including：Using the method for atomic layer deposition, In iii-v substrate growth thickness it is d under the conditions of 200 DEG C -400 DEG C1The Al of nanometer2OmPassivation layer, wherein 0.2nm≤ d1≤3.8nm.This method adjusts Al by adjusting 200 DEG C of -400 DEG C of atomic layer deposition temperature2OmThe content of oxygen in passivation layer, Wherein 200 DEG C of Al for tending to form low oxygen content2OmPassivation layer, m=2.5；400 DEG C of Al for tending to form elevated oxygen level2Om Passivation layer, m=3；Al2OmRelatively low oxygen content in passivation layer, it is possible to increase Al2OmAl-O tetrahedral grids structure in passivation layer Flexibility, increase Al2OmThe rotatable characteristic of Al-O tetrahedrons in passivation layer, so as to fulfill for iii-v substrate surface defect Passivation；Al2OmHigher oxygen content in passivation layer, can reduce the electric leakage of composite gate dielectric layer and lift reliability.
Step 2：In the Al2OmY is grown on passivation layer2OnStrengthening layer, wherein 2.5≤n≤3；
In this step, in Al2OmY is grown on passivation layer2OnStrengthening layer, including：Using the method for atomic layer deposition, In Al under the conditions of 200 DEG C -400 DEG C2OmGrowth thickness is d on passivation layer2The Y of nanometer2OnStrengthening layer, wherein 0.4nm≤d1+ d2≤4nm.This method adjusts Y by adjusting 200 DEG C of -400 DEG C of atomic layer deposition temperature2OnThe content of oxygen in strengthening layer, wherein 200 DEG C of Y for tending to form low oxygen content2OnStrengthening layer, n=2.5；400 DEG C of Y for tending to form elevated oxygen level2OnStrengthen Layer, n=3.
Step 3：To Al2OmPassivation layer and Y2OnStrengthening layer carries out situ heat treatment, realizes Al2OmPassivation layer and Y2OnStrengthen The mixing of layer, obtains AlxY2-xO3Interface passivation layer, wherein 1.2≤x≤1.9；
In this step, to Al2OmPassivation layer and Y2OnStrengthening layer carries out situ heat treatment, is by Al2OmPassivation layer and Y2OnBy force Change layer and carry out in-situ annealing processing in atomic layer deposition apparatus under the conditions of 200 DEG C -400 DEG C.This method is in situ by adjusting The temperature of heat treatment realizes Al2OmPassivation layer and Y2OnThe mixing of strengthening layer according to a certain percentage, mixing ratio is by Al2OmPassivation layer Thickness d1With Y2OnStrengthening layer thickness d2Ratio d1:d2Determine, wherein 19:1≤d1:d2≤1:19；This method passes through Al2OmPassivation Layer and Y2OnStrengthening layer is mixed to get AlxY2-xO3Interface passivation layer, realizes AlxY2-xO3The average coordination number of interface passivation layer 2.8 to 4.2 regulation and control, and then meet the needs of various devices are to interface defect density and reliability, wherein, average coordination number 2.8 be in d1:d2Between 19:1st, obtained under conditions of m=3 and n=3；Average coordination number 4.2 is in d1:d2Between 1:19、m Obtained under conditions of=2.5 and n=2.5.AlxY2-xO31.2≤x≤1.9 are as interface passivation layer in interface passivation layer It is more excellent as a result, the AlxY2-xO3The average coordination number of interface passivation layer is between 3.28 to 2.86, average coordination number during wherein x=1.2 For 3.28, x=1.9 when average coordination number be 2.86.
Step 4：In the AlxY2-xO3High dielectric insulation layer is grown on interface passivation layer.
In this step, in AlxY2-xO3High dielectric insulation layer is grown on interface passivation layer, is the side using atomic layer deposition Method, in Al under the conditions of 200 DEG C -400 DEG CxY2-xO3Deposition thickness is more than or equal to 0nm and less than or equal to 4nm's on interface passivation layer High dielectric insulation layer.
Embodiment 1
The method that the composite gate dielectric layer applied to iii-v substrate is made according to the embodiment of the present invention 1, including following step Suddenly：
Step 101：Be 400 microns by thickness, n-type doping concentration be 5 × 1015cm-3InP substrate carry out cleaning treatment, Then the method for utilizing atomic layer deposition, growth thickness is 0.5 nanometer of Al under the conditions of 200 DEG C2O2.5Layer；The step 101 has Body includes：
Step 101.1：InP substrate surface is totally submerged in absolute ethyl alcohol upward, is cleaned by ultrasonic 3 minutes, removes table There is the organic matter of partial polarization in face；
Step 101.2：Taken out after InP substrate by step 101.1 is infiltrated 15 seconds in deionized water；
Step 101.3：InP substrate surface Jing Guo step 101.2 is totally submerged in acetone upward, is cleaned by ultrasonic 3 Minute, the organic matter of removal surface non-polarized；
Step 101.4：Taken out after InP substrate by step 101.3 is infiltrated 15 seconds in deionized water；
Step 101.5：Concentrated hydrochloric acid (mass fraction 37%) and deionized water are taken, with 1：9 volume ratio mixing；Step will be passed through Rapid 101.4 InP substrate surface is totally submerged in the dilute hydrochloric acid solution obtained after mixing and is kept for 1 minute upward；
Step 101.6：Taken out after InP substrate by step 101.5 is infiltrated 15 seconds in deionized water；
Step 101.7：It is 22% sulphur that InP substrate surface Jing Guo step 101.6 is totally submerged into mass fraction upward Change ammonia (NH4)2In S solution, kept for 15 minutes；
Step 101.8：Taken out after InP substrate by step 101.7 is infiltrated 15 seconds in deionized water, use nitrogen rapidly Air-blowing is done；
Step 101.9：InP substrate Jing Guo step 101.8 is put into atomic layer deposition apparatus, utilizes atomic layer deposition Method, using trimethyl aluminium and water as precursors the order of water (be first passed through be passed through after trimethyl aluminium), in 200 DEG C of conditions Lower growth thickness is 0.5 nanometer of Al2O2.5Layer.
Step 102：Using the method for atomic layer deposition, change yttrium using three (butyl cyclopentadiene) and water is used as precursors (be first passed through after three (butyl cyclopentadiene) change yttrium and be passed through the order of water) growth thickness is 0.3 nanometer of Y under the conditions of 300 DEG C2O3 Layer.
Step 103：The Al that will be grown2O2.5Layer and Y2O3Layer carries out under the conditions of 300 DEG C in atomic layer deposition apparatus Situ heat treatment, obtains the Al that thickness is 0.8 nanometer1.25Y0.75O3Interface passivation layer；The step 103 specifically includes：
Step 103.1：After step 102 is completed, the nitrogen of purity 99.999% is passed through into atomic layer deposition room, is protected It is 50 Pascals to hold air pressure, starts timing after gas pressure intensity is stablized.
Step 103.2：In-situ annealing processing is carried out under the conditions of 300 DEG C of temperature, keeps the temperature 30 minutes, sends out Al and Y atoms Raw diffusion, forms the Al that the average coordination number that thickness is 0.8 nanometer is 3.251.25Y0.75O3Interface passivation layer.
Step 104：Utilize the method for atomic layer deposition, Al after the annealing process1.25Y0.75O3With double on interface passivation layer (penta diyl of ethyl ring) hafnium dichloride and water (are passed through as precursors after being first passed through double (penta diyl of ethyl ring) hafnium dichlorides The order of water) growth thickness is 3 nanometers of HfO under the conditions of 300 DEG C2Layer.
Embodiment 2
The method that the composite gate dielectric layer applied to iii-v substrate is made according to the embodiment of the present invention 2, including following step Suddenly：
Step 201：Be 20 nanometers by epitaxy layer thickness, n-type doping concentration be 1 × 1018cm-3Silicon On Insulator on In0.53Ga0.47As substrates carry out cleaning treatment, and silicon substrate is intrinsic silicon, and thickness of insulating layer is 50 nanometers；Then atomic layer is utilized The method of deposit, growth thickness is 0.3 nanometer of Al under the conditions of 200 DEG C2O2.5Layer；The step 201 specifically includes：
Step 201.1：By In on Silicon On Insulator0.53Ga0.47As substrate surfaces are totally submerged in absolute ethyl alcohol upward, It is cleaned by ultrasonic 3 minutes, removing surface has the organic matter of partial polarization；
Step 201.2：By In on the Silicon On Insulator Jing Guo step 201.10.53Ga0.47As substrates soak in deionized water Profit is taken out after 15 seconds；
Step 201.3：By In on the Silicon On Insulator Jing Guo step 201.20.53Ga0.47As substrate surfaces soak completely upward Submerge in acetone, be cleaned by ultrasonic 3 minutes, remove the organic matter of surface non-polarized；
Step 201.4：By In on the Silicon On Insulator Jing Guo step 201.30.53Ga0.47As substrates soak in deionized water Profit is taken out after 15 seconds；
Step 201.5：Concentrated hydrochloric acid (mass fraction 37%) and deionized water are taken, with 1：4 volume ratio mixing；Step will be passed through In on rapid 201.4 Silicon On Insulator0.53Ga0.47As substrate surfaces are totally submerged the dilute hydrochloric acid solution obtained after mixing upward It is middle to be kept for 1 minute；
Step 201.6：By In on the Silicon On Insulator Jing Guo step 201.50.53Ga0.47As substrates soak in deionized water Profit is taken out after 15 seconds；
Step 201.7：By In on the Silicon On Insulator Jing Guo step 201.60.53Ga0.47As substrate surfaces soak completely upward Mass fraction is submerged for 22% vulcanization ammonia (NH4)2In S solution, kept for 15 minutes；
Step 201.8：By In on the Silicon On Insulator Jing Guo step 201.70.53Ga0.47As substrates soak in deionized water Profit is taken out after 15 seconds, is dried up with nitrogen rapidly；
Step 201.9：By In on the Silicon On Insulator Jing Guo step 201.80.53Ga0.47As substrates are put into atomic layer deposition In equipment, using the method for atomic layer deposition, (it is passed through using trimethyl aluminium and water as precursors after being first passed through trimethyl aluminium The order of water), growth thickness is 0.3 nanometer of Al under the conditions of 200 DEG C2O2.5Layer.
Step 202：Using the method for atomic layer deposition, change yttrium using three (butyl cyclopentadiene) and water is used as precursors (be first passed through after three (butyl cyclopentadiene) change yttrium and be passed through the order of water) growth thickness is 0.3 nanometer of Y under the conditions of 300 DEG C2O3 Layer.
Step 203：The Al that will be grown2O2.5Layer and Y2O3Layer carries out under the conditions of 300 DEG C in atomic layer deposition apparatus Situ heat treatment, obtains the AlYO that thickness is 0.6 nanometer3Interface passivation layer；The step 203 specifically includes：
Step 203.1：After step 202 is completed, the nitrogen of purity 99.999% is passed through into atomic layer deposition room, is protected It is 50 Pascals to hold air pressure, starts timing after gas pressure intensity is stablized.
Step 203.2：In-situ annealing processing is carried out under the conditions of 300 DEG C of temperature, keeps the temperature 30 minutes, sends out Al and Y atoms Raw diffusion, forms the AlYO that the average coordination number that thickness is 0.6 nanometer is 3.43Interface passivation layer.
Step 204：Utilize the method for atomic layer deposition, AlYO after the annealing process3In 300 DEG C of bars on interface passivation layer Growth thickness is 3 nanometers of Hf under part0.9Y0.13O2Layer；The step 204 specifically includes：
Step 204.1：Using the method for atomic layer deposition, after step 203.2, with double (ethyl rings penta under the conditions of 300 DEG C Diyl) hafnium dichloride and water is as precursors the order of water (be first passed through be passed through after double (penta diyl of ethyl ring) hafnium dichlorides) Growth thickness is 1.35 nanometers of HfO2Layer；
Step 204.2：Using the method for atomic layer deposition, after step 204.1, with three (butyl rings penta under the conditions of 300 DEG C Diene) change yttrium and water as the precursors order of water (be first passed through be passed through after three (butyl cyclopentadiene) change yttrium) at 300 DEG C Under the conditions of growth thickness be 0.3 nanometer of Y2O3Layer；
Step 204.3：Using the method for atomic layer deposition, after step 204.2, with double (ethyl rings penta under the conditions of 300 DEG C Diyl) hafnium dichloride and water is as precursors the order of water (be first passed through be passed through after double (penta diyl of ethyl ring) hafnium dichlorides) Growth thickness is 1.35 nanometers of HfO2Layer；
Step 204.4：After step 204.3 is completed, the nitrogen of purity 99.999% is passed through into atomic layer deposition room, Holding air pressure is 50 Pascals, starts timing after gas pressure intensity is stablized.
Step 204.5：In-situ annealing processing is carried out under the conditions of 300 DEG C of temperature, keeps the temperature 30 minutes, sends out Hf and Y atoms Raw diffusion, forms the Hf that thickness is 3 nanometers0.9Y0.13O2High dielectric insulation layer.
Embodiment 3
The method that the composite gate dielectric layer applied to iii-v substrate is made according to the embodiment of the present invention 3, including following step Suddenly：
Step 301：Be 400 microns by thickness, n-type doping concentration be 1 × 1017cm-3GaAs substrates carry out at cleaning Reason, then using the method for atomic layer deposition, growth thickness is 2 nanometers of Al under the conditions of 250 DEG C2O2.7Layer；The step 301 Specifically include：
Step 301.1：GaAs substrate surfaces are totally submerged in absolute ethyl alcohol upward, are cleaned by ultrasonic 3 minutes, remove table There is the organic matter of partial polarization in face；
Step 301.2：Taken out after GaAs substrates by step 301.1 are infiltrated 15 seconds in deionized water；
Step 301.3：GaAs substrate surfaces Jing Guo step 301.2 are totally submerged in acetone upward, are cleaned by ultrasonic 3 Minute, the organic matter of removal surface non-polarized；
Step 301.4：Taken out after GaAs substrates by step 301.3 are infiltrated 15 seconds in deionized water；
Step 301.5：Concentrated hydrochloric acid (mass fraction 37%) and deionized water are taken, with 1：4 volume ratio mixing；Step will be passed through Rapid 101.4 InP substrate surface is totally submerged in the dilute hydrochloric acid solution obtained after mixing and is kept for 1 minute upward；
Step 301.6：Taken out after GaAs substrates by step 301.5 are infiltrated 15 seconds in deionized water；
Step 301.7：It is 22% sulphur that GaAs substrate surfaces Jing Guo step 301.6 are totally submerged into mass fraction upward Change ammonia (NH4)2In S solution, kept for 15 minutes；
Step 301.8：Taken out after GaAs substrates by step 301.7 are infiltrated 15 seconds in deionized water, it is rapid to use Nitrogen dries up；
Step 301.9：GaAs substrates Jing Guo step 301.8 are put into atomic layer deposition apparatus, are formed sediment using atomic layer Long-pending method, using trimethyl aluminium and water as precursors the order of water (be first passed through be passed through after trimethyl aluminium), in 250 DEG C of bars Growth thickness is 2 nanometers of Al under part2O2.7Layer.
Step 302：Using the method for atomic layer deposition, change yttrium using three (butyl cyclopentadiene) and water is used as precursors (be first passed through after three (butyl cyclopentadiene) change yttrium and be passed through the order of water) growth thickness is 0.3 nanometer of Y under the conditions of 300 DEG C2O3 Layer.
Step 303：The Al that will be grown2O2.7Layer and Y2O3Layer carries out under the conditions of 300 DEG C in atomic layer deposition apparatus Situ heat treatment, obtains the Al that thickness is 2.3 nanometers1.74Y0.26O3Interface passivation layer；
Step 303.1：After step 302 is completed, the nitrogen of purity 99.999% is passed through into atomic layer deposition room, is protected It is 50 Pascals to hold air pressure, starts timing after gas pressure intensity is stablized.
Step 303.2：In-situ annealing processing is carried out under the conditions of 300 DEG C of temperature, keeps the temperature 30 minutes, sends out Al and Y atoms Raw diffusion, forms the Al that the average coordination number that thickness is 2.3 nanometers is 2.961.74Y0.26O3Interface passivation layer.
Step 304, the method for atomic layer deposition, Al after the annealing process are utilized1.74Y0.26O3With double on interface passivation layer (penta diyl of ethyl ring) hafnium dichloride and water (are passed through as precursors after being first passed through double (penta diyl of ethyl ring) hafnium dichlorides The order of water) growth thickness is 2 nanometers of HfO under the conditions of 300 DEG C2Layer.
Particular embodiments described above, has carried out the purpose of the present invention, technical solution and beneficial effect further in detail Describe in detail it is bright, it should be understood that the foregoing is merely the present invention specific embodiment, be not intended to limit the invention, it is all Within the spirit and principles in the present invention, any modification, equivalent substitution, improvement and etc. done, should be included in the guarantor of the present invention Within the scope of shield.

Claims (9)

  1. A kind of 1. production method of composite gate dielectric layer applied to iii-v substrate, it is characterised in that including：
    Step 1：Iii-v substrate is cleaned, grows Al in the iii-v substrate2OmPassivation layer, wherein 2.5≤m≤3；
    Step 2：In the Al2OmY is grown on passivation layer2OnStrengthening layer, wherein 2.5≤n≤3；
    Step 3：To Al2OmPassivation layer and Y2OnStrengthening layer carries out situ heat treatment, realizes Al2OmPassivation layer and Y2OnStrengthening layer Mixing, obtains AlxY2-xO3Interface passivation layer, wherein 1.2≤x≤1.9；
    Step 4：In the AlxY2-xO3High dielectric insulation layer is grown on interface passivation layer.
  2. 2. according to the method described in claim 1, it is characterized in that, grown described in step 1 in the iii-v substrate Al2OmPassivation layer, including：
    In iii-v substrate growth thickness it is d under the conditions of 200 DEG C -400 DEG C using the method for atomic layer deposition1Nanometer Al2OmPassivation layer, wherein 0.2nm≤d1≤3.8nm。
  3. 3. according to the method described in claim 2, it is characterized in that, this method is by adjusting 200 DEG C of -400 DEG C of atomic layer depositions Temperature adjusts Al2OmThe content of oxygen in passivation layer, wherein 200 DEG C of Al for tending to form low oxygen content2OmPassivation layer, m= 2.5；400 DEG C of Al for tending to form elevated oxygen level2OmPassivation layer, m=3；Al2OmRelatively low oxygen content, Neng Gouti in passivation layer High Al2OmThe flexibility of Al-O tetrahedral grids structure in passivation layer, increases Al2OmThe rotatable spy of Al-O tetrahedrons in passivation layer Property, so as to fulfill the passivation for iii-v substrate surface defect；Al2OmHigher oxygen content in passivation layer, can reduce multiple Close the electric leakage of gate dielectric layer and lift reliability.
  4. 4. according to the method described in claim 2, it is characterized in that, in the Al described in step 22OmY is grown on passivation layer2On Strengthening layer, including：
    Using the method for atomic layer deposition, in Al under the conditions of 200 DEG C -400 DEG C2OmGrowth thickness is d on passivation layer2Nanometer Y2OnStrengthening layer, wherein 0.4nm≤d1+d2≤4nm。
  5. 5. according to the method described in claim 4, it is characterized in that, this method is by adjusting 200 DEG C of -400 DEG C of atomic layer depositions Temperature adjusts Y2OnThe content of oxygen in strengthening layer, wherein 200 DEG C of Y for tending to form low oxygen content2OnStrengthening layer, n=2.5； 400 DEG C of Y for tending to form elevated oxygen level2OnStrengthening layer, n=3.
  6. 6. according to the method described in claim 4, it is characterized in that, to Al described in step 32OmPassivation layer and Y2OnStrengthening layer into Row situ heat treatment, is by Al2OmPassivation layer and Y2OnStrengthening layer is under the conditions of 200 DEG C -400 DEG C in atomic layer deposition apparatus Carry out in-situ annealing processing.
  7. 7. according to the method described in claim 6, it is characterized in that,
    This method realizes Al by adjusting the temperature of situ heat treatment2OmPassivation layer and Y2OnStrengthening layer according to a certain percentage mixed Close, mixing ratio is by Al2OmPassivation layer thickness d1With Y2OnStrengthening layer thickness d2Ratio d1:d2Determine, wherein 19:1≤d1:d2≤1: 19；
    This method passes through Al2OmPassivation layer and Y2OnStrengthening layer is mixed to get AlxY2-xO3Interface passivation layer, realizes AlxY2-xO3Boundary The regulation and control of the average coordination number 2.8 to 4.2 of face passivation layer, and then meet various devices to interface defect density and reliability Demand, wherein, average coordination number 2.8 is in d1:d2Equal to 19:1st, obtained under conditions of m=3 and n=3；Average coordination number 4.2 be in d1:d2Equal to 1:19th, obtained under conditions of m=2.5 and n=2.5.
  8. 8. the method according to the description of claim 7 is characterized in that AlxY2-xO31.2≤x≤1.9 are in interface passivation layer As the more excellent of interface passivation layer as a result, the AlxY2-xO3The average coordination number of interface passivation layer is between 3.28 to 2.86, wherein x Average coordination number is 2.86 when average coordination number is 3.28, x=1.9 when=1.2.
  9. 9. according to the method described in claim 1, it is characterized in that, in the Al described in step 4xY2-xO3It is raw on interface passivation layer Grow tall dielectric insulation layer, is the method using atomic layer deposition, in Al under the conditions of 200 DEG C -400 DEG CxY2-xO3Interface passivation layer Upper deposition thickness is more than 0nm and the high dielectric insulation layer less than or equal to 4nm.
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