CN104319290A - Three-grid graphene fin type field effect transistor and manufacturing method thereof - Google Patents
Three-grid graphene fin type field effect transistor and manufacturing method thereof Download PDFInfo
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- CN104319290A CN104319290A CN201410593448.9A CN201410593448A CN104319290A CN 104319290 A CN104319290 A CN 104319290A CN 201410593448 A CN201410593448 A CN 201410593448A CN 104319290 A CN104319290 A CN 104319290A
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- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 title claims abstract description 63
- 229910021389 graphene Inorganic materials 0.000 title claims abstract description 62
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 26
- 238000002353 field-effect transistor method Methods 0.000 title 1
- 239000000758 substrate Substances 0.000 claims abstract description 32
- 230000005669 field effect Effects 0.000 claims abstract description 27
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 9
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 9
- 239000010703 silicon Substances 0.000 claims abstract description 7
- 239000010410 layer Substances 0.000 claims description 116
- 238000000034 method Methods 0.000 claims description 34
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 20
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 16
- 239000000463 material Substances 0.000 claims description 15
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 14
- 238000005468 ion implantation Methods 0.000 claims description 13
- 239000000377 silicon dioxide Substances 0.000 claims description 10
- 235000012239 silicon dioxide Nutrition 0.000 claims description 8
- 238000000137 annealing Methods 0.000 claims description 7
- 230000008021 deposition Effects 0.000 claims description 7
- VNWKTOKETHGBQD-UHFFFAOYSA-N methane Chemical compound C VNWKTOKETHGBQD-UHFFFAOYSA-N 0.000 claims description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 5
- 229920005591 polysilicon Polymers 0.000 claims description 5
- -1 carbon ion Chemical class 0.000 claims description 4
- 238000007687 exposure technique Methods 0.000 claims description 4
- 239000002356 single layer Substances 0.000 claims description 4
- 229910052799 carbon Inorganic materials 0.000 claims description 3
- 239000007769 metal material Substances 0.000 claims description 3
- 229910052732 germanium Inorganic materials 0.000 claims description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 2
- 238000002347 injection Methods 0.000 claims description 2
- 239000007924 injection Substances 0.000 claims description 2
- 239000004065 semiconductor Substances 0.000 description 14
- 239000003292 glue Substances 0.000 description 5
- 230000003287 optical effect Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 239000013078 crystal Substances 0.000 description 3
- 230000007797 corrosion Effects 0.000 description 2
- 238000005260 corrosion Methods 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 125000004429 atom Chemical group 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 210000000746 body region Anatomy 0.000 description 1
- 125000004432 carbon atom Chemical group C* 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/7855—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with at least two independent gates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66484—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with multiple gate, at least one gate being an insulated gate
Abstract
The invention discloses a three-grid graphene fin type field effect transistor and a manufacturing method thereof. Graphene layers for covering three surfaces are formed on a grid in the middle of a fin structure on a substrate, grid dielectric layers and grid electrode layers are deposited successively to form a three-grid structure in order to form a 3D device, and therefore, electrical properties of the transistor can be improved. Compared with a single-grid structure and a double-grid structure, the surface area of a silicon wafer occupied by the transistor can be reduced by means of the three-grid structure.
Description
Technical field
The present invention relates to the manufacturing technology field of semiconductor device, particularly relate to a kind of three grid Graphene fin formula field effect transistor and manufacture methods thereof.
Background technology
Along with the development of semiconductor technology, the performance of semiconductor device steadily improves.The performance raising of semiconductor device realizes mainly through the characteristic size constantly reducing semiconductor device, and the characteristic size of semiconductor device narrows down to Nano grade.Semiconductor device is under this characteristic size, and conventional planar makes the method for semiconductor device, and namely the manufacture method of single gate semiconductor device cannot be suitable for, so there is the manufacture method of multiple-grid semiconductor device.Compared with the manufacture method of single gate semiconductor device, multiple-grid semiconductor device has stronger short channel rejection ability, better subthreshold behavior, higher driving force and can bring higher current densities.
At present, fin field effect pipe (FinFET) is widely used as the representative of multiple-grid semiconductor device, and FinFET is divided into double grid FinFET and three gate FinFETs, and double grid FinFET is wherein widely used.
Fig. 1 is the manufacture method flow chart of prior art double grid FinFET, and the manufacturing process cross-sectional view of the prior art double grid FinFET shown in composition graphs 2a ~ Fig. 2 e, is described in detail to manufacture method:
Step 101, the substrate 11 providing silicon semiconductor-on-insulator (SOI, semiconductor on insulator) crystal to be backing material, this substrate 11 is made up of silicon body region 1, buried oxidation layer 2 and monocrystalline silicon 3, as shown in Figure 2 a;
Step 102, on this substrate 11, form the mask 12 with fin structure (i.e. Fin, or title fin structure) pattern, as shown in Figure 2 b; In this step, the mask 12 with fin structure pattern can be silicon nitride layer, forming process is: deposition mask 12 on the substrate 11, after mask 12 applies optical resistance glue layer, develop after adopting the light shield exposure coating optical resistance glue layer with fin structure, optical resistance glue layer forms the optical resistance glue layer of fin structure pattern, then there is the optical resistance glue layer of fin structure pattern for mask, etch mask 12, obtains the mask 12 with fin structure pattern; In this step, nano impression mode also can be adopted to form the mask 12 with fin structure pattern; For having mask 12 three-dimensional structure diagram of fin structure pattern in the circle of Fig. 2 b;
Step 103, there is the mask 12 of fin structure pattern for blocking, the monocrystalline silicon 3 in etched substrate 11, after obtaining fin structure, remove remaining mask 12, as shown in Figure 2 c; It is the three-dimensional structure diagram of fin structure in the circle of Fig. 2 c;
Step 104, ion implantation mode is adopted to carry out highly doped after annealing at the zone line of fin structure, obtain high-doped zone, then adopt corrosion solvent clean fin structure, erode the high-doped zone of zone line, non-doped region is not corroded, as shown in Figure 2 d; At the three-dimensional structure diagram that the circle of Fig. 2 d is the fin structure after zone line doping and corrosion;
Step 105, on remaining fin structure surface successively deposition of gate dielectric layer and polysilicon layer, photoetching and etching technics is then adopted to form grid at the zone line of fin, as shown in Figure 2 e; In this step, the two ends of fin are respectively as source electrode and drain electrode; Be perspective view at the circle of Fig. 2 e;
Step 106, adopt ion implantation mode to adulterate to grid, source electrode and drain electrode, obtain the device layer of FinFET, not shown in the drawings.
Research shows, grapheme material is by mono-layer graphite Structure composing, there is fabulous electric property, especially its carrier mobility will far above common Si material, its calculated value is approximately higher than greatly Si material carrier mobility 1-2 order of magnitude, and therefore Graphene application in the transistor receives much concern.
How being applied to by Graphene in multiple-grid fin formula field effect transistor as channel material, realizing 3D device, to improve the electric property of transistor, is one of those skilled in the art's technical problem urgently to be resolved hurrily.
Summary of the invention
The object of the invention is to make up above-mentioned the deficiencies in the prior art, a kind of three grid Graphene fin formula field effect transistor and manufacture methods thereof are provided, to form 3D device, improve the electric property of transistor, and the silicon chip surface area that transistor takies can be reduced.
For achieving the above object, the invention provides a kind of three grid Graphene fin formula field effect transistors, it comprises: the dielectric layer on substrate, substrate and the fin structure on dielectric layer (i.e. alleged " fin structure " in prior art), described fin structure is cubic shaped and comprises the grid in centre position and the source/drain electrode of end positions, described grid has three surfaces do not contacted with underlying dielectric layers, each described surface covers graphene layer, gate dielectric layer and grid electrode layer successively, to form three grid graphene-structured.
Further, described substrate is Si, SiC or Ge, and described fin structure is Si, SiC or Ge, and described graphene layer is single-layer graphene or multi-layer graphene.
Further, described gate dielectric layer is silicon dioxide or high-k material, and described grid electrode layer is polysilicon or metal material.
Further, described gate dielectric layer is for containing HfO
2high-k material, described grid electrode layer is Ta, TaN or Mo.
The present invention also provides a kind of manufacture method of three grid Graphene fin formula field effect transistors, and it comprises the following steps:
Step S01, provides substrate, and on substrate, form the fin structure layer of dielectric layer and fin structure to be formed successively;
Step S02, graphical described fin structure layer, forms the fin structure of cubic shaped;
Step S03, on three surfaces that described fin structure does not contact with underlying dielectric layers, forms the graphene layer covered;
Step S04, deposition of gate dielectric layer and grid electrode layer successively on described graphene layer;
Step S05, graphical described gate dielectric layer and grid electrode layer, form the gate patterns in fin structure centre position, and remove the Graphene beyond described gate patterns;
Step S06, carries out ion implantation to the two ends of described fin structure, forms source/drain electrode.
Further, described fin structure layer is carborundum, and step S03 comprises by high annealing, the silicon atom of silicon carbide is spread and leaves surface, thus form graphene layer.
Further, described fin structure is silicon or germanium, and step S03 comprises by ion implantation or plasma injection carbonaceous gas, by carbon ion implatation on three surfaces of fin structure, then forms graphene layer by high annealing.
Further, described carbonaceous gas is methane.
Further, step S04 comprises and utilizes gate dielectric layer described in CVD or ALD process deposits, utilizes grid electrode layer described in CVD or PVD process deposits.
Further, step S02 comprises double exposure or the multiple-exposure technique based on abutment wall.
Further, also comprise between step S05 and S06 and form LDD lightly-doped drain zone structure by ion implantation, and form side wall between described gate patterns and fin structure two ends source/drain electrode region to be formed.
Three grid Graphene fin formula field effect transistor and manufacture methods thereof provided by the invention, gate location in the middle of fin structure covers the surperficial graphene layer of formation three, deposition of gate dielectric layer and grid electrode layer successively again, thus form three grid graphene-structured, to form 3D device, can improve the electric property of transistor, and compared to single grid and double-gate structure, three grid structures of the present invention also can reduce the silicon chip surface area that transistor takies.
Accompanying drawing explanation
For can clearer understanding objects, features and advantages of the present invention, below with reference to accompanying drawing, preferred embodiment of the present invention be described in detail, wherein:
Fig. 1 is the manufacture method flow chart of prior art double grid FinFET;
Fig. 2 a-Fig. 2 e is respectively the manufacturing process cross-sectional view of prior art double grid FinFET;
Fig. 3 is the manufacture method flow chart of the present invention three grid Graphene fin formula field effect transistor;
Fig. 4 a-Fig. 4 d is the manufacture process cross-sectional view of the present invention three grid Graphene fin formula field effect transistor;
Fig. 5 is the plan structure schematic diagram of the present invention three grid Graphene fin formula field effect transistor;
Fig. 6 is A-A direction cutaway view in Fig. 5.
Embodiment
Refer to Fig. 5 and Fig. 6, the three grid Graphene fin formula field effect transistors of the present embodiment, it comprises: substrate 21, dielectric layer 22 on substrate 21 and the fin structure 23 on dielectric layer 22, fin structure 23 is cubic shaped and comprises the grid 31 in centre position and the source electrode 32 of end positions and drain 33, Fig. 6 is visible, the cross section of fin structure 23 is rectangle, one bar limit contacts with lower dielectric layer, three surfaces of other three limits and fin structure do not contact with dielectric layer, grid 31 is made to have three surfaces do not contacted with underlying dielectric layers 22, each surface is coated with graphene layer 24 successively, gate dielectric layer 25 and grid electrode layer 26, to form three grid structures.
Wherein, substrate 21 can be Si, SiC or Ge, and fin structure 23 can be Si, SiC or Ge, and graphene layer can be single-layer graphene or multi-layer graphene, and dielectric layer 22 can be SiO
2or SiN etc.; Gate dielectric layer 25 can be silicon dioxide or high-k material, as containing HfO
2high-k material, grid electrode layer can be polysilicon or metal material, as Ta, TaN or Mo.
embodiment of the method 1
Refer to Fig. 3 and consult Fig. 4 a-4e, the manufacture method of the present embodiment three grid Graphene fin formula field effect transistor simultaneously, it comprises the following steps:
Step S01, as shown in fig. 4 a, provides SiC substrate 51, and in SiC substrate 51, form the fin structure layer 531 of silicon dioxide layer 52 and fin structure to be formed successively.Wherein, fin structure layer 531 is SiC material, and its crystal orientation is for being 0001 crystal orientation along substrate surface direction, and thickness can be 10-1000nm.
Step S02, as shown in Figure 4 b, graphical described fin structure layer, form the fin structure 53 of cubic shaped, the width of fin structure 53 can be 5-100nm, and fin structure 53 length can be 20-10000nm (depression angle).Wherein, this step can comprise double exposure or the multiple-exposure technique based on abutment wall.
Step S03, as illustrated in fig. 4 c, on three surfaces that fin structure 53 does not contact with underlying silica layer 52, forms the graphene layer 54 covered.Wherein, this step adopts high annealing, is generally 800-1200 DEG C, makes the Si atoms permeating on fin structure SiC material surface leave surface, retains C atom, and forms graphene layer.
Step S04, as shown in figure 4d, deposition of gate dielectric layer 55 and grid electrode layer 56 successively on graphene layer 54.Wherein, this step passes through CVD or ALD process deposits gate dielectric layer 55, by CVD or PVD process deposits grid electrode layer 56.In the present embodiment, gate dielectric layer 55 is silicon dioxide, and grid electrode layer 56 is polysilicon.
Step S05, graphical gate dielectric layer 55 and grid electrode layer 56, remove the gate dielectric in the middle of fin structure beyond gate location and gate electrode, forms the gate patterns in fin structure centre position, and remove the Graphene beyond gate patterns.
Step S06, carries out ion implantation doping to the two ends of fin structure 53, forms source/drain electrode.
In practical application, also comprise between step S05 and S06 and form LDD lightly-doped drain zone structure by ion implantation, and form the existing techniques such as side wall, to improve transistor arrangement between described gate patterns and fin structure two ends source/drain electrode region to be formed.Wherein, LDD lightly-doped drain zone structure is between grid both sides side wall and source/drain electrode.
Formed three grid Graphene fin formula field effect transistor structures in, using SiC substrate 51 as raceway groove, silicon dioxide layer 52 as gate dielectric, buried regions substrate (SiC substrate 51) as electrode, can be formed together with graphene layer around grid structure.Now, isolation can be realized by formation STI or PN junction in the substrate region between each device.
embodiment of the method 2
The manufacture method of the present embodiment three grid Graphene fin formula field effect transistor, it comprises the following steps:
Step S01, provides Si substrate, and forms the fin structure layer of silicon dioxide layer and fin structure to be formed successively on a si substrate.Wherein, fin structure layer is Si material.
Step S02, graphical described fin structure layer, form the fin structure of cubic shaped, the width of fin structure can be 5-100nm, and fin structure length can be 20-10000nm (depression angle).Wherein, this step can comprise double exposure or the multiple-exposure technique based on abutment wall.
Step S03, on three surfaces that fin structure does not contact with underlying silica layer, forms the graphene layer covered.Wherein, this step injects carbonaceous gas by ion implantation or plasma, by carbon ion implatation on three surfaces of fin structure, then by high annealing, is generally 500-1200 DEG C, by separating out mechanism or flooding mechanism, forms graphene layer.Preferably, this carbonaceous gas is methane etc.
Step S04, deposition of gate dielectric layer and grid electrode layer successively on graphene layer.Wherein, this step passes through CVD or ALD process deposits gate dielectric layer, by CVD or PVD process deposits grid electrode layer.In the present embodiment, gate dielectric layer is for containing HfO
2and the high-k material of the element such as Al, N, grid electrode layer is Ta.
Step S05, graphical gate dielectric layer and grid electrode layer, remove the gate dielectric in the middle of fin structure beyond gate location and gate electrode, forms the gate patterns in fin structure centre position, and remove the Graphene beyond gate patterns.
Step S06, carries out ion implantation doping to the two ends of fin structure, forms source/drain electrode.
In practical application, also comprise between step S05 and S06 and form LDD lightly-doped drain zone structure by ion implantation, and form side wall between described gate patterns and fin structure two ends source/drain electrode region to be formed.
Formed three grid Graphene fin formula field effect transistor structures in, using Si substrate as raceway groove, silicon dioxide layer as gate dielectric, buried regions substrate (Si substrate) as electrode, can be formed together with graphene layer around grid structure.Now, isolation can be realized by formation STI or PN junction in the substrate region between each device.
Claims (10)
1. a grid Graphene fin formula field effect transistor, it is characterized in that, it comprises: the dielectric layer on substrate, substrate and the fin structure on dielectric layer, described fin structure is cubic shaped and comprises the grid in centre position and the source/drain electrode of end positions, described grid has three surfaces do not contacted with underlying dielectric layers, each described surface covers graphene layer, gate dielectric layer and grid electrode layer successively, to form three grid structures.
2. three grid Graphene fin formula field effect transistors according to claim 1, it is characterized in that: described substrate is Si, SiC or Ge, described fin structure is Si, SiC or Ge, and described graphene layer is single-layer graphene or multi-layer graphene.
3. three grid Graphene fin formula field effect transistors according to claim 1, is characterized in that: described gate dielectric layer is silicon dioxide or high-k material, and described grid electrode layer is polysilicon or metal material.
4. three grid Graphene fin formula field effect transistors according to claim 3, is characterized in that: described gate dielectric layer is for containing HfO
2high-k material, described grid electrode layer is Ta, TaN or Mo.
5. a manufacture method for three grid Graphene fin formula field effect transistors, it is characterized in that, it comprises the following steps:
Step S01, provides substrate, and on substrate, form the fin structure layer of dielectric layer and fin structure to be formed successively;
Step S02, graphical described fin structure layer, forms the fin structure of cubic shaped;
Step S03, on three surfaces that described fin structure does not contact with underlying dielectric layers, forms the graphene layer covered;
Step S04, deposition of gate dielectric layer and grid electrode layer successively on described graphene layer;
Step S05, graphical described gate dielectric layer and grid electrode layer, form the gate patterns in fin structure centre position, and remove the Graphene beyond described gate patterns;
Step S06, carries out ion implantation to the two ends of described fin structure, forms source/drain electrode.
6. the manufacture method of three grid Graphene fin formula field effect transistors according to claim 5, it is characterized in that: described fin structure layer is carborundum, step S03 comprises by high annealing, the silicon atom of silicon carbide is spread and leaves surface, thus form graphene layer.
7. the manufacture method of three grid Graphene fin formula field effect transistors according to claim 5, it is characterized in that: described fin structure is silicon or germanium, step S03 comprises by ion implantation or plasma injection carbonaceous gas, by carbon ion implatation on three surfaces of fin structure, then by high annealing to form graphene layer.
8. the manufacture method of three grid Graphene fin formula field effect transistors according to claim 7, is characterized in that: described carbonaceous gas is methane.
9. the manufacture method of three grid Graphene fin formula field effect transistors according to claim 5, is characterized in that, and: step S04 comprises and utilizes gate dielectric layer described in CVD or ALD process deposits, utilizes grid electrode layer described in CVD or PVD process deposits.
10. the manufacture method of three grid Graphene fin formula field effect transistors according to claim 5, is characterized in that: step S02 comprises double exposure or the multiple-exposure technique based on abutment wall; Also comprise between step S05 and S06 and form LDD lightly-doped drain zone structure by ion implantation, and form side wall between described gate patterns and fin structure two ends source/drain electrode region to be formed.
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| CN107564818A (en) * | 2016-07-01 | 2018-01-09 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and its manufacture method |
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| CN107735864A (en) * | 2015-06-08 | 2018-02-23 | 美商新思科技有限公司 | Substrate and the transistor with the 2D material channels on 3D geometric figures |
| US10950736B2 (en) | 2015-06-08 | 2021-03-16 | Synopsys, Inc. | Substrates and transistors with 2D material channels on 3D geometries |
| CN107735864B (en) * | 2015-06-08 | 2021-08-31 | 美商新思科技有限公司 | Substrate and transistor with 2D material channel on 3D geometry |
| CN106935481A (en) * | 2015-12-30 | 2017-07-07 | 中芯国际集成电路制造(上海)有限公司 | The forming method of semiconductor devices |
| CN106935481B (en) * | 2015-12-30 | 2019-12-31 | 中芯国际集成电路制造(上海)有限公司 | Method for forming semiconductor device |
| CN107564818A (en) * | 2016-07-01 | 2018-01-09 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and its manufacture method |
| CN107564818B (en) * | 2016-07-01 | 2020-08-25 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and method for manufacturing the same |
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| CN107256887A (en) * | 2017-06-23 | 2017-10-17 | 上海集成电路研发中心有限公司 | A kind of graphene FinFET transistors and its manufacture method |
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