CN108599756A - A kind of ddr interface circuit of adjust automatically signal dutyfactor - Google Patents
A kind of ddr interface circuit of adjust automatically signal dutyfactor Download PDFInfo
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- CN108599756A CN108599756A CN201810863611.7A CN201810863611A CN108599756A CN 108599756 A CN108599756 A CN 108599756A CN 201810863611 A CN201810863611 A CN 201810863611A CN 108599756 A CN108599756 A CN 108599756A
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- 102000003922 Calcium Channels Human genes 0.000 claims abstract description 19
- 108090000312 Calcium Channels Proteins 0.000 claims abstract description 19
- 238000005070 sampling Methods 0.000 claims abstract description 10
- 238000010586 diagram Methods 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/017509—Interface arrangements
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
- H03K19/018507—Interface arrangements
Abstract
The invention discloses a kind of ddr interface circuits of adjust automatically signal dutyfactor, including clock signal unit, data signal units and data sampling signal unit, the clock signal unit includes DCC modules, the clock signal clk P that the DCC modules send the clock signal unit, CLKN, which is received back, to be come, detect the duty ratio of its forward signal, generate the voltage VDCC by Duty ratio control, voltage VDCC feeds back to the clock signal unit, data signal units and the respective prime control terminal DCC_S of data sampling signal unit, the signal dutyfactor adjustment of deviation is returned.
Description
Technical field
The present invention relates to DDR (Double Data Rate synchronous DRAM) technical fields more particularly to ddr interface electricity
Road.
Background technology
It is higher and higher with the interface circuits operating rate such as DDR, including clock signal (clock), data-signal (DQ),
The challenge that the duty ratio of data sampling signal (DQS) is brought is increasing, and traditional circuit generally uses control line, when naked eyes are found
When signal dutyfactor is inadequate, carried out manually by control line it is certain make up, or even do not adjust simply.
Invention content
The purpose of the present invention is to provide the ddr interface circuits of adjust automatically signal dutyfactor.
Realizing the technical solution of above-mentioned purpose is：
A kind of ddr interface circuit of adjust automatically signal dutyfactor, including clock signal unit, data signal units sum number
According to sampled signal unit,
The clock signal unit includes DCC modules, the clock which sends the clock signal unit
Signal CLKP, CLKN, which are received back, to be come, and is detected the duty ratio of its forward signal, is generated the voltage VDCC by Duty ratio control, voltage
VDCC feeds back to the clock signal unit, data signal units and the respective prime control terminal DCC_ of data sampling signal unit
S。
Preferably, the DCC modules include comparator, the in-phase input end input clock signal CLKP of the comparator, instead
Phase input terminal input clock signal CLKN, output end output voltage VDCC.
Preferably, the prime control terminal DCC_S includes：First PMOS tube, the second PMOS tube, the first NMOS tube and
Two NMOS tubes, wherein
The source electrode of first PMOS tube connects power supply, the source electrode of drain electrode the second PMOS tube of connection, and grid meets voltage VDCC；
Second PMOS tube is connected with the respective grid of the first NMOS tube is used as input terminal, and respective drain electrode is connected as output
End；
The source electrode of drain electrode the first NMOS tube of connection of second NMOS tube, grid connect voltage VDCC, source electrode ground connection.
The beneficial effects of the invention are as follows：The present invention is believed by detecting the duty ratio of clock signal automatically come adjust automatically clock
Number, the duty ratio of data-signal and data sampling signal, avoid time-consuming and laborious manual setting.Also, with temperature voltage
Equal environmental changes are that dynamic adjusts in real time, ensure that all signal dutyfactors are always optimal.
Description of the drawings
Fig. 1 is the circuit structure diagram of the ddr interface circuit of the present invention；
Fig. 2 is the circuit diagram of DCC modules in the present invention；
Fig. 3 is the circuit diagram of prime control terminal DCC_S in the present invention.
Specific implementation mode
The present invention will be further described with reference to the accompanying drawings.
As shown in Figure 1, ddr interface includes clock signal (clock) unit, data-signal (DQ) unit, data sampling letter
Number (DQS) unit etc., such signal are divided into as differential signal, such as：Clock signal, data acquisition signal.Single-ended signal, such as：Number
It is believed that number.The forward signal circuit of differential signal and the circuit of single-ended signal are consistent, the reverse signal circuit of differential signal
From being replicated by single-ended signal circuit, before plus a reverser composition.Circuit is consistent, then because process voltage temperature etc. causes
Duty cycle deviations showed on all signals unanimously.
Using this consistency, in ddr interface circuit of the invention, clock signal unit includes DCC modules, the DCC moulds
Clock signal clk P, CLKN that clock signal unit is sent are received back by block, detect the duty ratio of its forward signal, produce
The raw voltage VDCC by Duty ratio control.Specifically, referring to Fig.2, DCC modules include comparator U, comparator U's is same mutually defeated
Enter to hold input clock signal CLKP, inverting input input clock signal CLKN, output end output voltage VDCC.In Fig. 1, DQSP
For the forward signal of data sampling signal, DQSN is the reverse signal of data sampling signal.
Voltage VDCC feeds back to clock signal unit, data signal units and the respective prime control of data sampling signal unit
End DCC_S processed.Referring particularly to Fig. 3, prime control terminal DCC_S includes：First PMOS tube MP1, the second PMOS tube MP2, first
NMOS tube MN1 and the second NMOS tube MN2.The source electrode of first PMOS tube MP1 connects power supply, the source of the second PMOS tube MP2 of drain electrode connection
Pole, grid meet voltage VDCC.Second PMOS tube MP2 and the first respective grids of NMOS tube MN1, which are connected, is used as input terminal Vin, respectively
From drain electrode be connected be used as output end vo ut.The source electrode of the first NMOS tube MN1 of drain electrode connection of second NMOS tube MN2, grid connect
Voltage VDCC, source electrode ground connection.
When duty ratio is low, voltage VDCC is reduced, then in prime control terminal DCC_S, the first PMOS tube MP1 and the second PMOS tube
MP2 abilities enhance, and the first NMOS tube MN1 and the second NMOS tube MN2 reduced capabilities, duty ratio are got higher therewith.Conversely, voltage VDCC
It increases, duty ratio is lower therewith, to which the adjustment of the signal dutyfactor of deviation is returned in real time.
Above example is used for illustrative purposes only rather than limitation of the present invention, the technology people in relation to technical field
Member, without departing from the spirit and scope of the present invention, can also make various transformation or modification, therefore all equivalent
Technical solution should also belong to scope of the invention, should be limited by each claim.
Claims (3)
1. a kind of ddr interface circuit of adjust automatically signal dutyfactor, including clock signal unit, data signal units and data
Sampled signal unit, which is characterized in that
The clock signal unit includes DCC modules, the clock signal which sends the clock signal unit
CLKP, CLKN, which are received back, to be come, and is detected the duty ratio of its forward signal, is generated voltage VDCC, voltage VDCC by Duty ratio control
Feed back to the clock signal unit, data signal units and the respective prime control terminal DCC_S of data sampling signal unit.
2. the ddr interface circuit of adjust automatically signal dutyfactor according to claim 1, which is characterized in that the DCC moulds
Block includes comparator, the in-phase input end input clock signal CLKP of the comparator, inverting input input clock signal CLKN,
Output end output voltage VDCC.
3. the ddr interface circuit of adjust automatically signal dutyfactor according to claim 1, which is characterized in that before described
Grade control terminal DCC_S include：First PMOS tube, the second PMOS tube, the first NMOS tube and the second NMOS tube, wherein
The source electrode of first PMOS tube connects power supply, the source electrode of drain electrode the second PMOS tube of connection, and grid meets voltage VDCC；
Second PMOS tube is connected with the respective grid of the first NMOS tube is used as input terminal, and respective drain electrode, which is connected, is used as output end；
The source electrode of drain electrode the first NMOS tube of connection of second NMOS tube, grid connect voltage VDCC, source electrode ground connection.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810863611.7A CN108599756A (en) | 2018-08-01 | 2018-08-01 | A kind of ddr interface circuit of adjust automatically signal dutyfactor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810863611.7A CN108599756A (en) | 2018-08-01 | 2018-08-01 | A kind of ddr interface circuit of adjust automatically signal dutyfactor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN108599756A true CN108599756A (en) | 2018-09-28 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810863611.7A Pending CN108599756A (en) | 2018-08-01 | 2018-08-01 | A kind of ddr interface circuit of adjust automatically signal dutyfactor |
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Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6320438B1 (en) * | 2000-08-17 | 2001-11-20 | Pericom Semiconductor Corp. | Duty-cycle correction driver with dual-filter feedback loop |
| US20100219870A1 (en) * | 2009-03-02 | 2010-09-02 | Nec Electronics Corporation | Duty ratio correction circuit and duty ratio correction method |
| CN102638246A (en) * | 2012-04-25 | 2012-08-15 | 上海宏力半导体制造有限公司 | Duty ratio regulating circuit |
| CN102761319A (en) * | 2012-04-27 | 2012-10-31 | 北京时代民芯科技有限公司 | Clock circuit capable of realizing stable duty ratio and phase calibration |
| CN103856186A (en) * | 2012-12-05 | 2014-06-11 | 艾尔瓦特集成电路科技（天津）有限公司 | Duty ratio regulating circuit and regulating method |
| CN104980126A (en) * | 2014-04-01 | 2015-10-14 | 中兴通讯股份有限公司 | Clock duty ratio adjusting circuit and multiphase clock generator |
| CN208424339U (en) * | 2018-08-01 | 2019-01-22 | 灿芯半导体(上海)有限公司 | A kind of ddr interface circuit of adjust automatically signal dutyfactor |
-
2018
- 2018-08-01 CN CN201810863611.7A patent/CN108599756A/en active Pending
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6320438B1 (en) * | 2000-08-17 | 2001-11-20 | Pericom Semiconductor Corp. | Duty-cycle correction driver with dual-filter feedback loop |
| US20100219870A1 (en) * | 2009-03-02 | 2010-09-02 | Nec Electronics Corporation | Duty ratio correction circuit and duty ratio correction method |
| CN101826860A (en) * | 2009-03-02 | 2010-09-08 | 恩益禧电子股份有限公司 | Duty-cycle correction circuit and duty ratio correction method |
| CN102638246A (en) * | 2012-04-25 | 2012-08-15 | 上海宏力半导体制造有限公司 | Duty ratio regulating circuit |
| CN102761319A (en) * | 2012-04-27 | 2012-10-31 | 北京时代民芯科技有限公司 | Clock circuit capable of realizing stable duty ratio and phase calibration |
| CN103856186A (en) * | 2012-12-05 | 2014-06-11 | 艾尔瓦特集成电路科技（天津）有限公司 | Duty ratio regulating circuit and regulating method |
| CN104980126A (en) * | 2014-04-01 | 2015-10-14 | 中兴通讯股份有限公司 | Clock duty ratio adjusting circuit and multiphase clock generator |
| CN208424339U (en) * | 2018-08-01 | 2019-01-22 | 灿芯半导体(上海)有限公司 | A kind of ddr interface circuit of adjust automatically signal dutyfactor |
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Address after: 6th floor, building 2, Lide international, 1158 Zhangdong Road, Pudong New Area pilot Free Trade Zone, Shanghai, 201203 Applicant after: Canxin semiconductor (Shanghai) Co.,Ltd. Address before: 6th floor, building 2, Lide international, 1158 Zhangdong Road, Pudong New Area pilot Free Trade Zone, Shanghai, 201203 Applicant before: BRITE SEMICONDUCTOR (SHANGHAI) Corp. |
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