CN108599739A - A kind of integrating circuit based on non-overlapping clock charge transfer technology - Google Patents
A kind of integrating circuit based on non-overlapping clock charge transfer technology Download PDFInfo
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- CN108599739A CN108599739A CN201810796818.7A CN201810796818A CN108599739A CN 108599739 A CN108599739 A CN 108599739A CN 201810796818 A CN201810796818 A CN 201810796818A CN 108599739 A CN108599739 A CN 108599739A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/01—Details
- H03K3/012—Modifications of generator to improve response time or to decrease power consumption
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
- H03K19/00346—Modifications for eliminating interference or parasitic voltages or currents
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Abstract
The invention discloses the integrating circuit based on non-overlapping clock charge transfer technology, the left side is switched-capacitor integrator, its effect is in non-overlapping clock control signal s1, under the control of s2, charge and discharge are carried out to point Vramp, the right is non-overlapping clock generation circuit, and effect is to generate non-overlapping clock control signal s1, s2.For comparing traditional quadrature device, there is the present invention response quickly, the high advantage of accuracy can be applied to integrator response and the higher occasion of required precision.On the other hand, amplifier A2 structures of the present invention increase phase margin using with miller-compensated dual-stage amplifier by introducing negative zero.Under 500KHz sensor output frequencies, typical DC gain is about 80dB, GBW 25MHz, and maximum output current absorbability is 25mA, and the power supply rejection ratio (PSRR) when 1KHz is more than 90dB.For entire reference frequency output, it is ensured that 70dB DC current gains and 100 degree of phase margins.
Description
Technical field
The present invention relates to circuit design fields, are especially a kind of integral electricity based on non-overlapping clock charge transfer technology
Road.
Background technology
Conventional operational amplifiers integrating circuit is made of amplifier, capacitance, resistance, by controlling the value of capacitance and resistance,
The time constant of the charge and discharge of integrator can be controlled, and then controls charge and discharge process.Currently, there is many structures, function
Different integrating circuit.
It is found by retrieval, the disclosure of the invention of patent No. CN201080027821.4 one kind has a photodiode (PD)
And integrating circuit；Integrating circuit includes amplifying circuit, capacity cell (C2) and the 2nd switch (SW2).Amplifying circuit has by PMOS
The driving portion that transistor (T1) and NMOS transistor (T2) respective drain terminal are interconnected together.By PMOS transistor
(T10) constitute the 1st switch (SW1), corresponding to the 1st reset signal (Reset1) for being input to gate terminal level and into
Row on-off action.When 1st reset signal (Reset1) is low level, the 1st switch (SW1) becomes closed state, to PMOS crystal
The gate terminal for managing (T1) applies power supply potential (VDD), and PMOS transistor (T1) is thus made to become closed state.It as a result, can be real
The amplifying circuit, integrating circuit and optical detection device of power reducing and high speed can now be taken into account.
A kind of integrator of the disclosure of the invention of patent No. CN201110194074.X and its switch capacitance integrator circuit.At this
In invention, by using sampling module within a clock cycle according to clock pulse signal to positive terminal voltage signal and negative terminal electricity
Pressure signal is sampled, and output plus terminal voltage sampling signal and negative terminal voltage sampled signal and integration module are to anode electricity
It presses sampled signal and negative terminal voltage sampled signal to carry out integral operation, realizes and complete voltage twice within a clock cycle and adopt
Sample and twice voltage integrating meter operation improve integral operation speed and efficiency.
A kind of integrating circuit of high-frequency dust removing power supply resonance current of the disclosure of the invention of patent No. CN201410034108.2,
Including current detection circuit, absolute value circuit, optical coupling isolation circuit, negative circuit, integrating circuit, limit filtration circuit and integral
Switching circuit, wherein current detection circuit, absolute value circuit, optical coupling isolation circuit, negative circuit and integrating circuit are sequentially connected,
Limit filtration circuit and integral restrictor circuit are connected with integrating circuit.
However traditional operational amplifier integral, the precision reached to charging/discharging voltage is not high, and when electric discharge may
There is the insufficient situation of charge bleed off, therefore, it is difficult to meet some response quicklies, the high application scenario of accuracy.
Invention content
Therefore, in order to solve above-mentioned deficiency, the present invention provides a kind of based on non-overlapping clock charge transfer technology herein
Integrating circuit；Integrating circuit of the present invention, mainly for conventional operational amplifiers integrating circuit charging/discharging voltage precision
Not high, charge bleed off is insufficient when electric discharge, it is difficult to accomplish high-precision, propose the shortcomings that high speed.
The invention is realized in this way a kind of integrating circuit based on non-overlapping clock charge transfer technology of construction, special
Sign is：
The integrating circuit includes the switched-capacitor integrator on the left side and the non-overlapping clock generation circuit two parts on the right；
Wherein, its effect of the switched-capacitor integrator on the left side be in non-overlapping clock control signal s1, it is right under the control of s2
Point Vramp carries out charge and discharge, and the right is non-overlapping clock generation circuit, and effect is to generate non-overlapping clock control signal s1,
s2。
As an improvement of the above technical solution, the integrating circuit based on non-overlapping clock charge transfer technology, it is special
Sign is：Wherein, switched-capacitor integrator has switch s1, s2, amplifier A2, capacitance Ci, capacitance Cd；
When s1 is 1, i.e. s1 is closed, and when s2 0, i.e. s2 are opened, integrating circuit is in charged state, and the ends iph are to electricity at this time
Hold Ci to charge, due to the clamping action of amplifier A2, capacitance Ci left ends keep 0.3V, capacitance Ci right ends to charge to 0.6V,
And the quantity of electric charge of capacitance Cd accumulation is (0-Vref1) Cd, the total charge dosage of capacitance Ci and Cd accumulation is 0.3 (Ci-Cd), capacitance
Ci right ends charge to non-overlapping clock s1 after 0.6V, and s2 reversals become s1 openings, and s2 is closed, and capacitance Cd is introduced at this time
The quantity of electric charge be 0.3Cd, since the voltage of capacitance Ci left ends remains unchanged 0.3V, the voltage of capacitance Ci right ends becomes at this time
0.6(1-Cd/Ci)；
If the capacitance ratio for controlling capacitance Cd and Ci is 1：2, then the voltage after capacitance Ci electric discharges will be exactly equal to
0.3V, but since this process is controlled by non-overlapping clock s1, s2, entire discharge process response is rapid, and the electricity after electric discharge
Pressure is only related with the ratio of Cd and Ci, can accomplish to accurately control.
As an improvement of the above technical solution, the integrating circuit based on non-overlapping clock charge transfer technology, it is special
Sign is：Amplifier A2 is used by metal-oxide-semiconductor Mi1、Mi2、Mi3、Mi4、Mi5、Mi6、Mi7、Mi8、Mi9、 Mi10、Mi11、Mi12The band of formation
Miller-compensated dual-stage amplifier；Increase phase margin by introducing negative zero.
The invention has the advantages that：The present invention is based on the integrating circuit overall structures of non-overlapping clock charge transfer technology
As shown in Figure 1, the left side is switched-capacitor integrator, effect be in non-overlapping clock control signal s1, it is right under the control of s2
Point Vramp carries out charge and discharge, and the right is non-overlapping clock generation circuit, and effect is to generate non-overlapping clock control signal s1,
s2.For comparing traditional quadrature device, there is the present invention response quickly, the high advantage of accuracy can be applied to ring integrator
It should be with the higher occasion of required precision.On the other hand, amplifier A2 structures of the present invention, put using with miller-compensated two-stage
Big device increases phase margin by introducing negative zero.Under 500KHz sensor output frequencies, typical DC gain is about
80dB, GBW 25MHz, maximum output current absorbability are 25mA, and the power supply rejection ratio (PSRR) when 1KHz is more than 90dB.
For entire reference frequency output, it is ensured that 70dB DC current gains and 100 degree of phase margins.
Description of the drawings
Fig. 1 is the integrating circuit based on non-overlapping clock charge transfer technology；
Fig. 2 is with miller-compensated dual-stage amplifier schematic diagram.
Specific implementation mode
Below in conjunction with attached drawing 1- Fig. 2, the present invention is described in detail, technical solution in the embodiment of the present invention into
Row clearly and completely describes, it is clear that described embodiments are only a part of the embodiments of the present invention, rather than whole realities
Apply example.Based on the embodiments of the present invention, those of ordinary skill in the art are obtained without making creative work
Every other embodiment, shall fall within the protection scope of the present invention.
The present invention provides a kind of integrating circuit based on non-overlapping clock charge transfer technology, main needle herein by improving
Not high to conventional operational amplifiers integrating circuit charging/discharging voltage precision, charge bleed off is insufficient when electric discharge, it is difficult to accomplish height
The shortcomings that precision, high speed and propose.As Figure 1-Figure 2, it can be practiced as follows；
The integrating circuit includes the switched-capacitor integrator on the left side and the non-overlapping clock generation circuit two parts on the right；
Wherein, its effect of the switched-capacitor integrator on the left side is in non-overlapping clock control signal s1, under the control of s2, to point Vramp
Charge and discharge are carried out, the right is non-overlapping clock generation circuit, and effect is to generate non-overlapping clock control signal s1, s2.
As shown in Figure 1, wherein switched-capacitor integrator has switch s1, s2, amplifier A2, capacitance Ci, capacitance Cd；
When s1 is 1, i.e. s1 is closed, and when s2 0, i.e. s2 are opened, integrating circuit is in charged state, and the ends iph are to electricity at this time
Hold Ci to charge, due to the clamping action of amplifier A2, capacitance Ci left ends keep 0.3V, capacitance Ci right ends to charge to 0.6V,
And the quantity of electric charge of capacitance Cd accumulation is (0-Vref1) Cd, the total charge dosage of capacitance Ci and Cd accumulation is 0.3 (Ci-Cd), capacitance
Ci right ends charge to non-overlapping clock s1 after 0.6V, and s2 reversals become s1 openings, and s2 is closed, and capacitance Cd is introduced at this time
The quantity of electric charge be 0.3Cd, since the voltage of capacitance Ci left ends remains unchanged 0.3V, the voltage of capacitance Ci right ends becomes at this time
0.6(1-Cd/Ci)；
If the capacitance ratio for controlling capacitance Cd and Ci is 1：2, then the voltage after capacitance Ci electric discharges will be exactly equal to
0.3V, but since this process is controlled by non-overlapping clock s1, s2, entire discharge process response is rapid, and the electricity after electric discharge
Pressure is only related with the ratio of Cd and Ci, can accomplish to accurately control.
As shown in Figure 2；Amplifier A2 is used by metal-oxide-semiconductor Mi1、Mi2、Mi3、Mi4、Mi5、Mi6、Mi7、Mi8、 Mi9、Mi10、Mi11、
Mi12The miller-compensated dual-stage amplifier of the band of formation；Increase phase margin by introducing negative zero.
So pass through after above description it is found that the present invention is based on the integrating circuit of non-overlapping clock charge transfer technology is whole
For body structure as shown in Figure 1, the left side is switched-capacitor integrator, effect is in non-overlapping clock control signal s1, the control of s2
Under, charge and discharge are carried out to point Vramp, the right is non-overlapping clock generation circuit, and effect is to generate non-overlapping clock control letter
Number s1, s2.When s1 is 1 (s1 closures), and s2 is 0 (s2 openings), integrating circuit is in charged state, and iph is to capacitance Ci at this time
It charges, due to the clamping action of amplifier A2, Ci left ends keep 0.3V, and Ci right ends charge to 0.6V, and the electricity of Cd accumulation
Lotus amount is that the total charge dosage of (0-Vref1) Cd, Ci and Cd accumulation is 0.3 (Ci-Cd), and Ci right ends charge to non-overlapping after 0.6V
Clock s1, s2 reversal, becomes s1 openings, and s2 is closed.The quantity of electric charge introduced Cd is 0.3Cd at this time, due to Ci left ends
Voltage remains unchanged 0.3V, and the voltage of Ci right ends becomes 0.6 (1-Cd/Ci) at this time, if the capacitance ratio of control Cd and Ci is
1：2, then the voltage after Ci electric discharges will be exactly equal to 0.3V, and since this process is controlled by non-overlapping clock s1, s2, it is whole
A discharge process response is rapid, and the voltage after electric discharge is only related with the ratio of Cd and Ci, can accomplish to accurately control.Fig. 2
Increase phase margin by introducing negative zero using with miller-compensated dual-stage amplifier for amplifier A2 structures.
Under 500KHz sensor output frequencies, typical DC gain is about 80dB, GBW 25MHz, and maximum output current absorbability is
Power supply rejection ratio (PSRR) when 25mA, 1KHz is more than 90dB.For entire reference frequency output, it is ensured that 70dB direct currents increase
Benefit and 100 degree of phase margins.
The foregoing description of the disclosed embodiments enables those skilled in the art to implement or use the present invention.
Various modifications to these embodiments will be apparent to those skilled in the art, as defined herein
General Principle can be realized in other embodiments without departing from the spirit or scope of the present invention.Therefore, of the invention
It is not intended to be limited to the embodiments shown herein, and is to fit to and the principles and novel features disclosed herein phase one
The widest range caused.
Claims (3)
1. a kind of integrating circuit based on non-overlapping clock charge transfer technology, it is characterised in that：
The integrating circuit includes the switched-capacitor integrator on the left side and the non-overlapping clock generation circuit two parts on the right；
Wherein, its effect of the switched-capacitor integrator on the left side is in non-overlapping clock control signal s1, under the control of s2, to point
Vramp carries out charge and discharge, and the right is non-overlapping clock generation circuit, and effect is to generate non-overlapping clock control signal s1, s2.
2. the integrating circuit according to claim 1 based on non-overlapping clock charge transfer technology, it is characterised in that：Wherein,
Switched-capacitor integrator has switch s1, s2, amplifier A2, capacitance Ci, capacitance Cd；
When s1 is 1, i.e. s1 is closed, and when s2 0, i.e. s2 are opened, integrating circuit is in charged state, and the ends iph are to capacitance Ci at this time
It charges, due to the clamping action of amplifier A2, capacitance Ci left ends keep 0.3V, capacitance Ci right ends to charge to 0.6V, and electric
The quantity of electric charge for holding Cd accumulation is (0-Vref1) Cd, and the total charge dosage of capacitance Ci and Cd accumulation is 0.3 (Ci-Cd), capacitance Ci right ends
Non-overlapping clock s1 after 0.6V is charged to, s2 reversals become s1 openings, and s2 is closed, at this time charge introduced capacitance Cd
Amount is 0.3Cd, and since the voltage of capacitance Ci left ends remains unchanged 0.3V, the voltage of capacitance Ci right ends becomes 0.6 (1-Cd/ at this time
Ci)；
If the capacitance ratio for controlling capacitance Cd and Ci is 1：2, then the voltage after capacitance Ci electric discharges will be exactly equal to 0.3V,
Again since this process is controlled by non-overlapping clock s1, s2, the response of entire discharge process is rapid, and the voltage after discharging only and
The ratio of Cd and Ci is related, can accomplish to accurately control.
3. the integrating circuit according to claim 1 based on non-overlapping clock charge transfer technology, it is characterised in that：Amplifier
A2 is used by metal-oxide-semiconductor Mi1、Mi2、Mi3、Mi4、Mi5、Mi6、Mi7、Mi8、Mi9、Mi10、Mi11、Mi12The miller-compensated two-stage of the band of formation
Amplifier；Increase phase margin by introducing negative zero.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810796818.7A CN108599739A (en) | 2018-07-19 | 2018-07-19 | A kind of integrating circuit based on non-overlapping clock charge transfer technology |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201810796818.7A CN108599739A (en) | 2018-07-19 | 2018-07-19 | A kind of integrating circuit based on non-overlapping clock charge transfer technology |
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| CN108599739A true CN108599739A (en) | 2018-09-28 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109646016A (en) * | 2018-12-25 | 2019-04-19 | 重庆湃芯入微科技有限公司 | A kind of low-power consumption integrating circuit adjusted based on current automatic adaptation |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1576861A (en) * | 2003-07-22 | 2005-02-09 | 维加·格里沙伯股份公司 | Method and circuit arrangement for evaluating a capacitor |
| CN102025265A (en) * | 2010-11-16 | 2011-04-20 | 灿芯半导体(上海)有限公司 | Frequency jittering circuit |
| CN105099426A (en) * | 2014-05-05 | 2015-11-25 | 盛群半导体股份有限公司 | Capacitive touch control sensing circuit |
| CN106663202A (en) * | 2016-10-27 | 2017-05-10 | 深圳市汇顶科技股份有限公司 | Capacitive fingerprint sensor |
| CN106796259A (en) * | 2016-11-08 | 2017-05-31 | 深圳市汇顶科技股份有限公司 | Capacitive detection circuit and its control method |
-
2018
- 2018-07-19 CN CN201810796818.7A patent/CN108599739A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1576861A (en) * | 2003-07-22 | 2005-02-09 | 维加·格里沙伯股份公司 | Method and circuit arrangement for evaluating a capacitor |
| CN102025265A (en) * | 2010-11-16 | 2011-04-20 | 灿芯半导体(上海)有限公司 | Frequency jittering circuit |
| CN105099426A (en) * | 2014-05-05 | 2015-11-25 | 盛群半导体股份有限公司 | Capacitive touch control sensing circuit |
| CN106663202A (en) * | 2016-10-27 | 2017-05-10 | 深圳市汇顶科技股份有限公司 | Capacitive fingerprint sensor |
| CN106796259A (en) * | 2016-11-08 | 2017-05-31 | 深圳市汇顶科技股份有限公司 | Capacitive detection circuit and its control method |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109646016A (en) * | 2018-12-25 | 2019-04-19 | 重庆湃芯入微科技有限公司 | A kind of low-power consumption integrating circuit adjusted based on current automatic adaptation |
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Application publication date: 20180928 |