CN108597462A - A kind of gate driving circuit and electronic equipment - Google Patents
A kind of gate driving circuit and electronic equipment Download PDFInfo
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- CN108597462A CN108597462A CN201810011845.9A CN201810011845A CN108597462A CN 108597462 A CN108597462 A CN 108597462A CN 201810011845 A CN201810011845 A CN 201810011845A CN 108597462 A CN108597462 A CN 108597462A
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- 239000004973 liquid crystal related substance Substances 0.000 claims abstract description 49
- 239000010409 thin film Substances 0.000 claims description 78
- 238000007599 discharging Methods 0.000 claims description 53
- 230000001960 triggered effect Effects 0.000 claims description 15
- 230000000694 effects Effects 0.000 abstract description 5
- 230000009467 reduction Effects 0.000 description 17
- 238000012986 modification Methods 0.000 description 4
- 230000004048 modification Effects 0.000 description 4
- 230000000750 progressive effect Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0224—Details of interlacing
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Abstract
The invention discloses a kind of gate driving circuit and electronic equipments, gate driving circuit includes control module, odd-numbered line drive module and even number line drive module, wherein, control module is connect with odd-numbered line drive module, to control the odd number horizontal-drive signal that odd-numbered line drive module generates the odd-line pixels for driving liquid crystal display area；Control module is connect with even number line drive module, to control the even number horizontal-drive signal that even number line drive module generates the even rows for driving liquid crystal display area；Wherein, odd-numbered line drive module and even number line drive module alternately produce odd number horizontal-drive signal and even number horizontal-drive signal under the control of odd-numbered line gating signal and even number line gating signal respectively.Grid electrode drive circuit structure is simple, and can carry out interlacing scan to liquid crystal display area pixel, improves the refresh rate of liquid crystal display, improves display efficiency, and improves the display effect of liquid crystal display panel.
Description
Technical Field
The present invention relates to the field of display control of electronic devices, and in particular, to a gate driving circuit and an electronic device.
Background
Currently, LCD display panels (liquid crystal display panels of liquid crystal displays) driven by GOAs (Gate Driver on Array) are all scanned line by line, and the line by line scanning is to turn on line scanning signals of the displays in sequence and provide data line by line. Although progressive scanning makes the image quality of liquid crystal display good, progressive scanning picture refresh frequency is slow. The current LCD displays PPI higher and higher, and the refresh frequency is hard to be increased due to the limitation of pixel charging time, so that it is more difficult to realize high refresh frequency by line-by-line scanning. In addition, when the liquid crystal display scans line by line, when an RG color mixed picture is displayed, the odd-even lines have different brightness due to the inconsistent charging states of the odd-even lines, and bright and dark stripes are visible during display, resulting in poor display effect.
Disclosure of Invention
Embodiments of the present invention provide a gate driving circuit and an electronic device, where the gate driving circuit can perform interlaced scanning on pixels in a liquid crystal display region, thereby improving a refresh rate of a liquid crystal display and improving image quality.
In order to solve the technical problem, the embodiment of the invention adopts the following technical scheme: a gate driving circuit comprises a control module, an odd row driving module and an even row driving module,
the control module is connected with the odd row driving module to control the odd row driving module to generate odd row driving signals for driving odd row pixels of the liquid crystal display area;
the control module is connected with the even-numbered line driving module to control the even-numbered line driving module to generate even-numbered line driving signals for driving even-numbered line pixels of the liquid crystal display area; wherein,
the odd row driving module and the even row driving module alternately generate the odd row driving signal and the even row driving signal under the control of an odd row strobe signal and an even row strobe signal respectively.
Preferably, the odd-numbered row driving module has an odd-numbered driving end for generating the odd-numbered row driving signal, and the control module includes an odd-numbered row discharging branch, which is connected to the odd-numbered driving end to discharge the odd-numbered driving end, so as to eliminate the odd-numbered row driving signal;
the control module comprises an even-numbered line discharging branch circuit, and the even-numbered line discharging branch circuit is connected with the even-numbered driving end to discharge the even-numbered driving end so as to eliminate the even-numbered line driving signal.
Preferably, the odd-numbered row driving module comprises an odd-numbered row input end and an odd-numbered row thin film transistor, wherein the odd-numbered row input end is used for inputting the odd-numbered row strobe signal, the odd-numbered row input end is connected with the drain electrode of the odd-numbered row thin film transistor, and the source electrode of the odd-numbered row thin film transistor is connected with the odd-numbered driving end;
the even-numbered row driving module comprises an even-numbered row input end and an even-numbered row thin film transistor, the even-numbered row input end is used for inputting the even-numbered row strobe signal, the even-numbered row input end is connected with the drain electrode of the even-numbered row thin film transistor, and the source electrode of the even-numbered row thin film transistor is connected with the even-numbered driving end.
Preferably, the control module has a first control end, and the first control end is connected to the odd row driving module and is used for driving the odd row driving module to generate the odd row driving signal; and is
The first control end is connected with the even row driving module to drive the even row driving module to generate the even row driving signal.
Preferably, the control module includes a control input terminal and a control thin film transistor, a gate and a drain of the control thin film transistor are both connected to the control input terminal, and a source of the control thin film transistor is connected to the first control terminal.
Preferably, the control module has a second control end, and the second control end is connected to the odd-numbered row discharging branch circuit to control the odd-numbered row discharging branch circuit to perform discharging operation on the odd-numbered driving end;
the second control end is connected with the even-numbered row discharging branch circuit and used for controlling the even-numbered row discharging branch circuit to discharge the even-numbered driving end.
Preferably, the odd-numbered row discharging branch circuit comprises an odd-numbered row discharging thin film transistor, and a gate of the odd-numbered row discharging thin film transistor is connected with the second control terminal, so that the second control terminal controls the odd-numbered row discharging thin film transistor to perform discharging operation on the odd-numbered driving terminal;
the even-row discharging branch circuit comprises an even-row discharging thin film transistor, and the grid electrode of the even-row discharging thin film transistor is connected with the second control end, so that the second control end controls the even-row discharging thin film transistor to discharge the even-row driving end.
Preferably, the gate driving circuit further comprises a trigger reset module, and the trigger reset module is connected to the control module to generate a trigger reset signal under the control of the control module, so as to trigger the second pixel row in the display area pixels to be turned on and reset the first pixel row in the display area pixels.
Preferably, the trigger reset module has a trigger reset end to generate the trigger reset signal, the control module includes a trigger reset discharge branch corresponding to the trigger reset module, the trigger reset discharge branch is connected to the trigger reset end, and the trigger reset discharge branch performs a discharge operation on the trigger reset end under the control of the control module.
The embodiment of the invention also provides a liquid crystal display which comprises the gate drive circuit.
The embodiment of the invention has the beneficial effects that: the grid driving circuit is simple in structure, interlaced scanning can be carried out on pixels in the liquid crystal display area, the refresh rate of the liquid crystal display is improved, the display efficiency is improved, and the phenomenon of color-mixed pictures appearing in progressive scanning is avoided.
Drawings
Fig. 1 is a schematic structural diagram of a gate driving circuit according to an embodiment of the invention;
fig. 2 is a structural diagram of an embodiment of a gate driving circuit according to the embodiment of the invention.
Description of the reference numerals
1-control module 2-odd row driving module 3-odd row pixel
4-even row driving module 5-even row pixels
Detailed Description
Various aspects and features of the present invention are described herein with reference to the drawings.
It will be understood that various modifications may be made to the embodiments of the invention herein. Accordingly, the foregoing description should not be construed as limiting, but merely as exemplifications of embodiments. Other modifications will occur to those skilled in the art which are within the scope and spirit of the invention.
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and, together with a general description of the invention given above, and the detailed description of the embodiments given below, serve to explain the principles of the invention.
These and other characteristics of the invention will become apparent from the following description of a preferred form of embodiment, given as a non-limiting example, with reference to the accompanying drawings.
It should also be understood that, although the invention has been described with reference to some specific examples, a person of skill in the art shall certainly be able to achieve many other equivalent forms of the invention, having the characteristics as set forth in the claims and hence all coming within the field of protection defined thereby.
The above and other aspects, features and advantages of the present invention will become more apparent in view of the following detailed description when taken in conjunction with the accompanying drawings.
Specific embodiments of the present invention are described hereinafter with reference to the accompanying drawings; however, it is to be understood that the disclosed embodiments are merely exemplary of the invention, which can be embodied in various forms. Well-known and/or repeated functions and constructions are not described in detail to avoid obscuring the invention in unnecessary or unnecessary detail. Therefore, specific structural and functional details disclosed herein are not to be interpreted as limiting, but merely as a basis for the claims and as a representative basis for teaching one skilled in the art to variously employ the present invention in virtually any appropriately detailed structure.
The specification may use the phrases "in one embodiment," "in another embodiment," "in yet another embodiment," or "in other embodiments," which may each refer to one or more of the same or different embodiments in accordance with the invention.
The gate driving circuit of the embodiment of the invention is applied to the display process of the liquid crystal panel, can control the scanning mode of the liquid crystal panel aiming at the pixel points, and particularly can control the liquid crystal panel to carry out interlaced scanning. As shown in fig. 1, the gate driving circuit includes a control module 1, an odd row driving module 2 and an even row driving module 4, wherein,
the control module 1 is connected to the odd row driving module 2 to control the odd row driving module 2 to generate odd row driving signals for driving the odd row pixels 3 of the liquid crystal display region. The control module 1 comprises a plurality of electronic components with different functions and can generate control signals to the odd row driving module 2, and the odd row driving module 2 can also be a combination of the plurality of electronic components. In one embodiment, the control module 1 has at least one odd row control terminal capable of sending an odd row strobe signal to control the odd row driving module 2 to generate an odd row driving signal capable of driving the odd row pixels 3 of the liquid crystal display region to display without displaying the even row pixels 5 at the same time. For example, the odd row driving signal may drive the odd row pixels 3 in the liquid crystal panel to display with a high level as a driving command, and when the odd row driving signal stops outputting the high level, the display of one or more rows of the odd row pixels 3 is completed.
The control module 1 is connected to the even row driving module 4 to control the even row driving module 4 to generate even row driving signals for driving the even row pixels 5 of the liquid crystal display region. Like the odd row driver module 2, the even row driver module 4 may also be a combination of various electronic components. In one embodiment, the control module 1 has at least one even row control terminal capable of sending an even row strobe signal to control the even row driving module 4 to generate an even row driving signal capable of driving the even row pixels 5 of the liquid crystal display region to display without displaying the odd row pixels 3, and the even row control terminal may be the same as the odd row control terminal or different from the odd row control terminal, so as to be configured independently in form. Similarly, the even-numbered row driving signal may drive the even-numbered row pixels 5 in the liquid crystal panel to display with a high level as a driving command, and when the even-numbered row driving signal stops outputting the high level, the display of the even-numbered row pixels 5 of one or more rows is completed.
The odd row driving module 2 and the even row driving module 4 alternately generate odd row driving signals and even row driving signals under the control of the odd row strobe signals and the even row strobe signals, respectively. The odd row driving signals and the even row driving signals are not generated simultaneously but generated alternately, so that the gate driving circuit can enable the liquid crystal display panel to display only odd rows or only even rows within a certain time period, the display efficiency of the liquid crystal display is improved, and the refreshing frequency is improved. In one embodiment, the liquid crystal display panel is set to have a higher resolution, so that when the liquid crystal display panel displays only odd-numbered lines or even-numbered lines, the image quality of the displayed image is not affected in the sense of the user. Meanwhile, the display efficiency is improved, and a color mixing picture phenomenon caused by line-by-line scanning cannot be generated (namely, in the line-by-line scanning process, when an RG color mixing picture is displayed, due to the fact that charging states of odd lines and even lines are inconsistent, brightness difference of odd and even lines can be caused, bright and dark stripes can be seen during display, and the display effect is poor), and the display effect of the liquid crystal display panel is improved.
In an embodiment of the present invention, referring to fig. 2, the odd row driving module 2 has an odd driving end for generating an odd row driving signal, and the control module 1 includes an odd row discharging branch, and the odd row discharging branch is connected to the odd driving end to discharge the odd driving end, so as to eliminate the odd row driving signal. In one embodiment, the ODD driving terminals (e.g., OUT _ ODD in one embodiment) have the capability of driving the ODD-numbered rows of pixels 3 of the lcd panel to display when not being discharged, and if the ODD-numbered rows of pixels 3 to be driven are completely displayed, the ODD driving terminals OUT _ ODD can be discharged to eliminate the ODD-numbered rows of driving signals and prepare for the EVEN-numbered rows of driving terminals (e.g., OUT _ EVEN in one embodiment) to activate. The ODD driving terminals OUT _ ODD are connected, and the ODD driving terminals OUT _ ODD can be subjected to a discharging operation by grounding the ODD driving terminals or the like.
The even-numbered row driving module 4 has an even-numbered driving terminal for generating an even-numbered row driving signal, and the control module 1 includes an even-numbered row discharging branch connected to the even-numbered driving terminal to discharge the even-numbered driving terminal, thereby eliminating the even-numbered row driving signal. Similar to the odd-numbered row driving module 2, in one embodiment, the EVEN-numbered driving terminal OUT _ EVEN has the capability of driving the EVEN-numbered row pixels 5 of the liquid crystal display panel to display when not being discharged, and if the driven EVEN-numbered row pixels 5 are completely displayed, the EVEN-numbered driving terminal OUT _ EVEN can be subjected to discharge processing, so that the EVEN-numbered row driving signal is eliminated and preparation is made for starting the odd-numbered row driving terminal. When all the even-numbered rows of pixels 5 are displayed, the whole picture of the liquid crystal display panel is displayed. Similar to the odd-numbered row discharging branch, the EVEN-numbered row discharging branch (e.g., including M11B, M12B, and M4B) of the control module 1 may also be formed by various types of electronic components, and is connected to the EVEN-numbered driving terminal OUT _ EVEN, so that the EVEN-numbered driving terminal OUT _ EVEN may be discharged by grounding the EVEN-numbered driving terminal OUT _ EVEN, and the like, so as to eliminate the EVEN-numbered row driving signal.
In an embodiment of the present invention, in conjunction with fig. 2, the ODD row driving module 2 includes an ODD row input terminal (for example, SCAN _ ODD in an embodiment) for inputting the ODD row strobe signal, and an ODD row thin film transistor (for example, M3A in an embodiment), the ODD row input terminal SCAN _ ODD is connected to the drain of the ODD row thin film transistor M3A, and the source of the ODD row thin film transistor is connected to the ODD driving terminal. The thin film transistor has a function of a switch, in an embodiment, the ODD-numbered row of thin film transistors has a gate G, a source S and a drain D, and the control module 1 may operate the ODD-numbered row of thin film transistors M3A by operating the gate of the ODD-numbered row of thin film transistor M3A, so as to control the drain and the source of the ODD-numbered row of thin film transistors M3A to be conductive, and further, enable the ODD-numbered row input terminal SCAN _ ODD to output a signal thereof to the ODD-numbered driving terminal OUT _ ODD, so that the ODD-numbered driving terminal OUT _ ODD drives the ODD-numbered row of pixels 3 of the liquid crystal display panel to display.
The EVEN row driving module 4 includes EVEN row input terminals (such as SCAN _ EVEN in one embodiment and an EVEN row thin film transistor (such as M3B in one embodiment) for inputting EVEN row strobe signals, the EVEN row input terminal SCAN _ EVEN is connected to the drain of the EVEN row thin film transistor M3B, the source of the EVEN row thin film transistor is connected to the EVEN driving terminal, similarly to the odd row driving module 2, the EVEN row thin film transistor also has a gate G, a source S and a drain D, the control module 1 can operate the EVEN row thin film transistor M3B itself by operating the gate of the EVEN row thin film transistor M3B, thereby controlling the drain and source of the EVEN-numbered row thin film transistor M3B to be conducted, further, enabling the EVEN-numbered row input terminal SCAN _ EVEN to output its signal to the EVEN-numbered driving terminal OUT _ EVEN, so that the EVEN driving end OUT _ EVEN drives the EVEN row pixels 5 of the liquid crystal display panel to display.
In one embodiment of the present invention, referring to fig. 2, the control module 1 has a first control terminal (e.g. PU in one embodiment, the first control terminal PU is connected to the odd row driving module 2 for driving the odd row driving module 2 to generate the odd row driving signal, and the first control terminal PU is connected to the even row driving module 4 for driving the even row driving module 4 to generate the even row driving signal, the control module 1 can send out a control signal through the first control terminal, e.g. form the control signal by driving the variation of the voltage of the first control terminal, and further drive the odd row driving module 2 to generate the odd row driving signal, for example, the first control terminal PU is connected to the gate of the odd row thin film transistor (e.g. M3A in the embodiment) in the odd row driving module 2, and can turn on the drain and source of the odd row thin film transistor M3A when the first control terminal PU is at a high level, so that the odd row driving module 2 is driven to generate odd row driving signals. Similarly, the first control terminal PU is connected to the gate of the even-row thin film transistor (e.g., M3B in the specific embodiment) in the even-row driving module 4, and when the first control terminal PU is at a high level, the drain and the source of the even-row thin film transistor M3B can be turned on, so that the even-row driving module 4 is driven to generate the even-row driving signal.
In one embodiment of the present invention, the control module 1 includes a control INPUT terminal (e.g., INPUT in one embodiment and a control thin film transistor (e.g., M1 in one embodiment), the gate and the drain of the control thin film transistor M1 are both connected to the control INPUT terminal INPUT, and the source of the control thin film transistor is connected to the first control terminal PU. the control INPUT terminal INPUT can perform a timing change, for example, the control thin film transistor M1 is turned on when the control INPUT terminal INPUT is high, and the first control terminal PU is charged to high level, so that the first control terminal PU can control the odd row driving module 2 or the even row driving module 4 connected thereto.
In one embodiment of the present invention, in conjunction with fig. 2, the control module 1 has a second control terminal (e.g., PDA and PDB in one embodiment), which is connected to the ODD row discharging branch for controlling the ODD row discharging branch to discharge the ODD driving terminal (e.g., OUT _ ODD in one embodiment). The control module 1 may send a control signal through the second control terminal (PDA and PDB), for example, a control signal is formed by driving the second control terminal (PDA and PDB) to increase the voltage, so as to drive and control the ODD-numbered row discharging branch, so that the ODD-numbered row discharging branch performs a discharging operation on the ODD-numbered driving terminal OUT _ ODD, and the ODD-numbered driving terminal OUT _ ODD stops driving the ODD-numbered row pixels 3 of the liquid crystal panel to display.
The second control terminals PDA and PDB are connected to the EVEN row discharging branch circuit for controlling the EVEN row discharging branch circuit to perform discharging operation on the EVEN driving terminal OUT _ EVEN. Similar to the odd-numbered row discharging branch, the voltage of the second control terminal PDA and the PDB is increased to form a control signal, and then the EVEN-numbered row discharging branch is driven and controlled, so that the EVEN-numbered row discharging branch performs a discharging operation on the EVEN-numbered driving terminal OUT _ EVEN, and the EVEN-numbered driving terminal OUT _ EVEN stops driving the display of the EVEN-numbered row pixels 5 of the liquid crystal panel, or completes the display of one or more rows of the EVEN-numbered row pixels 5.
In an embodiment of the present invention, in conjunction with fig. 2, the gate driving circuit further includes a trigger reset module, and the trigger reset module is connected to the control module 1 to generate a trigger reset signal under the control of the control module 1, so as to trigger the second pixel row in the display area pixels to be turned on and reset the first pixel row in the display area pixels. In one embodiment, the triggered reset module includes reset thin film transistors (e.g., M3C, a reset input CLK, and a triggered reset OUT _ C in one embodiment). The gate of the reset thin film transistor M3C is connected to the first control terminal PU of the control module 1, the drain of the reset thin film transistor M3C is connected to the reset input terminal CLK, the source of the reset thin film transistor M3C is connected to the trigger reset terminal OUT _ C, when the first control terminal PU of the control module 1 is at a high level, the reset thin film transistor M3C is turned on, the reset input terminal CLK is output to the trigger reset terminal OUT _ C, and the trigger reset terminal OUT _ C is used for driving a second pixel row in the display region pixels of the liquid crystal display panel to be turned on, and resetting a first pixel row in the display region pixels, wherein the first pixel row is displayed with the second pixel row first, that is, the first pixel row has the functions of triggering the next row to be turned on and resetting the previous row.
Preferably, with reference to fig. 2, the trigger reset module has a trigger reset terminal OUT _ C to generate a trigger reset signal, the control module 1 includes a trigger reset discharge branch corresponding to the trigger reset module, the trigger reset discharge branch is connected to the trigger reset terminal, and the trigger reset discharge branch performs a discharge operation on the trigger reset terminal OUT _ C under the control of the control module 1. As further described in conjunction with the above embodiments, the triggered reset discharging branch includes a first triggered reset thin film transistor M11C and a second triggered reset thin film transistor M12C, a drain of the first triggered reset thin film transistor M11C is connected to the triggered reset terminal OUT _ C, a drain of the second triggered reset thin film transistor M12C is also connected to the triggered reset terminal OUT _ C, the first control terminal PU of the control module 1 is connected to a gate of the first triggered reset thin film transistor M11C, and when the first control terminal PU is at a high level, the first triggered reset thin film transistor M11C is turned on to discharge (may be connected to the ground line VSS) the triggered reset terminal OUT _ C, thereby stopping the reset operation. The second control terminal PDB of the control module 1 is connected to the gate of the second trigger reset thin film transistor M12C, and when the second control terminal PDB is high, the second trigger reset thin film transistor M12C is turned on, so that the trigger reset terminal OUT _ C is also discharged (and may be connected to the ground line VSS), thereby stopping the reset operation. The first trigger reset thin film transistor M11C and the second trigger reset thin film transistor M12C of the trigger reset discharge branch have the structural structure, so that the output of the display area for driving the liquid crystal display panel is separated from the output responsible for triggering reset, the circuit structure is simpler and easier to realize, and the function of interlaced scanning is realized.
In an embodiment of the present invention, referring to fig. 2, the control module 1 further includes a RESET terminal RESET and at least one RESET thin film transistor, which are used to perform a RESET operation on the gate driving circuit or the control module 1 in the gate driving circuit, for example, to discharge a PU in the control module 1 to perform a RESET operation on the control module 1. In one embodiment, the RESET thin film transistor includes M2, M10A, and M10B, when RESET is high at the RESET terminal, M2 is turned on to discharge to the first control terminal PU; in one embodiment, the PDA in the second control terminal is connected to the gate of M10A, and discharges the first control terminal PU when the PDA in the second control terminal is high; in another embodiment, the PDB in the second control terminal is connected to the gate of M10B, and discharges the first control terminal PU when the PDB in the second control terminal is high. Further, if the RESET terminal RESET is at a high level, the thin film transistor M4A and the thin film transistor M4B are turned on, and the discharging operation is performed to the EVEN driving terminal OUT _ EVEN and the ODD driving terminal OUT _ ODD, thereby stopping the display of the pixels in the liquid crystal panel.
For further example, when odd-numbered lines are scanned, the control INPUT terminal INPUT is a high-level pulse, the control thin film transistor M1 is turned on, the first control terminal PU is charged to a high level, the reset INPUT terminal CLK is output to the trigger reset terminal OUT _ C, and then the next line is triggered to be turned on and the previous line is reset; meanwhile, the ODD drive end OUT _ ODD outputs the same waveform as the first control end PU (the frame of the ODD row input end SCAN _ ODD is high level at the beginning), the last row time of the pulse width of the first control end PU, the ODD row drive signal is output to the liquid crystal panel, and one row of pixels are lightened; when a signal sent by the RESET terminal RESET comes, the first control terminal PU discharges to the VSS low level, the ODD-numbered row thin film transistor M3A is turned off, and the ODD-numbered driving terminal OUT _ ODD stops outputting the high level, thereby completing scanning of one row; at other times of a frame, the first control end PU is low, and the generated noise can be well controlled by the PDA or PDB. In addition, the timing principle of even line scanning is the same as that of odd line scanning, and the description is omitted again.
In one embodiment of the present invention, in conjunction with fig. 2, the gate driving circuit further comprises a noise reduction module, such as a first noise reduction branch and a second noise reduction branch, wherein the first noise reduction branch comprises a first noise reduction input terminal (e.g., VDDA), at least one first noise reduction thin film transistor and corresponding first noise reduction discharge circuit (e.g., M8A and M6A); the second noise reduction branch includes a second noise reduction input (e.g., VDDB), at least one second noise reduction thin film transistor, and corresponding second noise reduction discharge circuits (e.g., M8B and M6B). For example, the first noise reduction thin film transistor includes M9A and M5A, a gate and a drain of M9A are connected to the first noise reduction input terminal VDDA, a source of M9A is connected to a gate of M5A, and M5A is used to pull up the voltage of the second control terminal PDB of the control module 1 to perform noise reduction processing on the first control terminal PU. Similarly, the second noise reduction thin film transistor includes M9B and M5B, the gate and drain of M9B are connected to the second noise reduction input terminal VDDB, the source of M9B is connected to the gate of M5B, and M5B is used to pull up the voltage of the second control terminal PDA of the control module 1 to perform noise reduction processing on the first control terminal PU.
The embodiment of the invention also provides a liquid crystal display which comprises the gate drive circuit. In addition, the liquid crystal display also comprises a liquid crystal display panel and corresponding accessories, and the grid drive circuit can drive pixels in the liquid crystal display panel to alternately display odd lines and even lines. The refresh rate and the display effect of the liquid crystal display are improved. The liquid crystal display can be used as a display device of various electronic devices, such as a display of a desktop computer, a display of a notebook computer, a display of a television and the like.
The above embodiments are only exemplary embodiments of the present invention, and are not intended to limit the present invention, and the scope of the present invention is defined by the claims. Various modifications and equivalents may be made by those skilled in the art within the spirit and scope of the present invention, and such modifications and equivalents should also be considered as falling within the scope of the present invention.
Claims (10)
1. A gate driving circuit, comprising a control module, an odd row driving module and an even row driving module, wherein,
the control module is connected with the odd row driving module to control the odd row driving module to generate odd row driving signals for driving odd row pixels of the liquid crystal display area;
the control module is connected with the even-numbered line driving module to control the even-numbered line driving module to generate even-numbered line driving signals for driving even-numbered line pixels of the liquid crystal display area; wherein,
the odd row driving module and the even row driving module alternately generate the odd row driving signal and the even row driving signal under the control of an odd row strobe signal and an even row strobe signal respectively.
2. The gate drive circuit of claim 1, wherein
The odd-numbered line driving module is provided with an odd-numbered driving end used for generating the odd-numbered line driving signal, the control module comprises an odd-numbered line discharging branch, and the odd-numbered line discharging branch is connected with the odd-numbered driving end to discharge the odd-numbered driving end so as to eliminate the odd-numbered line driving signal;
the control module comprises an even-numbered line discharging branch circuit, and the even-numbered line discharging branch circuit is connected with the even-numbered driving end to discharge the even-numbered driving end so as to eliminate the even-numbered line driving signal.
3. The gate drive circuit of claim 2, wherein
The odd-numbered row driving module comprises an odd-numbered row input end and an odd-numbered row thin film transistor, the odd-numbered row input end is used for inputting the odd-numbered row strobe signal, the odd-numbered row input end is connected with the drain electrode of the odd-numbered row thin film transistor, and the source electrode of the odd-numbered row thin film transistor is connected with the odd-numbered driving end;
the even-numbered row driving module comprises an even-numbered row input end and an even-numbered row thin film transistor, the even-numbered row input end is used for inputting the even-numbered row strobe signal, the even-numbered row input end is connected with the drain electrode of the even-numbered row thin film transistor, and the source electrode of the even-numbered row thin film transistor is connected with the even-numbered driving end.
4. The gate drive circuit of claim 1, wherein
The control module is provided with a first control end, and the first control end is connected with the odd row driving module and is used for driving the odd row driving module to generate the odd row driving signal; and is
The first control end is connected with the even row driving module to drive the even row driving module to generate the even row driving signal.
5. The gate drive circuit of claim 4, wherein
The control module comprises a control input end and a control thin film transistor, the grid electrode and the drain electrode of the control thin film transistor are connected to the control input end, and the source electrode of the control thin film transistor is connected with the first control end.
6. The gate drive circuit of claim 2, wherein
The control module is provided with a second control end, and the second control end is connected with the odd-numbered row discharging branch circuit and is used for controlling the odd-numbered row discharging branch circuit to discharge the odd-numbered driving end;
the second control end is connected with the even-numbered row discharging branch circuit and used for controlling the even-numbered row discharging branch circuit to discharge the even-numbered driving end.
7. The gate drive circuit of claim 6, wherein
The odd-numbered row discharging branch circuit comprises an odd-numbered row discharging thin film transistor, and the grid electrode of the odd-numbered row discharging thin film transistor is connected with the second control end, so that the second control end controls the odd-numbered row discharging thin film transistor to discharge the odd-numbered driving end;
the even-row discharging branch circuit comprises an even-row discharging thin film transistor, and the grid electrode of the even-row discharging thin film transistor is connected with the second control end, so that the second control end controls the even-row discharging thin film transistor to discharge the even-row driving end.
8. The gate driving circuit of claim 1, further comprising a triggered reset module connected to the control module to generate a triggered reset signal under control of the control module to trigger a second row of pixels in the display area pixels to turn on and reset a first row of pixels in the display area pixels.
9. The gate driving circuit according to claim 8, the trigger reset module having a trigger reset terminal to generate the trigger reset signal, the control module comprising a trigger reset discharge branch corresponding to the trigger reset module, the trigger reset discharge branch being connected to the trigger reset terminal, the trigger reset discharge branch performing a discharge operation on the trigger reset terminal under the control of the control module.
10. A liquid crystal display comprising the gate driving circuit as claimed in any one of claims 1 to 9.
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| CN201810011845.9A CN108597462A (en) | 2018-01-05 | 2018-01-05 | A kind of gate driving circuit and electronic equipment |
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| CN201810011845.9A CN108597462A (en) | 2018-01-05 | 2018-01-05 | A kind of gate driving circuit and electronic equipment |
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| CN108597462A true CN108597462A (en) | 2018-09-28 |
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| CN201810011845.9A Pending CN108597462A (en) | 2018-01-05 | 2018-01-05 | A kind of gate driving circuit and electronic equipment |
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