CN108595297B - UPI speed detection method and device - Google Patents
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- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
- G06F11/221—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test buses, lines or interfaces, e.g. stuck-at or open line faults
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- G06F11/00—Error detection; Error correction; Monitoring
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Abstract
The embodiment of the invention discloses a method and a device for detecting a UPI speed, wherein the detection method comprises the following steps: obtaining CPUBUSNO from the UBOX device to obtain a value of CPUBUSNO 3; obtaining a value corresponding to the position 0xD4 from the device PQ _ CSR _ PLLFCR, and respectively judging the working states of UPI bus0, UPI bus1 and UPI bus2 according to the obtained value; if any one of the values of the UPI bus0, UPI bus1 and UPI bus2 is not equal to the nominal value, the test result fails; otherwise, the test passes. The UPI speed detection method and the UPI speed detection device can ensure that the UPI speed reaches a nominal value, thereby improving the test coverage rate and the product quality of a CPU (Central processing Unit) and reducing the material control cost of projects and factories.
Description
Technical Field
The invention relates to the field of computer software development, in particular to a method and a device for detecting a UPI speed.
Background
The upi (ultra Path interconnect) is a connection bus between CPUs with more bandwidth and flexibility, which is proposed by Intel on the new generation server platform Purley, and its transmission rate can reach 10.4GT/s at most. In a multi-CPU system, CPUs communicate with each other via the bus, thereby determining the load distribution and the like of a single CPU. The UPI connection is very important and if its rate is lower than the nominal 9.6GT/s or 10.4GT/s, it will cause the overall server system to operate at a significantly reduced performance. Therefore, we need to check in factory test whether the UPI speed reaches the nominal value to determine if we have errors in PCB layout wiring and part soldering.
Based on the importance of the UPI to the performance of the server, the invention provides a UPI speed detection method and a UPI speed detection device, which are used for ensuring that the UPI speed meets a nominal value.
Disclosure of Invention
The embodiment of the invention provides a method and a device for detecting a UPI speed, which are used for ensuring that the UPI speed reaches a nominal value, thereby improving the test coverage rate of a CPU (Central processing Unit) and the product quality.
In order to solve the technical problem, the embodiment of the invention discloses the following technical scheme:
the invention provides a UPI speed detection method in a first aspect, which comprises the following steps:
obtaining CPUBUSNO from the UBOX device to obtain a value of CPUBUSNO 3;
obtaining a value corresponding to the position 0xD4 from the device PQ _ CSR _ PLLFCR, and respectively judging the working states of UPI bus0, UPI bus1 and UPI bus2 according to the obtained value;
if any one of the values of the UPI bus0, UPI bus1 and UPI bus2 is not equal to the nominal value, the test result fails; otherwise, the test passes.
Based on the scheme, the method is optimized as follows:
further, the step of acquiring a value corresponding to the position 0xD4 from the slave device PQ _ CSR _ PLLFCR, and determining the working states of the UPI bus0, the UPI bus1, and the UPI bus2 according to the acquired value specifically includes:
reading a bus number of PCIe (peripheral component interconnect express) 3, a device number 0x0E and a function number 0x03, reading a 0xD4 position slave PQ _ CSR _ PLLFCR and acquiring a corresponding value thereof, wherein if the acquired value is 0x03, the speed of the UPI bus0 is 9.6GT/s, if the acquired value is 0x04, the speed of the UPI bus0 is 10.4GT/s, and if the acquired value is other values, the UPI bus0 does not work;
reading a bus number of PCIe (peripheral component interconnect express) 3, a device number 0x0F and a function number 0x03, reading a 0xD4 position slave PQ _ CSR _ PLLFCR and acquiring a corresponding value thereof, wherein if the acquired value is 0x03, the speed of the UPI bus1 is 9.6GT/s, if the acquired value is 0x04, the speed of the UPI bus1 is 10.4GT/s, and if the acquired value is other values, the UPI bus1 does not work;
through reading bus number of PCIe (peripheral component interconnect express) 3, device number 0x10 and function number 0x03, reading 0xD4 position slave PQ _ CSR _ PLLFCR and obtaining the corresponding value, if the obtained value is 0x03, the speed of UPI bus2 is 9.6GT/s, if the obtained value is 0x04, the speed of UPI bus2 is 10.4GT/s, and if the obtained value is other values, the UPI bus2 does not work.
As an optimization, before obtaining CPUBUSNO from the UBOX device, the method further comprises the following steps:
the PCIe device acquiring the UPI speed is placed in an un-hidden state, and then the server is restarted.
Further, the specific operation steps of placing the PCIe device that acquires the UPI speed in the non-hidden state include: DFX Feature of Enable BIOS setup menu.
After the test is completed, the DFX feature is set to disable in the BIOS setup menu to place the PCIe device that acquires the UPI speed in a hidden state.
The invention provides a detection device of UPI speed, which comprises a CPUBUSNO obtaining unit, a UPI bus state judging unit and a UPI bus comparison unit:
the CPUBUSNO obtaining unit is used for obtaining CPUBUSNO from a UBOX device to obtain a value of CPUBUSNO 3;
the UPI bus state judgment unit is used for acquiring a value corresponding to the position 0xD4 from the device PQ _ CSR _ PLLFCR and respectively judging the working states of UPI bus0, UPI bus1 and UPI bus2 according to the acquired value;
the UPI bus comparison unit is used for comparing any one of the values of UPI bus0, UPI bus1 and UPI bus2 with a nominal value, if the comparison is inconsistent, the test result fails, otherwise, the test passes.
Furthermore, the detection device further comprises a PCIe state control unit, where the PCIe state control unit is configured to control the PCIe device that acquires the UPI speed to be in a hidden state or a non-hidden state.
In the apparatus for detecting UPI speed, the UPI bus state determining unit specifically includes a UPI bus0 state determining unit, a UPI bus1 state determining unit, and a UPI bus2 state determining unit;
the UPI bus0 state judgment unit reads 0xD4 position slave device PQ _ CSR _ PLLFCR and acquires the corresponding value by reading PCIe bus number ═ CPUBUSNO3, device number ═ 0x0E and function number ═ 0x03, if the acquired value is 0x03, the speed of UPI bus0 is 9.6GT/s, if the acquired value is 0x04, the speed of UPI bus0 is 10.4GT/s, and if the acquired value is other values, the UPI bus0 does not work;
the UPI bus1 state judgment unit reads 0xD4 position slave device PQ _ CSR _ PLLFCR and acquires the corresponding value by reading PCIe bus number ═ CPUBUSNO3, device number ═ 0x0F and function number ═ 0x03, if the acquired value is 0x03, the speed of UPI bus1 is 9.6GT/s, if the acquired value is 0x04, the speed of UPI bus1 is 10.4GT/s, and if the acquired value is other values, the UPI bus1 does not work;
the UPI bus2 status determining unit reads the bus number of PCIe as CPUBUSNO3, the device number as 0x10, and the function number as 0x03, reads the 0xD4 position slave device PQ _ CSR _ PLLFCR and obtains the corresponding value, if the obtained value is 0x03, the speed of the UPI bus2 is 9.6GT/s, if the obtained value is 0x04, the speed of the UPI bus2 is 10.4GT/s, and if the obtained value is other values, the UPI bus2 does not work.
The technical scheme provided by the embodiment of the application has the following beneficial effects:
the UPI speed detection method provided by the embodiment of the application comprises the steps of obtaining CPUBUSNO from UBOX equipment; obtaining a value corresponding to the position 0xD4 from the device PQ _ CSR _ PLLFCR, and respectively judging the working states of UPI bus0, UPI bus1 and UPI bus2 according to the obtained value; if any value of the UPI bus0, the UPI bus1 and the UPI bus2 is not equal to the nominal value, the test result fails; otherwise the test passes. The UPI speed detection method can ensure that the UPI speed reaches a nominal value, so that the test coverage rate and the product quality of a CPU (Central processing Unit) are improved, and the material management and control cost of projects and factories is reduced.
The UPI speed detection apparatus according to the second aspect of the present invention can achieve the same effects as the design method according to the first aspect.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and together with the description, serve to explain the principles of the application.
Fig. 1 is a schematic flow chart of a method for detecting a UPI speed according to an embodiment of the present application;
fig. 2 is a schematic structural diagram of a UPI speed detection apparatus according to an embodiment of the present application.
Reference numerals: the device comprises a 1-CPUBUSNO obtaining unit, a 2-UPI bus state judging unit and a 3-UPI bus comparing unit.
Detailed Description
In order to make those skilled in the art better understand the technical solution of the present invention, the technical solution in the embodiment of the present invention will be clearly and completely described below with reference to the drawings in the embodiment of the present invention, and it is obvious that the described embodiment is only a part of the embodiment of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Fig. 1 is a method for detecting a UPI speed according to an embodiment of the present application, and as can be seen from fig. 1, the method of the present embodiment includes the following steps:
obtaining CPUBUSNO from the UBOX device to obtain a value of CPUBUSNO 3;
obtaining a value corresponding to the position 0xD4 from the device PQ _ CSR _ PLLFCR, and respectively judging the working states of UPI bus0, UPI bus1 and UPI bus2 according to the obtained value;
if any one of the values of the UPI bus0, UPI bus1 and UPI bus2 is not equal to the nominal value, the test result fails; otherwise, the test passes.
Specifically, the specific implementation process of the steps is as follows:
s1, DFX Feature of Enable BIOS setup menu, aiming at hiding the PCIe equipment obtaining UPI speed no longer, then restarting the server, and automatically setting by adopting BIOS setting tool of AMI;
s2, obtaining CPUBUSNO from the UBOX device by reading the 0xcc position of PCIe bus number 0x0, device number 0x08, function number 0x02, thereby obtaining the value of CPUBUSNO 3;
s3, reading PCIe bus number 3, device number 0x0E + upiino, function number 0x03, and 0xD4 position to obtain its corresponding value from device PQ _ CSR _ PLLFCR, if this value is 0x03, the speed of UPI bus0 is 9.6GT/S, if it is 0x04, the speed of UPI bus0 is 10.4GT/S, if it is other value, it indicates that UPI bus0 is inactive;
s4, reading PCIe bus number 3, device number +0x0E (UPI no + 1), function number 0x03, reading 0xD4 position to obtain its corresponding value from device PQ _ CSR _ PLLFCR, if this value is 0x03, the speed of UPI bus1 is 9.6GT/S, if it is 0x04, the speed of UPI bus1 is 10.4GT/S, if it is other value, it is stated that UPI bus1 is inactive;
s5, reading PCIe bus number 3, device number +0x0E (UPI no + 2), function number 0x03, reading 0xD4 position to obtain its corresponding value from device PQ _ CSR _ PLLFCR, if this value is 0x03, the speed of UPI bus2 is 9.6GT/S, if it is 0x04, the speed of UPI bus2 is 10.4GT/S, if it is other value, it is stated that UPI bus2 is inactive;
s6, if any one of the steps S3-S5 has UPI bus non-work or is not equal to the nominal value, the test result fails; otherwise, the test is passed;
and S7, disabling the DFX feature in the BIOS setup menu to hide the PCIe equipment acquiring the UPI speed, and ending the test.
Fig. 2 is a detection apparatus for UPI speed according to an embodiment of the present application, and as can be seen from fig. 2, the detection apparatus of this embodiment includes a CPUBUSNO obtaining unit 1, a UPI bus state determining unit 2, and a UPI bus comparing unit 3:
a CPUBUSNO obtaining unit 1 is used for obtaining CPUBUSNO from a UBOX device to obtain a value of CPUBUSNO 3;
the UPI bus state judgment unit 2 is configured to obtain a value corresponding to the position 0xD4 from the device PQ _ CSR _ PLLFCR, and respectively judge the working states of the UPI bus0, the UPI bus1, and the UPI bus2 according to the obtained value;
the UPI bus comparison unit 3 is configured to compare any one of the values of UPI bus0, UPI bus1, and UPI bus2 with a nominal value, and if the comparison is inconsistent, the test result fails, otherwise, the test passes.
Specifically, the detection apparatus further includes a PCIe state control unit, where the PCIe state control unit is configured to control the PCIe device that acquires the UPI speed to be in a hidden or non-hidden state.
Further, the UPI bus state judgment unit 2 specifically includes a UPI bus0 state judgment unit, a UPI bus1 state judgment unit, and a UPI bus2 state judgment unit;
the UPI bus0 state judgment unit reads 0xD4 position slave device PQ _ CSR _ PLLFCR and acquires the corresponding value by reading PCIe bus number ═ CPUBUSNO3, device number ═ 0x0E and function number ═ 0x03, if the acquired value is 0x03, the speed of UPI bus0 is 9.6GT/s, if the acquired value is 0x04, the speed of UPI bus0 is 10.4GT/s, and if the acquired value is other values, the UPI bus0 does not work;
the UPI bus1 state judgment unit reads 0xD4 position slave device PQ _ CSR _ PLLFCR and acquires the corresponding value by reading PCIe bus number ═ CPUBUSNO3, device number ═ 0x0F and function number ═ 0x03, if the acquired value is 0x03, the speed of UPI bus1 is 9.6GT/s, if the acquired value is 0x04, the speed of UPI bus1 is 10.4GT/s, and if the acquired value is other values, the UPI bus1 does not work;
the UPI bus2 status determining unit reads the bus number of PCIe as CPUBUSNO3, the device number as 0x10, and the function number as 0x03, reads the 0xD4 position slave device PQ _ CSR _ PLLFCR and obtains the corresponding value, if the obtained value is 0x03, the speed of the UPI bus2 is 9.6GT/s, if the obtained value is 0x04, the speed of the UPI bus2 is 10.4GT/s, and if the obtained value is other values, the UPI bus2 does not work.
The foregoing are merely exemplary embodiments of the present invention, which enable those skilled in the art to understand or practice the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (5)
1. A UPI speed detection method is characterized by comprising the following steps:
obtaining CPUBUSNO from the UBOX device to obtain a value of CPUBUSNO 3;
obtaining a value corresponding to the position 0xD4 from the device PQ _ CSR _ PLLFCR, and respectively judging the working states of UPI bus0, UPI bus1 and UPI bus2 according to the obtained value;
the steps of obtaining the value corresponding to the position 0xD4 from the slave device PQ _ CSR _ PLLFCR, and determining the working states of the UPI bus0, the UPI bus1 and the UPI bus2 according to the obtained value are specifically as follows:
reading a bus number of PCIe (peripheral component interconnect express) 3, a device number 0x0E and a function number 0x03, reading a 0xD4 position slave PQ _ CSR _ PLLFCR and acquiring a corresponding value thereof, wherein if the acquired value is 0x03, the speed of the UPI bus0 is 9.6GT/s, if the acquired value is 0x04, the speed of the UPI bus0 is 10.4GT/s, and if the acquired value is other values, the UPI bus0 does not work;
reading a bus number of PCIe (peripheral component interconnect express) 3, a device number 0x0F and a function number 0x03, reading a 0xD4 position slave PQ _ CSR _ PLLFCR and acquiring a corresponding value thereof, wherein if the acquired value is 0x03, the speed of the UPI bus1 is 9.6GT/s, if the acquired value is 0x04, the speed of the UPI bus1 is 10.4GT/s, and if the acquired value is other values, the UPI bus1 does not work;
reading a bus number of PCIe (peripheral component interconnect express) 3, a device number 0x10 and a function number 0x03, reading a 0xD4 position from a device PQ _ CSR _ PLLFCR and acquiring a corresponding value thereof, wherein if the acquired value is 0x03, the speed of the UPI bus2 is 9.6GT/s, if the acquired value is 0x04, the speed of the UPI bus2 is 10.4GT/s, and if the acquired value is other values, the UPI bus2 does not work;
if any one of the values of the UPI bus0, UPI bus1 and UPI bus2 is not equal to the nominal value, the test result fails; otherwise, the test passes.
2. The UPI speed detection method of claim 1, further comprising the steps of, prior to obtaining CPUBUSNO from the UBOX device:
the PCIe device acquiring the UPI speed is placed in an un-hidden state, and then the server is restarted.
3. The method for detecting a UPI speed of claim 2, wherein the step of placing the PCIe device that acquires the UPI speed in the non-hidden state is specifically: DFX Feature of Enable BIOS setup menu.
4. The method of claim 1, wherein after the testing is completed, setting the DFX feature to disable in the BIOS setup menu to place the PCIe device acquiring the UPI speed in a hidden state.
5. An apparatus for detecting UPI speed, comprising:
a CPUBUSNO obtaining unit for obtaining CPUBUSNO from the UBOX apparatus to obtain a value of CPUBUSNO 3;
a UPI bus state judgment unit, configured to obtain a value corresponding to position 0xD4 from the device PQ _ CSR _ PLLFCR, and respectively judge the operating states of UPI bus0, UPI bus1, and UPI bus2 according to the obtained value; the UPI bus comparison unit is used for comparing any one of the values of the UPI bus0, the UPI bus1 and the UPI bus2 with a nominal value, if the comparison is inconsistent, the test result fails, otherwise, the test passes;
the detection device also comprises a PCIe state control unit used for controlling the PCIe equipment for acquiring the UPI speed to be in a hidden or non-hidden state;
the UPI bus state judgment unit specifically comprises a UPI bus0 state judgment unit, a UPI bus1 state judgment unit and a UPI bus2 state judgment unit;
the UPI bus0 state judgment unit reads 0xD4 position slave device PQ _ CSR _ PLLFCR and acquires the corresponding value by reading PCIe bus number ═ CPUBUSNO3, device number ═ 0x0E and function number ═ 0x03, if the acquired value is 0x03, the speed of UPI bus0 is 9.6GT/s, if the acquired value is 0x04, the speed of UPI bus0 is 10.4GT/s, and if the acquired value is other values, the UPI bus0 does not work;
the UPI bus1 state judgment unit reads 0xD4 position slave device PQ _ CSR _ PLLFCR and acquires the corresponding value by reading PCIe bus number ═ CPUBUSNO3, device number ═ 0x0F and function number ═ 0x03, if the acquired value is 0x03, the speed of UPI bus1 is 9.6GT/s, if the acquired value is 0x04, the speed of UPI bus1 is 10.4GT/s, and if the acquired value is other values, the UPI bus1 does not work;
the UPI bus2 status determining unit reads the bus number of PCIe as CPUBUSNO3, the device number as 0x10, and the function number as 0x03, reads the 0xD4 position slave device PQ _ CSR _ PLLFCR and obtains the corresponding value, if the obtained value is 0x03, the speed of the UPI bus2 is 9.6GT/s, if the obtained value is 0x04, the speed of the UPI bus2 is 10.4GT/s, and if the obtained value is other values, the UPI bus2 does not work.
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| CN111124780B (en) * | 2019-11-30 | 2022-10-18 | 苏州浪潮智能科技有限公司 | UPI Link speed reduction test method, system, terminal and storage medium |
| CN115955416B (en) * | 2022-12-20 | 2024-10-22 | 苏州浪潮智能科技有限公司 | Method, device, equipment and storage medium for testing UPI bandwidth reduction |
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