CN110191010B - Pressure testing method of server - Google Patents
Pressure testing method of server Download PDFInfo
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- CN110191010B CN110191010B CN201910290067.6A CN201910290067A CN110191010B CN 110191010 B CN110191010 B CN 110191010B CN 201910290067 A CN201910290067 A CN 201910290067A CN 110191010 B CN110191010 B CN 110191010B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L43/00—Arrangements for monitoring or testing data switching networks
- H04L43/08—Monitoring or testing based on specific metrics, e.g. QoS, energy consumption or environmental parameters
Abstract
The invention provides a pressure test method of a server, which is suitable for the server comprising a super-path interconnection bus and comprises the following steps: respectively configuring internal memories for a plurality of processors in a server; respectively operating a testing thread on two processors which are interconnected by a super path interconnection bus, wherein each testing thread is configured to access a non-local memory through the super path interconnection bus, and the non-local memory is a memory which does not belong to the processor which is currently operating the testing thread; the invention provides a pressure test method of a server, which can flexibly set the time length and the load size of a test thread through an operating system, simulate practical application operation to carry out pressure test of the server, and has wide test coverage and high test efficiency; when the pressure test is carried out, the load of the super path interconnection bus is transferred, the load of the processor and the load of the memory are transferred, and the stability of the server can be synchronously improved in the test process.
Description
Technical Field
The invention relates to the technical field of testing of servers, in particular to a pressure testing method of a server comprising a super-path interconnection bus.
Technical Field
QPI (Quick Path Interconnect) bus technology is a point-to-point connection technology between CPUs (processors) instead of a Front Side Bus (FSB). Intel initiated an UPI (Ultra Path Interconnect) bus technology in 2017 instead of QPI bus technology. The UPI bus technology can improve the speed and ability of a server with a multicore CPU to access a system memory by interconnecting a plurality of CPUs.
With the advent of big data and artificial intelligence era, the demand of the server is increasing, and the stability requirement of the server is also increasing. The server is a product with extremely high reliability requirements, so the investment of the server test in the development process is also quite large.
Currently, most of the coupling tests for the UPI bus in the server stay in a rate test or a pressure test that does not involve OS (Operating System) application, and few of them are performed in the OS by simulating actual application operation. Only the transmission rate of the UPI bus is measured, and the stability cannot be completely ensured; the test is not carried out in the OS by simulating the actual application operation, the difference from the actual situation is large, and the coverage of the pressure test is insufficient.
Disclosure of Invention
The invention aims to provide a pressure test method of a server, which is suitable for pressure test of the server comprising a super-path interconnection bus, and is simple and visual and high in test efficiency.
Therefore, the invention provides a pressure test method of a server, which is suitable for pressure test of the server comprising a hyper-path interconnection bus, and comprises the following steps: respectively configuring internal memories for a plurality of processors in a server; and respectively running a testing thread on two processors which are interconnected by the super path interconnection bus, wherein each testing thread is configured to access a non-local memory through the super path interconnection bus, and the non-local memory is a memory which does not belong to the processor which is currently running the testing thread.
Further, the pressure testing method further comprises the following steps: the method comprises the steps of dividing a plurality of processors in a server into a plurality of stress test groups, wherein each stress test group comprises a first processor and a second processor which are interconnected through a hyper-path interconnection bus.
Further, the pressure testing method further comprises the following steps: binding the first processor and the memory allocated to the second processor through a numclt tool, and binding the second processor and the memory allocated to the first processor through the numclt tool; the numclt tool is a NUMA technical mechanism tool for controlling processes and sharing storage.
Further, in the step of running a test thread on each of the two processors, the memory bandwidth is tested by the stream test tool.
Further, the server is configured with an operating system, and the stress testing method further comprises the following steps: the time length and the load size of the testing thread are set through an operating system.
The pressure test method of the server can flexibly set the time length and the load size of the test thread through the operating system, simulate the actual application operation to carry out the pressure test of the server, and has the advantages of wide test coverage, simplicity, intuition and high test efficiency; when the pressure test is carried out, the load of the super path interconnection bus is transferred, the load of the processor and the load of the memory are transferred, and the stability of the server can be synchronously improved in the test process.
Drawings
The present invention will be further described in the following detailed description of preferred embodiments, which is to be read in connection with the accompanying drawings.
FIG. 1 is a schematic diagram of a server architecture for a hyper-path interconnect between two processors, according to an embodiment of the invention.
Detailed Description
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following description will be made with reference to the accompanying drawings. It is obvious that the drawings in the following description are only some examples of the invention, and that for a person skilled in the art, other drawings and embodiments can be derived from them without inventive effort.
For the sake of simplicity, the drawings only schematically show the parts relevant to the present invention, and they do not represent the actual structure as a product. In addition, in order to make the drawings concise and understandable, components having the same structure or function in some of the drawings are only schematically illustrated or only labeled. In this document, "one" means not only "only one" but also a case of "more than one".
The invention provides a pressure test method of a server, which is suitable for pressure test of the server comprising a super path interconnection bus. The interconnection mode may be pairwise interconnection realized by a mesh hyper-path interconnection bus, or linear interconnection in which each processor is connected with 1 or 2 other processors, or other possible interconnection modes.
The pressure testing method of the server comprises the following steps:
s1: respectively configuring internal memories for a plurality of processors in a server;
s2: dividing a plurality of processors in a server into a plurality of pressure test groups, wherein each pressure test group comprises a first processor and a second processor which are interconnected by a hyper-path interconnection bus;
s3: and respectively running a testing thread on two processors which are interconnected by the hyper-path interconnection bus, wherein each testing thread is configured to access a non-local memory through the hyper-path interconnection bus, and the non-local memory is a memory which does not belong to the processor currently running the testing thread.
The first embodiment is as follows:
a server architecture of a hyper-path interconnect between two processors according to a first embodiment of the present invention is shown in fig. 1, and a stress test method according to the present invention is described in detail below with reference to fig. 1.
The pressure testing method of the server provided by the invention comprises the following steps:
s1: allocating a first memory to a first processor CPU1 and a second memory to a second processor CPU2 by NUMA technology mechanism;
the Non-uniform Memory Access (NUMA) technology mechanism is a Non-uniform Memory Access mechanism, that is, a Memory is configured in a processor node, and a network channel such as a super path interconnection bus is needed for accessing memories of other processors.
S2: the first processor CPU1 and the second processor CPU2 form a stress test group by being interconnected by the hyper-path interconnection bus;
in other embodiments, two processors interconnected by a hyper-path interconnect bus are selected by an operating system in the server as a stress test set, and a plurality of stress test sets are simultaneously subjected to stress test to improve test efficiency.
S3: running a first test thread on the first processor CPU1, the first test thread configured to access a second memory allocated to the second processor CPU2 via a hyper path interconnect bus; a second test thread is run on the second processor CPU2, the second test thread configured to access the first memory allocated to the first processor CPU1 via the hyper path interconnect bus.
Preferably, the method for testing the thread configuration may include: binding a first processor CPU1 and a second memory through a numclt tool, and binding a second processor CPU2 and the first memory through the numclt tool; the numclt tool is a NUMA technical mechanism tool for controlling processes and sharing storage.
In the step of running the test threads on the two processors respectively, the memory bandwidth is tested by the stream test tool.
Preferably, the server is configured with an Operating System (OS), and the time length and the load size of the test thread are set by the OS in the stress test method.
The invention provides a pressure test method of a server, which is suitable for carrying out pressure test on the server comprising a super-path interconnection bus, and is simple and visual and high in test efficiency; the time length and the load of the testing thread can be flexibly set through the operating system, and the pressure test of the server is carried out by simulating the actual application operation. The test coverage is wide; when the pressure test is carried out, the load of the super path interconnection bus is transferred, the load of the processor and the load of the memory are transferred, and the stability of the server can be synchronously improved in the test process.
It should be noted that the server stress test method of the present invention is not only applicable to a server including 2 processors, but also generally applicable to a server including a plurality of processors.
It should be noted that the above embodiments can be freely combined as necessary. The above description is only a preferred embodiment of the present invention, but the present invention is not limited to the details of the above embodiment, and it should be noted that, for those skilled in the art, it is possible to make various modifications and alterations without departing from the principle of the present invention, and it should be understood that these modifications, alterations and equivalents should be regarded as the protection scope of the present invention.
Claims (3)
1. A stress test method of a server, which is suitable for stress testing of the server comprising a hyper-path interconnection bus, and is characterized in that the stress test method comprises the following steps:
respectively configuring internal memories for a plurality of processors in a server;
respectively operating a testing thread on two processors which are interconnected by a super path interconnection bus, wherein each testing thread is configured to access a non-local memory through the super path interconnection bus, and the non-local memory is a memory which does not belong to the processor which is currently operating the testing thread;
wherein the pressure testing method further comprises:
dividing a plurality of processors in a server into a plurality of pressure test groups, wherein each pressure test group comprises a first processor and a second processor which are interconnected by a hyper-path interconnection bus;
wherein the pressure testing method further comprises:
s1: allocating a first memory to a first processor and a second memory to a second processor through a NUMA (non-uniform memory access) technical mechanism;
s2: the first processor and the second processor are interconnected by the hyper-path interconnection bus to form a pressure test group;
s3: running a first test thread on the first processor, the first test thread configured to access a second memory allocated to the second processor through the hyper-path interconnect bus; running a second test thread on a second processor, the second test thread configured to access a first memory allocated to the first processor through a hyper-path interconnect bus;
wherein the pressure testing method further comprises:
s1: allocating a first memory to a first processor and a second memory to a second processor through a NUMA (non-uniform memory access) technical mechanism;
s2: selecting two processors interconnected by a hyper-path interconnection bus as a pressure test group by an operating system in the server;
s3: running a first test thread on the first processor, the first test thread configured to access a second memory allocated to the second processor through the hyper-path interconnect bus; running a second test thread on a second processor, the second test thread configured to access a first memory allocated to the first processor through a hyper-path interconnect bus;
wherein the step of respectively configuring the memories for the plurality of processors in the server comprises:
binding the first processor and the memory allocated to the second processor through a numclt tool, and binding the second processor and the memory allocated to the first processor through the numclt tool; the numclt tool is a NUMA technical mechanism tool for controlling processes and sharing storage.
2. The method for stress testing of a server according to claim 1, wherein in the step of running a test thread on each of the two processors, the memory bandwidth is tested by a stream test tool.
3. The server stress testing method according to claim 1, wherein the server is configured with an operating system, the stress testing method further comprising:
the time length and the load size of the testing thread are set through an operating system.
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| CN112463483A (en) * | 2020-11-23 | 2021-03-09 | 苏州浪潮智能科技有限公司 | UPI pressure testing method, system, terminal and storage medium |
| CN113868045B (en) * | 2021-09-02 | 2023-08-11 | 苏州浪潮智能科技有限公司 | Super-path interconnection link screening and classifying method, device and medium |
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| CN101354667A (en) * | 2007-07-24 | 2009-01-28 | 英业达股份有限公司 | Method for testing peripheral component interconnect bus level pressure |
| CN104484250A (en) * | 2014-11-28 | 2015-04-01 | 英业达科技有限公司 | Pressure testing method and pressure testing device for fast path interconnection bus |
| CN108595297A (en) * | 2018-05-09 | 2018-09-28 | 郑州云海信息技术有限公司 | A kind of detection method and device of UPI speed |
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| CN104239173A (en) * | 2013-06-06 | 2014-12-24 | 鸿富锦精密工业（深圳）有限公司 | Bus testing device and method of CPU (Central Processing Unit) |
| CN104679615A (en) * | 2013-11-26 | 2015-06-03 | 英业达科技有限公司 | Bus pressure test system and method thereof |
| TWI507868B (en) * | 2014-12-15 | 2015-11-11 | Inventec Corp | Pressure test method and device for testing qpi |
| CN107239371A (en) * | 2016-03-29 | 2017-10-10 | 迈普通信技术股份有限公司 | A kind of CPU pressure test devices and method |
| CN109448777A (en) * | 2018-11-12 | 2019-03-08 | 郑州云海信息技术有限公司 | A kind of test method and device of NVME solid state hard disk |
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| CN101354667A (en) * | 2007-07-24 | 2009-01-28 | 英业达股份有限公司 | Method for testing peripheral component interconnect bus level pressure |
| CN104484250A (en) * | 2014-11-28 | 2015-04-01 | 英业达科技有限公司 | Pressure testing method and pressure testing device for fast path interconnection bus |
| CN108595297A (en) * | 2018-05-09 | 2018-09-28 | 郑州云海信息技术有限公司 | A kind of detection method and device of UPI speed |
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