CN108573103A - A kind of the application verification system and its verification method of 4X RapidIO - Google Patents
A kind of the application verification system and its verification method of 4X RapidIO Download PDFInfo
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
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Abstract
A kind of the application verification system and its verification method of 4X RapidIO, including FPGA and 1601P generate 14 pairs of accurate differential clocks by 2 CDCM6208；The 1601P interconnects XC6VSX475T, is configured by the operating mode of 4X to 4 RapidIO Bank of XC6VSX475T；The 1601P and XC6VSX475T is respectively drawn 2 road 4X RapidIO by samtec connectors, and carries out interconnection test by client cables, by client cables try from translocation between samtec connectors.The present invention can not only meet under different working modes the needs of to differential clocks, and disclosure satisfy that 1X/4X compatibilities and mixed verification, additionally it is possible to realize the verification of the interconnecting application between device/plate of RapidIO.
Description
Technical field
The invention belongs to lsi development fields, are related to a kind of the application verification system and its authentication of 4X RapidIO
Method.
Background technology
1601P is 17 core processors of a normality, integrates multiple function moulds such as PPC, network-on-chip, DDR and RapidIO
Block or high-speed communication interface, the 4 road 4X RapidIO high-speed communication interfaces integrated in 1601P can be used with single channel 4X patterns,
Can also single channel 1X patterns use, can also be operated under 1X/4X mixed modes, increase the flexibility of the system integration.
But in proofing chip-coprocessor of early period, design is 4 road 1X, using the 4 road 1X with TMS320C6678
RapidIO is interconnected, and providing reference clock using a piece of CDCE62005 for 4 road 1X RapidIO carries out application verification, generally directed to
The interconnection verification of the respective channel between two devices is also only taken in the verification of 4X RapidIO, as shown in Figure 1, D_R_1- in figure
D_R_4 is the 4 road 1X RapiIO of TMS320C6678；P_R_1-P_R_4 is the 4 road 1X RapidIO of 1601C；C_D_CLK_1-
C_D_CLK_4 is the high-precision difference reference clock that CDCE62005 is the 4 road 125MHz that 1601C is provided, and D_D_CLK is
CDCE62005 is the high-precision difference clock for the 1 road 125MHz that TMS320C6678 is provided.
There is the following aspects in previous design structure：First, it is respectively by differential clocks generation circuit
Clock source is provided per road RapidIO, is not able to verify that different demands of the 4X RapidIO interfaces to differential clocks.Secondly, pass through two
The interconnection of respective pin between a device does not account for the application verification design that 1X is compatible with 4X and is used in mixed way.Finally, device it
Between interconnection only demonstrate design function basically, the comprehensive verification interconnected between plate in actual use can not be covered because
Do not design different connection types, do not comparing when something goes wrong, cannot orientation problem quickly, be not easy to the row of problem
It looks into.
Invention content
It is an object of the invention to the problems in for the above-mentioned prior art, provide a kind of application verification of 4X RapidIO
System and its verification method, which can not only meet under different working modes the needs of to differential clocks, and can expire
Foot is to 1X/4X compatibilities and mixed verification, additionally it is possible to realize the verification of the interconnecting application between device/plate of RapidIO.
To achieve the goals above, the application verification system of 4X RapidIO of the present invention：Including FPGA and 1601P, pass through
Clock chip generate 14 pairs of accurate differential clocks, for FPGA 4 RapidIO Bank 4 pairs of differential clocks are provided, be 1601P's
Wherein 2 road RapidIO provide 4 pairs of differential clocks respectively, and provide 2 pairs of differential clocks for the other 2 road RapidIO of 1601P；
1601P and FPGA is interconnected, and is configured by the operating mode of 4X to 4 RapidIO Bank of FPGA, according to 1601P's
RapidIO operating modes configure the RapidIO Bank operating modes of FPGA；1601P and FPGA are by connector by 2 road 4X
RapidIO is drawn, and carries out interconnection test, carries out trying from translocation between connector.
The clock chip uses 2 CDCM6208, FPGA that XC6VSX475T, connector is selected to select samtec connections
Device；The connection certainly between the interconnection test and connector of 1601P and XC6VSX475T is completed by EPLSP-019-1000 cables
Test.It is interconnected by samtec connector of the both threads cable respectively between 1601P and XC6VSX475T, and two special
Cable is isometric.The every CDCM6208 provides 8 pairs of high-precision difference clocks pair, selects exterior arrangement pattern, generates 8 pairs of phases
Same 125MHz differential clocks pair.The clock chip is provided with filtering and anti-interference electricity to its clock source and power supply module
Road.The clock chip is provided with filtering and anti-jamming circuit on transmission path clock.
The client cables for carrying out interconnection test to 1601P and FPGA are being provided with filtering close to receiving terminal
Capacitance.
On the circuit being connected between the 1601P and connector, receiving terminal is being provided with filter capacitor.
Described 1601P, the FPGA and clock chip is integrated on same pcb board.
The application verification method of 4X RapidIO of the present invention, including the following contents：
1) design of RapidIO differential reference clock sources is carried out according to the quantity of required differential clocks pair by clock chip；
2) driving capabilities of the RapidIO of verification 1601P to differential reference clock；
With the 1st road 4X RapidIO of the 1601P interconnected in FPGA plates a difference is provided per road 1X by 4 road 1X patterns
The 2nd road 4X RapidIO of the 1601P interconnected in clock, with FPGA plates provide a differential clocks by 1 road 4X patterns, and patch
The 3rd road 4X RapidIO of the connected 1601P of part provide a differential clocks by the pattern of 4 road 1X for every road 1X, with connector
The 4th road 4X RapidIO of connected 1601P provide a differential clocks by 1 road 4X patterns；
3) when carrying out the layout and wires design of RapidIO transmission lines, the transmission line of each 4X RapidIO presses difference
Transmission line carries out impedance matching and isometric wiring, and carries out the anti-interference of high-frequency signal in the line termination location close to receiving terminal
Design；
4) when carrying out connector pin definitions, making 1601P, there are one 4X outputs, a 4X inputs；There are one 4X by FPGA
Output, a 4X input；The RapidIO of 1601P-1601P, 1601P-FPGA and FPGA-FPGA are carried out in verification process
Interconnected communication pattern, when something goes wrong by comparing and analyzing, quick positioning question；
5) when 1601P is operated in 1X patterns, FPGA code is designed, forms 4 road RapidIO function IP, and be configured to 1X
Pattern verifies the 1X RapidIO communication functions of 1601P；When 1601P is operated in 4X patterns, FPGA code is designed, forms 1 tunnel
4X RapidIO function IP, and 4X patterns are configured to, verify the 4X RapidIO communication functions of 1601P.
Compared with prior art, the present invention has following advantageous effect：It is mixed using the distribution of differential clocks, 1X/4X
Using and device/plate between mutual contact mode, provide 14 pairs of differential clocks using 2 CDCM6208, meet different operating mould respectively
To the verification demand of differential clocks under formula.It is interconnected using FPGA and 1601P, by the RapidIO Bank Working moulds for configuring FPGA
Formula verifies the 1X/4X compatibilities of RapidIO on 1601P and mixed operating mode.1601P and XC6VSX475T is connect by samtec
Plug-in unit draws 4X RapidIO, and FPGA_RapidIO-1601P_RapidIO, FPGA_RapidIO- are realized by cable
The interconnection of FPGA_RapidIO, 1601P_RapidIO-1601P_RapidIO are tested.The present invention being capable of comprehensive verification RapidIO
Design function, provide design experiences for the investigation of problem and the subsequent system integration and apply example.
Further, the cable that the present invention is used to interconnect 1601P and XC6VSX475T is set close to receiving terminal
It is equipped with filter capacitor, on the circuit being connected between 1601P and samtec connectors, receiving terminal is being provided with filter capacitor,
So that when verifying demand of the different working modes to differential clocks source, it is ensured that the pure property of clock source enhances signal integrity.
Description of the drawings
The existing 4 road 1X RapidIO application verification schematic diagrames of Fig. 1；
The 4 road 4X RapidIO application verification system schematics that Fig. 2 present invention designs；
The 1601P minimum system schematic diagrames that Fig. 3 present invention designs；
The application schematic diagram of Fig. 4 differential clocks circuit CDCM6208 of the present invention；
The XC6VSX475T minimum system schematic diagrames that Fig. 5 present invention designs；
The 1601P that Fig. 6 present invention designs and XC6VSX475T connection diagrams；
The Anti-interference Design circuit diagram in the differential clocks sources of the present invention Fig. 7；
Anti-interference Design circuit diagram in Fig. 8 differential clocks transmission paths of the present invention；
For RapidIO interconnecting signal Completeness Design circuit diagrams between device in Fig. 9 present invention；
For Signal Integrity Design circuit diagram between device and connector in Figure 10 present invention；
The 1601P application verification plate structure schematic diagrams that Figure 11 present invention designs；
Specific implementation mode
Present invention will be described in further detail below with reference to the accompanying drawings.
Referring to Fig. 2,4X RapidIO application verification systems of the invention, in structure include 1601P minimum systems, 2
CDCM6208, XC6VSX475T minimum system, 4 samtec high speeds connectors and 2 EPLSP-019-1000 client cables.
P_R_1-P_R_4 on 1601P is respectively the 4 road 4X RapidIO of 1601P；P_D_CLK_1_1-P_D_CLK_1_4 is
The reference clock by 4 road 1X RapidIO that the P_R_1 that two CDCM6208 are 1601P is provided；P_D_CLK_3_1-P_D_
CLK_3_4 is the reference clock by 4 road 1X RapidIO that the P_R_3 that first CDCM6208 is 1601P is provided；P_D_CLK_
2 and P_D_CLK_4 is the reference by 1 road 4X RapidIO that the P_R_2 that first CDCM6208 is 1601P and P_R_4 is provided
Clock；F_D_CLK_1-F_D_CLK_1_4 is 4 that the 4 road 4X RapidIO that first CDCM6208 is XC6VSX475T are provided
Road differential clocks；Samtec_1 connects two-way 4X the RapidIO F_R_3 and F_R_4 of XC6VSX475T with samtec_2,
Samtec_3 connects 2 road 4X the RapidIO P_R_3 and P_R_4 of 1601P with samtec_4, can pass through external dedicated cable
EPLSP-019-1000 realizes interconnection.1601P is that the high ground term mesh of core grinds first sample chip certainly, need to be for it not in integrated minimum system
With power domain power supply, input clock and memory space etc..Wherein 1.2V_core provides the power supply electricity of 1.2V for the kernel of 1601P
Source；2.5V_IO provides the power supply of 2.5V for the I/O mouths of 1601P；1.5V_MIO is the DDR/QDR control unit interfaces of 1601P
The power supply of 1.5V is provided with external memory；SYS_CLK provides the accurate dominant frequency clock of 100MHz for 1601P；It deposits
External 3 DDR2+SDRAM of memory interface, 3 DDR3+SDRAM and 2 FLASH；To RapidIO carry out with XC6VSX475T,
The connection of samtec connectors designs, as shown in Figure 3.CDCM6208 every can provide 8 pairs of high-precision difference clocks pair, according to answering
With verification demand, using VDD_2.5 be its I/O and kernel is powered, and selects exterior arrangement pattern to generate 8 couples of identical 125MHz poor
Timesharing clock is to Diff_CLK_1-Diff_CLK_8, as shown in Figure 4.XC6VSX475T possesses multiple RapidIO Bank, is carried for it
For power supply and external memory, minimum system is formed.Wherein 1.0V_core provides the power supply of 1.0V for its kernel；1.0V_
MGT provides the power supply of 1.0V for part high speed Bank in FPGA；1.2V_MGT provides 1.2V's for the high speed Bank of FPGA
Power supply；2.5V_IO provides the power supply of 2.5V for the I/O mouths of FPGA；F_CLK provides the high-precision of 50MHz for FPGA
Clock source is as work dominant frequency；F_R_1 is connected with F_R_3 with high speed connector, can be realized by specialized high-speed cable with 1601P
The interconnection of 1X/4X RapidIO and from connection application verification, F_R_2 and F_R_4 in pcb board directly with the two-way of 1601P
RapidIO is interconnected, and realizes functional verification and Performance Evaluation, as shown in Figure 5.2 road 4X are respectively drawn in 1601P and XC6VSX475T
RapidIO can be realized between connection, interconnection test and the plate of 1X/4X compatible operations patterns by 2 EPLSP-019-1000 and be interconnected
Test.Wherein F_R_1-F_R_4 is the 4 road RapidIO of FPGA, and P_R_1-P_R_4 is the 4 road RapidIO, samtec_ of 1601P
1-samtec_4 is 4 high speed connectors, as shown in Figure 6.
It is interconnected by samtec connector of the both threads cable respectively between 1601P and XC6VSX475T, and two
Client cables are isometric, and cable is interconnected communication between test board, and isometric cable is to ensure the signal integrity of high-speed transfer.
The application verification system application conditions of 4X RapidIO of the present invention are as follows：
The application verification design of the invention can be applicable in the application verification design of the device of 4 road 4X RapidIO, remaining
Possess the device of RapidIO application verification and design can also use for reference in the present invention part design, complete to RapidIO's
The Performance Evaluation of functional verification and system integration application.First, when verifying demand of the different working modes to differential clocks source,
The pure property for having to ensure clock source, is filtered clock source and Anti-interference Design.VDD_PLL and VDD_VCO are
The PLL phaselocked loop power pins of CDCM6208 utilize EMI-TL2012 laminated filters and two height in externally fed
The capacitance composition filtering of collocation and anti-jamming circuit, pure power supply is provided for PLL；ELF is external filter input pipe
Foot, according to corresponding operating mode, in the RC filter networks of exterior design relevant parameter, it is ensured that clock signal clean and do not lose
Very, as shown in Figure 7.It is filtered on transmission path clock and Anti-interference Design, i.e., adds filtered electrical in the end of differential clocks
Hold, Diff_CLK_1-Diff_CLK_8 is 8 differential clocks pair of CDCM6208 outputs, and C is filter capacitor, as shown in Figure 8.
Secondly, when carrying out the application verification design between device by RapidIO, the connection cabling between two devices is as much as possible
It is short, it is ensured that every group of signal wire is isometric under the conditions of 4X operating modes, and adds filtered electrical close to device position in the receiving terminal of signal wire
Hold.TX/RX is respectively transmission/reception signal of the RapidIO of 1601P and FPGA, as shown in Figure 9.Finally, it is carrying out
Between the plate of RapidIO from connection and interconnecting application verification design when, connector is close proximity to the edge of pcb board, and connector and device
The signal wire cabling of part is short as much as possible, equally, between device and connector according to the type of signal in receiving terminal close to device
Part or connector are placed around filter capacitor, enhance the signal integrity of system.TX/RX is respectively the hair of the RapidIO of 1601P
It is filter capacitor to send/receive signal, C, and samtec is the dedicated high speed connectors of RapidIO, as shown in Figure 10.
It is a multi-core DSP processor based on the 1601P of the high ground term mesh of core " magnanimity information processing device " design, inside collection
At multiple autonomous instruction set DSP cores and 1 Power PC main control processor core, outside possesses DDR sdram interfaces, Rapid IO
The high-speed interfaces such as interface and QDRII interfaces.The wherein integrated two-way RapidIO interfaces in 4 tunnels support 4X and 1X patterns per road, single
A differential pair message transmission rate is 2.5Gbps.For the above design parameter, technical solution according to the invention designs 1601P
Application verification system, structure is as shown in figure 11.Pass through the actual test verification to 1601P application verification systems, 4 road 4X
The design function of RapidIO is verified.Verification result shows the application verification system based on the invention conceptual design, energy
Enough application verifications realized to 4X RapidIO realize the verification of compatible, the mixed operating modes of system 1X/4X and its to difference
The demand of clock, and the application verification between device/plate from connection/interconnection has been carried out, utmostly play the work(of application verification plate
It is able to verify that the function with application and development.Specifically, the verification method of the application verification system of 4X RapidIO of the present invention is as follows：
1. when carrying out the design of RapidIO differential reference clock sources, according to the quantity of required differential clocks pair in the design,
Select high-precision difference clock generator part CDCM6208, by filter and filter capacitor be combined in the way of design filtering and
Anti-jamming circuit is powered for itself PLL and VCO pin, with the stability for ensuring its power supply and pure property；Use PIN MODE patterns
In 0X06 patterns it is configured, so that every CDCM6208 is exported the high-precision difference clock of 8 road 125MHz, and this 8 tunnel
Phase relation between clock is adjustable；On the transmission line that differential clocks export to 1601P and FPGA, close to line terminal
Position configures filter capacitor, forms the anti-jamming circuit of high frequency clock signal.
2. in order to verify demands of the RapidIO of 1601P to differential reference clock driving capability, with FPGA into andante mutually
The 1st road 4X RapidIO of the 1601P of connection provide a differential clocks for it by 4 road 1X patterns per road 1X；With FPGA into andante
The 2nd road 4X RapidIO of the 1601P of interior interconnection provide a differential clocks by 1 road 4X patterns for it；With samtec connectors
The 3rd road 4X RapidIO of connected 1601P provide a differential clocks for it by the pattern of 4 road 1X per road 1X；With samtec
The 4th road 4X RapidIO of the connected 1601P of connector provide a differential clocks by 1 road 4X patterns for it.
When the layout and wires design of 3.RapidIO transmission lines, the transmission line of each 4X RapidIO presses differential transfer
Line carries out impedance matching and isometric wiring, and is equipped with capacitance in the line termination location close to receiving terminal and carries out the anti-of high-frequency signal
Disturbance-proof design.
4. carry out samtec connector pin definitions, it is ensured that there are one 4X outputs, a 4X inputs by 1601P；FPGA has
One 4X output, a 4X input.In this way, 1601P-1601P, 1601P-FPGA and FPGA- can be carried out in verification process
The RapidIO interconnected communication patterns of FPGA, are being convenient for comparative analysis, quick positioning question when something goes wrong.
5. carrying out the interconnection between samtec connectors using EPLSP-019-1000 specialized high-speed circuits.
6. in the RapidIO communications between verifying 1601P-FPGA, when 1601P is operated in 1X patterns, FPGA is designed
Code forms 4 road RapidIO function IP, and is configured to 1X patterns, verifies the 1X RapidIO communication functions of 1601P；When
When 1601P is operated in 4X patterns, FPGA code is designed, forms 1 road 4X RapidIO function IP, and be configured to 4X patterns, is verified
The communication function of the 4X RapidIO of 1601P.
The foregoing is merely presently preferred embodiments of the present invention, the equivalent change that all rights according to the present invention are done
With modification, it should all belong to the covering scope of the claims in the present invention.
Claims (10)
1. a kind of application verification system of 4X RapidIO, it is characterised in that：Including FPGA and 1601P, produced by clock chip
Raw 14 pairs of accurate differential clocks, for FPGA 4 RapidIO Bank 4 pairs of differential clocks are provided, wherein 2 tunnels that are 1601P
RapidIO provides 4 pairs of differential clocks respectively, and provides 2 pairs of differential clocks for the other 2 road RapidIO of 1601P；1601P with
FPGA is interconnected, and is configured by the operating mode of 4X to 4 RapidIO Bank of FPGA, is worked according to the RapidIO of 1601P
The RapidIO Bank operating modes of pattern configurations FPGA；1601P and FPGA is drawn 2 road 4X RapidIO by connector,
And interconnection test is carried out, it carries out trying from translocation between connector.
2. the application verification system of 4X RapidIO according to claim 1, it is characterised in that：The clock chip uses
2 CDCM6208, FPGA select XC6VSX475T, connector to select samtec connectors；Pass through EPLSP-019-1000 cables
Interconnecting for 1601P and XC6VSX475T is completed to try from translocation between test and connector.
3. the application verification system of 4X RapidIO according to claim 2, it is characterised in that：It is right respectively by both threads cable
Samtec connectors between 1601P and XC6VSX475T are interconnected, and two client cables are isometric.
4. the application verification system of 4X RapidIO according to claim 2, it is characterised in that：The every CDCM6208
8 pairs of high-precision difference clocks pair are provided, exterior arrangement pattern is selected, generate 8 pairs of identical 125MHz differential clocks pair.
5. the application verification system of 4X RapidIO according to claim 1, it is characterised in that：The clock chip is to it
Clock source and power supply module are provided with filtering and anti-jamming circuit.
6. according to the application verification system of the 4X RapidIO of claim 1 or 5, it is characterised in that：The clock chip
Filtering and anti-jamming circuit are provided on transmission path clock.
7. the application verification system of 4X RapidIO according to claim 1, it is characterised in that：It is described for 1601P with
FPGA is carried out in the client cables of interconnection test, and receiving terminal is being provided with filter capacitor.
8. according to the application verification system of the 4X RapidIO of claim 1 or 7, it is characterised in that：The 1601P with connect
On the circuit being connected between plug-in unit, receiving terminal is being provided with filter capacitor.
9. the application verification system of 4X RapidIO according to claim 1, it is characterised in that：Described 1601P, the FPGA with
And clock integrated chip is on same pcb board.
10. a kind of verification method of the application verification system of 4X RapidIO, it is characterised in that：
1) design of RapidIO differential reference clock sources is carried out according to the quantity of required differential clocks pair by clock chip；
2) driving capabilities of the RapidIO of verification 1601P to differential reference clock；
When providing a difference by 4 road 1X patterns for every road 1X with the 1st road 4X RapidIO of the 1601P interconnected in FPGA plates
The 2nd road 4X RapidIO of the 1601P interconnected in clock, with FPGA plates provide a differential clocks by 1 road 4X patterns, with connector
The 3rd road 4X RapidIO of connected 1601P provide a differential clocks by the pattern of 4 road 1X for every road 1X, with connector phase
The 4th road 4X RapidIO of 1601P even provide a differential clocks by 1 road 4X patterns；
3) when carrying out the layout and wires design of RapidIO transmission lines, the transmission line of each 4X RapidIO presses differential transfer
Line carries out impedance matching and isometric wiring, and carries out the anti-interference of high-frequency signal in the line termination location close to receiving terminal and set
Meter；
4) when carrying out connector pin definitions, making 1601P, there are one 4X outputs, a 4X inputs；There are one 4X to export by FPGA,
One 4X input；The mutual unicom of RapidIO of 1601P-1601P, 1601P-FPGA and FPGA-FPGA are carried out in verification process
Letter pattern, when something goes wrong by comparing and analyzing, quick positioning question；
5) when 1601P is operated in 1X patterns, FPGA code is designed, forms 4 road RapidIO function IP, and be configured to 1X patterns,
Verify the 1X RapidIO communication functions of 1601P；When 1601P is operated in 4X patterns, FPGA code is designed, forms 1 road 4X
RapidIO function IP, and 4X patterns are configured to, verify the 4X RapidIO communication functions of 1601P.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113704163A (en) * | 2021-09-08 | 2021-11-26 | 天津津航计算技术研究所 | Testing device and method for verifying integrity of SRIO protocol |
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| CN107329872A (en) * | 2017-07-05 | 2017-11-07 | 西安微电子技术研究所 | A kind of application verification plate of coprocessor |
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| US20070104219A1 (en) * | 2005-11-09 | 2007-05-10 | Honeywell International Inc. | System and method to facilitate testing of rapidio components |
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| CN106936735A (en) * | 2017-04-01 | 2017-07-07 | 济南浪潮高新科技投资发展有限公司 | A kind of ten thousand mbit ethernets based on domestic CPU are exchanged and RAPIDIO exchanges fusion plate |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113704163A (en) * | 2021-09-08 | 2021-11-26 | 天津津航计算技术研究所 | Testing device and method for verifying integrity of SRIO protocol |
| CN113704163B (en) * | 2021-09-08 | 2024-04-19 | 天津津航计算技术研究所 | Testing device and method for verifying SRIO protocol integrity |
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