CN206515812U - A kind of test board of server admin unit - Google Patents
A kind of test board of server admin unit Download PDFInfo
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- CN206515812U CN206515812U CN201720229725.7U CN201720229725U CN206515812U CN 206515812 U CN206515812 U CN 206515812U CN 201720229725 U CN201720229725 U CN 201720229725U CN 206515812 U CN206515812 U CN 206515812U
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Abstract
The utility model discloses a kind of test board of server admin unit, belong to a kind of board, technical problem to be solved in the utility model is：Examination equipment is being accompanied without the help of outside, the problem of all test functions of test cell can be covered again.Technical scheme is：Including power supply, manage connector for substrate, PCIE golden fingers, PHY chip, CPLD chips, SWITCH is switched, fan connector, I2C extended chips, RTC chip, I2C connectors, electrical level conversion chip, FLASH chip, USB connector, PECI connectors, voltage sensor, temperature sensor, potentiometer and VGA connector, power supply is used to power to management connector for substrate, management connector for substrate connects power supply respectively, PCIE golden fingers, two PHY chips, CPLD chips, SWITCH is switched, fan connector, I2C extended chips, RTC chip, I2C connectors, three electrical level conversion chips, FLASH chip, two USB connectors, PECI connectors, voltage sensor, temperature sensor, potentiometer and VGA connector.
Description
Technical field
The utility model is related to a kind of board, specifically a kind of test board of server admin unit.
Background technology
In the R ＆ D design of server, it usually needs server is tested using test board, traditional test board
Mainly to insert the slot on motherboard, functional test is carried out to multiple pins in slot.And traditional multi-unit server
Administrative unit realize that function is complex, test need could be carried out by computer unit, crosspoint and complete machine case,
Test process is very cumbersome.
In view of the above-mentioned problems, such as patent 201410798415.8, entitled " one kind is based on the management of domestic multi-unit server
The test device and method of unit ", the test device includes a test board and accompanies to be provided with examination equipment, test board to connect at a high speed
Device, high speed connector is docked with the corresponding high speed connector of multi-unit server administrative unit, and test board can be obtained or carried
For multichannel signal in place, multipath VGA signal, multichannel usb signal, multi-channel network signal and crosspoint CPU card network signal,
Crosspoint BMC network signals；By examination equipment is accompanied global function test can be carried out to multi-unit server administrative unit.The survey
Although the troublesome operation for solving and being tested multi-unit server administrative unit is put in trial assembly, there is a problem in that：
, it is necessary to accompany examination equipment to test by means of outside when the 1, testing server admin unit；2nd, to server pipe
, may be incomplete because of test event when reason unit is tested, or some mainboards do not support some functions, it is impossible to cover test
All test functions of unit.
Therefore, how just can guarantee that and accompanying examination equipment without the help of outside, all tests of test cell can be covered again
The problem of function is in the urgent need to address at present.
The content of the invention
Technical assignment of the present utility model is that deficiency, there is provided a kind of test board of server admin unit, is come for more than
How solution makes product be applicable in the design of a variety of servers, reduces the design cost of product and enables product spirit
The problem of application and convenient assembly and disassembly living.
Technical assignment of the present utility model realizes in the following manner,
A kind of test board of server admin unit, including power supply, management connector for substrate, PCIE golden fingers, PHY chip,
CPLD chips, SWITCH switches, fan connector, I2C extended chips, RTC（Real-time clock controller）Chip, I2C connections
Device, electrical level conversion chip, FLASH chip, USB connector, PECI connectors, voltage sensor, temperature sensor, potentiometer with
And VGA connector, power supply to management connector for substrate for powering, and management connector for substrate connects power supply, PCIE golden fingers, two respectively
Individual PHY chip, CPLD chips, SWITCH switches, fan connector, I2C extended chips, RTC chip, I2C connectors, three
Electrical level conversion chip, FLASH chip, two USB connectors, PECI connectors, voltage sensor, temperature sensor, potentiometers
And VGA connector；The other end of two PHY chips is connected with RJ45 interfaces respectively；The other end of CPLD chips and LED phases
Even；Wherein one end of SWITCH output switching terminals is connected with JTAG connectors, and the other end is connected with CPLD chips；I2C extends core
The other end of piece is connected with temperature sensor；The other end of three electrical level conversion chips is connected with RJ45 interfaces respectively.
UART signal is converted to RS3232 signals by electrical level conversion chip and picks out RJ45 interfaces by management connector for substrate,
To support the functional verification by connecting serial ports cable；
FLASH chip is SPI FLASH chips, and SPI signal is connected in SPI FLASH chips by management connector for substrate, with
It is verified read-write capability of the SPI signal to FLASH chip；
Multigroup I2C signals are coupled with CPLD chips, I2C extended chips, on RTC chip, propped up by management connector for substrate
Hold the checking to I2C functions；I/O signal is connected to LED by management connector for substrate by CPLD chips；
VGA signals are connected to VGA connector by management connector for substrate, to support to connect display, checking by VGA connector
VGA semiotic functions；
JTAG signal is connected on CPLD chips by management connector for substrate by SWITCH switches, to support checking to CPLD cores
Piece carries out the function of offline burning program；JTAG signal is connected on JTAG connectors by the SWITCH switch other ends, supports to pass through
Burning line carries out the function of burning program to CPLD chips；
Two-way RGMII signals are changed into MDI signals by management connector for substrate by PHY chip respectively, pass through RJ45 interfaces
Draw, to support the checking by connected with network cable to network communicating function；
PCIE signal is connected to PCIE golden fingers by management connector for substrate, to verify the function of PCIE interfaces；
Fan control signal is connected to fan connector by management connector for substrate, to support the test to fan speed-regulating function.
Electrical level conversion chip uses MAX3232 chips.
PHY chip is using 2 gigabit VSC8211 PHY chips.
I2C extended chips use PCA9548 chips.
RTC chip uses DS3232N chips.
Power source supplying voltage is 3.3V.
A kind of test board of server admin unit of the present utility model compared to the prior art, with advantages below：
1st, it can be used for connection management unit, and it tested, comprehensively, a test board can be solved test event
A variety of test performances；
2nd, functional verification, flash read-write capability test, the support pair of serial ports cable can be attached to administrative unit
The checkings of I2C functions, checking VGA semiotic functions, it is verified administrative unit the function of offline burning program, branch is carried out to CPLD
Hold by burning line CPLD is carried out burning program function, come support by connected with network cable to the checking of network communicating function,
To support to be inserted on other boards PCIE SLOT come the function of the PCIE interfaces of verification management unit by test board, to support
Test to fan speed-regulating function, to support by connecting test of the USB device to usb communication function, checking common I/O signals
Function.
Brief description of the drawings
The utility model is further illustrated below in conjunction with the accompanying drawings.
Accompanying drawing 1 is a kind of structured flowchart of the test board of server admin unit.
Embodiment
A kind of test board of server admin unit of the present utility model is made with reference to Figure of description and specific embodiment
It is explained in detail below.
Embodiment 1：
A kind of test board of server admin unit, including power supply, management connector for substrate, PCIE golden fingers, PHY chip,
CPLD chips, SWITCH switches, fan connector, I2C extended chips, RTC（Real-time clock controller）Chip, I2C connections
Device, electrical level conversion chip, FLASH chip, USB connector, PECI connectors, voltage sensor, temperature sensor, potentiometer with
And VGA connector, power supply to management connector for substrate for powering, and power source supplying voltage is 3.3V, and management connector for substrate connects respectively
Meet power supply, PCIE golden fingers, two PHY chips, CPLD chips, SWITCH switches, fan connector, I2C extended chips, RTC
Chip, I2C connectors, three electrical level conversion chips, FLASH chip, two USB connectors, PECI connectors, voltage sensors
Device, temperature sensor, potentiometer and VGA connector；The other end of two PHY chips is connected with RJ45 interfaces respectively；CPLD
The other end of chip is connected with LED；Wherein one end of SWITCH output switching terminals is connected with JTAG connectors, the other end and CPLD
Chip is connected；The other end of I2C extended chips is connected with temperature sensor；The other end of three electrical level conversion chips respectively with
RJ45 interfaces are connected.
Electrical level conversion chip uses MAX3232 chips, and management connector for substrate turns UART signal by electrical level conversion chip
It is changed to RS3232 signals and picks out RJ45 interfaces, supports the functional verification by connecting serial ports cable；
FLASH chip is SPI FLASH chips, and SPI signal is connected in SPI FLASH chips by management connector for substrate, with
It is verified read-write capability of the SPI signal to FLASH chip；
Multigroup I2C signals are coupled with CPLD chips, I2C extended chips by management connector for substrate, and I2C extended chips are used
PCA9548 chips, RTC chip, RTC chip have supported the checking to I2C functions using on DS3232N chips；Management board is connected
I/O signal is connected to LED by device by CPLD chips；
VGA signals are connected to VGA connector by management connector for substrate, to support to connect display, checking by VGA connector
VGA semiotic functions；
JTAG signal is connected on CPLD chips by management connector for substrate by SWITCH switches, to support checking to CPLD cores
Piece carries out the function of offline burning program；JTAG signal is connected on JTAG connectors by the SWITCH switch other ends, supports to pass through
Burning line carries out the function of burning program to CPLD chips；
PHY chip is passed through two-way RGMII signals using 2 gigabit VSC8211 PHY chips, management connector for substrate respectively
PHY chip changes into MDI signals, is drawn by RJ45 interfaces, to support the checking by connected with network cable to network communicating function；
PCIE signal is connected to PCIE golden fingers by management connector for substrate, to verify the function of PCIE interfaces；
Fan control signal is connected to fan connector by management connector for substrate, to support the test to fan speed-regulating function.
By embodiment above, the those skilled in the art can readily realize the utility model.But
It is it should be appreciated that the utility model is not limited to above-mentioned embodiment.It is described on the basis of disclosed embodiment
Those skilled in the art can be combined different technical characteristics, so as to realize different technical schemes.
It is the known technology of those skilled in the art in addition to the technical characteristic described in specification.
Claims (7)
1. a kind of test board of server admin unit, it is characterised in that including power supply, management connector for substrate, PCIE golden fingers,
PHY chip, CPLD chips, SWITCH switches, fan connector, I2C extended chips, RTC chip, I2C connectors, level turn
Change chip, FLASH chip, USB connector, PECI connectors, voltage sensor, temperature sensor, potentiometer and VGA connections
Device, power supply is used to power to management connector for substrate, and management connector for substrate connects power supply, PCIE golden fingers, two PHY cores respectively
Piece, CPLD chips, SWITCH switches, fan connector, I2C extended chips, RTC chip, I2C connectors, three level translations
Chip, FLASH chip, two USB connectors, PECI connectors, voltage sensor, temperature sensor, potentiometer and VGA connect
Connect device；The other end of two PHY chips is connected with RJ45 interfaces respectively；The other end of CPLD chips is connected with LED；SWITCH is opened
The wherein one end for closing output end is connected with JTAG connectors, and the other end is connected with CPLD chips；The other end of I2C extended chips
It is connected with temperature sensor；The other end of three electrical level conversion chips is connected with RJ45 interfaces respectively.
2. the test board of a kind of server admin unit according to claim 1, it is characterised in that management connector for substrate will
UART signal is converted to RS3232 signals by electrical level conversion chip and picks out RJ45 interfaces；
FLASH chip is SPI FLASH chips, and SPI signal is connected in SPI FLASH chips by management connector for substrate；
Multigroup I2C signals are coupled with CPLD chips, I2C extended chips, on RTC chip by management connector for substrate；Management board connects
Connect device and I/O signal is connected to LED by CPLD chips；
VGA signals are connected to VGA connector by management connector for substrate；
JTAG signal is connected on CPLD chips by management connector for substrate by SWITCH switches, and SWITCH switchs the other end by JTAG
Signal is connected on JTAG connectors；
Two-way RGMII signals are changed into MDI signals by management connector for substrate by PHY chip respectively, are drawn by RJ45 interfaces；
PCIE signal is connected to PCIE golden fingers by management connector for substrate；
Fan control signal is connected to fan connector by management connector for substrate.
3. the test board of a kind of server admin unit according to claim 1, it is characterised in that electrical level conversion chip is adopted
Use MAX3232 chips.
4. the test board of a kind of server admin unit according to claim 1, it is characterised in that PHY chip uses 2
Gigabit VSC8211 PHY chips.
5. the test board of a kind of server admin unit according to claim 1, it is characterised in that I2C extended chips are used
PCA9548 chips.
6. the test board of a kind of server admin unit according to claim 1, it is characterised in that RTC chip is used
DS3232N chips.
7. a kind of test board of server admin unit according to claim 1, it is characterised in that power source supplying voltage is
3.3V。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201720229725.7U CN206515812U (en) | 2017-03-10 | 2017-03-10 | A kind of test board of server admin unit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201720229725.7U CN206515812U (en) | 2017-03-10 | 2017-03-10 | A kind of test board of server admin unit |
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| Publication Number | Publication Date |
|---|---|
| CN206515812U true CN206515812U (en) | 2017-09-22 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201720229725.7U Expired - Fee Related CN206515812U (en) | 2017-03-10 | 2017-03-10 | A kind of test board of server admin unit |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107766186A (en) * | 2017-10-11 | 2018-03-06 | 郑州云海信息技术有限公司 | A kind of expansible fan board test board of USB interface and application method |
| CN107908585A (en) * | 2017-11-30 | 2018-04-13 | 郑州云海信息技术有限公司 | A kind of PCIE BOX plates for surpassing calculation function with PCIe card and GPU |
| CN109992555A (en) * | 2019-03-13 | 2019-07-09 | 苏州浪潮智能科技有限公司 | A kind of management board shared for multipath server |
| CN110375961A (en) * | 2019-07-29 | 2019-10-25 | 武汉电信器件有限公司 | A kind of automatic test approach of optical module and the Auto-Test System of optical module |
| CN111158710A (en) * | 2019-12-30 | 2020-05-15 | 杭州迪普科技股份有限公司 | Program programming method and device and network equipment |
| CN115982086A (en) * | 2023-02-14 | 2023-04-18 | 井芯微电子技术(天津)有限公司 | Chip prototype verification board |
-
2017
- 2017-03-10 CN CN201720229725.7U patent/CN206515812U/en not_active Expired - Fee Related
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107766186A (en) * | 2017-10-11 | 2018-03-06 | 郑州云海信息技术有限公司 | A kind of expansible fan board test board of USB interface and application method |
| CN107908585A (en) * | 2017-11-30 | 2018-04-13 | 郑州云海信息技术有限公司 | A kind of PCIE BOX plates for surpassing calculation function with PCIe card and GPU |
| CN109992555A (en) * | 2019-03-13 | 2019-07-09 | 苏州浪潮智能科技有限公司 | A kind of management board shared for multipath server |
| CN110375961A (en) * | 2019-07-29 | 2019-10-25 | 武汉电信器件有限公司 | A kind of automatic test approach of optical module and the Auto-Test System of optical module |
| CN111158710A (en) * | 2019-12-30 | 2020-05-15 | 杭州迪普科技股份有限公司 | Program programming method and device and network equipment |
| CN111158710B (en) * | 2019-12-30 | 2023-08-25 | 杭州迪普科技股份有限公司 | Program programming method, device and network equipment |
| CN115982086A (en) * | 2023-02-14 | 2023-04-18 | 井芯微电子技术(天津)有限公司 | Chip prototype verification board |
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| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20170922 Termination date: 20180310 |