CN108572544B - AC/DC B code self-adaptive analysis device and method - Google Patents
AC/DC B code self-adaptive analysis device and method Download PDFInfo
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Abstract
The invention relates to a time receiving and processing device, in particular to an alternating current-direct current B code self-adaptive analysis device and method. The intelligent control system comprises a power module, a B code processing module, a backboard module and a display control module. The B code processing module adopts an analysis processing mode of amplitude self-adaption and polarity self-adaption, and can correct the delay parameters of the analyzed pulse per second, so that an accurate pulse per second signal is obtained, and the convenience of user signal access is realized; a temperature control circuit is arranged between the first DC/DC module and the second switch control circuit of the power module, and comprises a thermistor, a voltage comparator and an MOS (metal oxide semiconductor) tube, when the ambient temperature reaches about +80 ℃, the voltage output is closed, the equipment is prevented from being damaged during high-temperature work, and the service life of the whole machine is prolonged.
Description
Technical Field
The invention relates to a time receiving and processing device, in particular to an alternating current-direct current B code self-adaptive analysis device and method.
Background
Time measurement, time information transmission and application are indispensable in people's life, national economic development, especially national defense construction. The rapid development of science and technology makes people put forward higher and higher requirements on time precision, such as systems for providing standard time signals for satellite or spacecraft launching, conventional weapon tests, measurement and control systems and the like. There are many methods for time service at present, including: satellite time service: such as the Beidou system and the GPS system of the United states of China; short-wave time service: the signal coverage area is small, and the equipment volume is large; long-wave time service: the signal coverage area is small, and the equipment volume is large; network time service: including NTP and PTP; carrying out parallel time service: binary signals are transmitted in parallel, and the transmission distance is short; b code time service: the time service system comprises an alternating current code and a direct current code, has high anti-interference characteristic and the like because of signal transmission in a wired mode, and has application environments according to the characteristics of various time service modes.
The B code signal is divided into two transmission modes of a B code alternating current signal (B-AC) and a B code direct current signal (B-DC), the signals contain information content and format as shown in figure 1, the B-DC signal is generally transmitted by adopting a differential signal and has nanosecond-level time service precision; the B-AC code can meet the requirement of long-distance time information transmission and can reach microsecond-level time service precision.
After the B code time service device in the prior art works at a high temperature for a long time, the abnormal condition of a power supply is easy to occur, so that other parts are damaged, the performance of the whole machine is influenced, self-correction cannot be realized when time information is wrong, and errors are easy to cause during long-distance transmission.
Disclosure of Invention
The technical problem to be solved by the invention is to overcome the defects of the prior art, and provide an AC/DC B code self-adaptive analysis device and method, which can realize the functions of B code AC/DC signal analysis, self-adaptive adjustment of input amplitude and polarity, display of receiving time information and state and the like; in addition, the extensible function slot position is provided, other function modules can be inserted, and different business functions can be quickly realized, so that the development speed is increased, and the development cost is reduced.
The technical scheme for solving the technical problems in the patent is as follows: an alternating current-direct current B code self-adaptive analysis device comprises a power module, a B code processing module, a backboard module and a display control module;
the power supply module supplies power to each module through the backboard module;
b sign indicating number processing module, through the backplate module with it links to each other to show accuse module, B sign indicating number processing module gathers chip and alternating current-direct current converting circuit including transformer, numerical control attenuator and AD that connect in order, alternating current-direct current converting circuit interconnect FPGA processing circuit, FPGA processing circuit interconnect ARM processing circuit, level converting circuit is connected to FPGA processing circuit's input, and the output is connected numerical control attenuator, protection circuit is connected to level converting circuit's input.
The backboard module interconnects all the modules through onboard high-speed sockets;
the display control module is connected with the B code processing module through the backboard module and comprises an information processing module and a display module, the information processing module is used for receiving the state of each module and the information required to be displayed, and the display module is used for displaying the B code analysis time and the state information received by the information processing module.
Further, the intelligent network system further comprises a switch module, wherein the switch module comprises 8 network ports in expansion, 5 network ports of the switch module are interconnected with the modules through the backboard module, and the other 3 network ports are used for completing data communication with external equipment.
Further, the power supply module comprises a power supply protection circuit, a direct current filter, a first switch control circuit, a first DC/DC module and a second switch control circuit which are connected in sequence.
Further, a temperature control circuit is arranged between the first DC/DC module and the second switch control circuit of the power supply module.
Furthermore, the temperature control circuit comprises a thermistor, a voltage comparator and an MOS (metal oxide semiconductor) tube, and when the ambient temperature reaches about +80 ℃, the voltage output is closed, so that the equipment is prevented from being damaged during high-temperature work.
Furthermore, the output end of the second control circuit of the power supply module is provided with a second DC/DC module and a third DC/DC module for subsequently expanding the output function of the alternating current B code.
Furthermore, the display module is a low-temperature serial port liquid crystal display module.
An AC/DC B code self-adaptive analysis method comprises the following specific steps:
step one, high level time statistics: performing high-level timing on an input direct-current signal to obtain redundant counts of 2ms, 5ms and 8 ms;
step two, verifying the whole second: judging and verifying 8ms of the whole second moment, if the judgment result shows that the input signal is valid, carrying out delay parameter correction on the analyzed second pulse so as to obtain a correct second pulse signal, writing a count obtained by timing into an FIFO (first in first out) space of the FPGA (field programmable gate array) processing circuit for data caching, and informing the ARM processing circuit to carry out reading analysis;
and step three, the ARM processing circuit completes the analysis of the information layer according to the standard protocol of the B code and sends the time data to the display control module and the external equipment through the backboard module.
Further, the input dc signal is a dc signal generated by an ac B-code input, and the specific process is as follows: the AC B code input from the outside enters a transformer for isolation and then enters a numerical control attenuator for amplitude adaptive control; then, the AC signal data is acquired by an AD acquisition chip; the alternating current signal is subjected to signal conditioning through a signal conditioning circuit, whether a sampling value exceeds a set maximum threshold or not is judged through AD data sampled in an FPGA processing circuit, and if the sampling value exceeds the set maximum threshold, the numerical control attenuator is controlled to increase attenuation until the amplitude requirement is met; if the peak value is too small, controlling the numerical control attenuator to reduce the attenuation until the amplitude meets the requirement or the attenuation reaches the minimum value, so that the AD sampling value is always in the optimal value range; and then, calculating the adjusted sampling value to obtain a zero-position voltage and a high-low level decision threshold, estimating a zero-crossing point and a peak position of the input signal according to the zero-position voltage, converting the sampled alternating-current B code signal into a direct-current B code signal at the peak moment according to the decision threshold, judging whether the polarity of the input signal is correct or not according to the sampling value at the peak position, and reversing the obtained direct-current B code signal if the polarities are inconsistent.
Further, the input dc signal is a dc signal generated by a dc B code input, and the specific process is as follows: the direct current B code signal input from the outside is sent to the FPGA processing circuit for processing after passing through the protection circuit and the level conversion circuit.
The beneficial effect of this patent is:
1. the B code processing module adopts an analysis processing mode of amplitude self-adaption and polarity self-adaption, and can correct the delay parameters of the analyzed pulse per second, so that an accurate pulse per second signal is obtained, and the convenience of user signal access is realized;
2. according to the power module, the temperature control circuit is arranged between the first DC/DC module and the second switch control circuit, the temperature control circuit comprises the thermistor, the voltage comparator and the MOS tube, when the ambient temperature reaches about +80 ℃, the voltage output is closed, the equipment is prevented from being damaged during high-temperature work, and the service life of the whole power module is prolonged;
3. the switch module comprises 8 network port expansion, wherein 5 network ports of the switch module are interconnected with each module through the backboard module, and the other 3 network ports are used for completing data communication with external equipment, so that the expansion of multiple Ethernet interfaces is realized, and the access quantity of internal and external equipment is effectively increased.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.
FIG. 1 is a diagram illustrating the information content and format of a B-code AC/DC signal;
FIG. 2 is a schematic block diagram of a power module of the present invention;
FIG. 3 is a schematic block diagram of B-code DC signal processing according to the present invention;
FIG. 4 is a functional block diagram of a B-code processing module according to the present invention;
FIG. 5 is a schematic block diagram of a B-code AC to DC signal according to the present invention.
Detailed Description
The invention aims to provide an AC/DC B code self-adaptive analysis device and method, which can realize the functions of B code AC/DC signal analysis, self-adaptive adjustment of input amplitude and polarity, display of receiving time information and state and the like. In addition, the extensible function slot position is provided, other function modules can be inserted, and different business functions can be quickly realized, so that the development speed is increased, and the development cost is reduced.
The invention relates to an AC/DC B code analysis device, comprising: the system comprises a power module, a B code processing module, a switch module, a display control module, other modules and the like, wherein all plug-ins are interconnected through interfaces of a backboard module.
The power supply module supplies power to each module through the backboard module;
b sign indicating number processing module, through the backplate module with it links to each other to show accuse module, B sign indicating number processing module gathers chip and alternating current-direct current converting circuit including transformer, numerical control attenuator and AD that connect in order, alternating current-direct current converting circuit interconnect FPGA processing circuit, FPGA processing circuit interconnect ARM processing circuit, level converting circuit is connected to FPGA processing circuit's input, and the output is connected numerical control attenuator, protection circuit is connected to level converting circuit's input.
The backboard module interconnects all the modules through onboard high-speed sockets;
the display control module is connected with the B code processing module through the backboard module and comprises an information processing module and a display module, the information processing module is used for receiving the state of each module and the information required to be displayed, and the display module is used for displaying the B code analysis time and the state information received by the information processing module.
Further, the intelligent network system further comprises a switch module, wherein the switch module comprises 8 network ports in expansion, 5 network ports of the switch module are interconnected with the modules through the backboard module, and the other 3 network ports are used for completing data communication with external equipment.
Further, the power supply module comprises a power supply protection circuit, a direct current filter, a first switch control circuit, a first DC/DC module and a second switch control circuit which are connected in sequence.
Further, a temperature control circuit is arranged between the first DC/DC module and the second switch control circuit of the power supply module.
Furthermore, the temperature control circuit comprises a thermistor, a voltage comparator and an MOS (metal oxide semiconductor) tube, and when the ambient temperature reaches about +80 ℃, the voltage output is closed, so that the equipment is prevented from being damaged during high-temperature work.
Furthermore, the output end of the second control circuit of the power supply module is provided with a second DC/DC module and a third DC/DC module for subsequently expanding the output function of the alternating current B code.
Furthermore, the display module is a low-temperature serial port liquid crystal display module.
The power module is implemented by the functional block diagram shown in fig. 2, wherein an external power input firstly passes through a power protection circuit, and the power protection circuit comprises an anti-surge design performed by a TVS (JK30), an anti-reverse connection circuit formed by a MOS (SUD50P04) and a direct current filter added for considering the electromagnetic compatibility design; the direct current power supply protection circuit outputs a voltage, the voltage is input into a first DC/DC module (FED 60-24S 12) after passing through a direct current filter and a first switch control circuit, the voltage is output by a second switch control circuit, a temperature control circuit is additionally arranged between the first DC/DC module and the second switch control circuit and comprises a thermistor, a voltage comparator (MAX931) and an MOS (SI4497) tube circuit, when the ambient temperature reaches about +80 ℃, the voltage output is closed, and the equipment is prevented from being damaged during high-temperature work; in consideration of the subsequent extension of the alternating current B code output function, a second DC/DC module and a third DC/DC module which generate +8V and-8V are added into the power supply module.
The hardware implementation block diagram of the B code processing module is shown in fig. 4, the front panel includes B code ac/dc input and output, a test serial port and a status indicator, and the rear interface includes a serial port, an ethernet port, a CAN port, an I2C, and other interfaces. Because the peak-to-peak value range of an alternating current B code signal input from the outside reaches + 0.5V- +10V, the modulation ratio is 2: 1-6: 1, in order to enable the machine to be adaptive to different input ranges, after the input end of the AC is isolated by a transformer, the AC enters a numerical control attenuator to carry out amplitude adaptive control, so that the voltage amplitude input into an AD acquisition chip (ADS808Y) meets the requirement that the peak-to-peak value is not more than 2V, and the numerical control attenuator is composed of a digital potentiometer and an operational amplifier. The software processing block diagram of the B code alternating current signal to the direct current signal is shown in figures 4 and 5, firstly, the input alternating current signal is conditioned, whether a sampling value exceeds a set maximum threshold is judged through AD data sampled in an FPGA, and if the sampling value exceeds the set maximum threshold, a numerical control attenuator is controlled to increase attenuation until the amplitude requirement is met; if the peak value is too small, controlling the numerical control attenuator to reduce the attenuation until the amplitude meets the requirement or the attenuation reaches the minimum value, so that the AD sampling value is always in the optimal value range; then, the adjusted sampling value is operated to obtain zero-position voltage and a high-low level decision threshold, so that the zero-crossing point and the peak position of the input signal can be estimated according to the zero-position voltage, the sampled B alternating current signal can be converted into a B direct current signal at the peak moment according to the decision threshold, whether the polarity of the input signal is correct or not can be judged according to the sampling value at the peak position, if the polarities are not consistent, the obtained B code direct current signal is reversed, and the subsequent processing of the signal when the signal reaches the point is consistent with the processing of an external input direct current signal; a hardware processing block diagram of the direct current B code signal is shown in fig. 4, and the direct current B code signal is sent to the FPGA for processing after passing through a protection circuit and level conversion; as shown in fig. 3, a hardware processing block diagram of the dc signal is that, firstly, high-level timing is performed on the input dc signal to obtain redundant counts of 2ms, 5ms, and 8ms, and at the same time, judgment and verification are performed on 8ms of the whole second time, if the result is positive, the input signal is indicated, and the analyzed pulse per second is corrected by the delay parameter, so that an accurate pulse per second signal is obtained. And simultaneously writing the count obtained by timing into an FIFO space of the FPGA, and informing the ARM to read and analyze. And the ARM completes the analysis of the information layer according to the standard protocol of the B code and sends the time data to the display control module and the external interface.
The switch module mainly comprises a network expansion chip and a protection circuit, and is required to realize 5 paths of Ethernet interfaces on the back panel and 3 paths of Ethernet interfaces on the front panel. The design of the module selects the IP175DLF chip of the Jiuyang electronic to realize the function of a plurality of paths of Ethernet interfaces, the IP175DLF chip is an Ethernet switch with 5 ports of the Jiuyang electronic and supports the working temperature range of minus 40 to 85 ℃, 2 IP175DLF chips are used in the module, the function of 8 paths of Ethernet interfaces at most is realized through the interconnection of network interfaces, wherein the 5 paths of network interfaces are interconnected with each internal functional module through a backboard module, and 3 network interfaces are designed on a front panel of the switch module and are used for finishing the data communication with external equipment. Each Ethernet interface is isolated and driven through an HX5400NL transformer, all Ethernet interfaces use protection devices for electrostatic protection and voltage-withstanding protection, and considering that the Ethernet interfaces are easily affected by lightning surge and residual voltage after primary protection of ceramic discharge tubes, GDT is adopted to conduct common-mode surge protection at the front end of the transformer, and a TVS tube which is low in junction capacitance, fast in reaction time and capable of protecting static electricity is selected to absorb differential-mode energy.
The display control module comprises an information processing module and a display module, the information processing module is an STM32F407ARM chip, the display module is a low-temperature liquid crystal screen, the ARM chip receives the state of each internal module and information to be displayed, such as B code time data and the like, and then the display of various data is completed according to an interface protocol of the liquid crystal screen; meanwhile, some state indications needing visual representation are completed by an indicator lamp on an IO port driving panel of the ARM.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.
Claims (2)
1. An AC/DC B code self-adaptive analysis method is characterized in that: the AC/DC B code self-adaptive analysis device is used for analyzing, and comprises a power module, a B code processing module, a back panel module and a display control module;
the power module supplies power to the modules through the backboard module, the power module comprises a power protection circuit, a direct current filter, a first switch control circuit, a first DC/DC module and a second switch control circuit which are connected in sequence, a temperature control circuit is arranged between the first DC/DC module and the second switch control circuit of the power module, the temperature control circuit comprises a thermistor, a voltage comparator and an MOS (metal oxide semiconductor) tube, and when the ambient temperature reaches 75-85 ℃, the voltage output is turned off through the second switch control circuit, so that the equipment is prevented from being damaged during high-temperature work;
the B code processing module is connected with the display control module through the backboard module and comprises a transformer, a numerical control attenuator, an AD acquisition chip and an AC-DC conversion circuit which are sequentially connected, the AC-DC conversion circuit is connected with the FPGA processing circuit, the FPGA processing circuit is connected with the ARM processing circuit, the input end of the FPGA processing circuit is connected with the level conversion circuit, the output end of the FPGA processing circuit is connected with the numerical control attenuator, and the input end of the level conversion circuit is connected with the protection circuit;
the backboard module interconnects all the modules through onboard high-speed sockets;
the display control module is connected with the B code processing module through the backboard module and comprises an information processing module and a display module, the information processing module is used for receiving the state of each module and information required to be displayed, and the display module is used for displaying the B code analysis time and the state information received by the information processing module;
the AC/DC B code self-adaptive analysis device also comprises an exchanger module, wherein the exchanger module comprises 8 network ports for expansion, 5 network ports of the exchanger module are interconnected with each module through the backboard module, and the other 3 network ports are used for completing data communication with external equipment;
the output end of a second control circuit of the power supply module is provided with a second DC/DC module and a third DC/DC module for subsequently expanding the output function of the alternating current B code;
the display module is a low-temperature serial port liquid crystal display module;
the AC/DC B code self-adaptive analysis device comprises the following specific steps of:
step one, high level time statistics: performing high-level timing on an input direct-current signal to obtain redundant counts of 2ms, 5ms and 8 ms;
step two, verifying the whole second: judging and verifying 8ms of the whole second moment, if the judgment result shows that the input signal is valid, carrying out delay parameter correction on the analyzed second pulse so as to obtain a correct second pulse signal, writing a count obtained by timing into an FIFO (first in first out) space of the FPGA (field programmable gate array) processing circuit for data caching, and informing the ARM processing circuit to carry out reading analysis;
step three, the ARM processing circuit completes the analysis of the information layer according to the standard protocol of the B code and sends the time data to the display control module and the external equipment through the backboard module;
the input direct current signal is a direct current signal generated by alternating current B code input, and the specific process is as follows: the AC B code input from the outside enters a transformer for isolation and then enters a numerical control attenuator for amplitude adaptive control; then, the AC signal data is acquired by an AD acquisition chip; the alternating current signal is subjected to signal conditioning through a signal conditioning circuit, whether a sampling value exceeds a set maximum threshold or not is judged through AD data sampled in an FPGA processing circuit, and if the sampling value exceeds the set maximum threshold, the numerical control attenuator is controlled to increase attenuation until the amplitude requirement is met; if the peak value is too small, controlling the numerical control attenuator to reduce the attenuation until the amplitude meets the requirement or the attenuation reaches the minimum value, so that the AD sampling value is always in the optimal value range; and then, calculating the adjusted sampling value to obtain a zero-position voltage and a high-low level decision threshold, estimating a zero crossing point and a peak position of the input signal according to the zero-position voltage, converting the sampled alternating-current B code signal into a direct-current B code signal at the peak moment according to the decision threshold, judging whether the polarity of the input signal is correct or not according to the sampling value at the peak position, and reversing the obtained direct-current B code signal if the polarities are inconsistent.
2. The adaptive analysis method for AC/DC B codes according to claim 1, characterized in that: the input direct current signal is a direct current signal generated by direct current B code input, and the specific process is as follows: the direct current B code signal input from the outside is sent to the FPGA processing circuit for processing after passing through the protection circuit and the level conversion circuit.
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