CN103138767A

CN103138767A - Decoder of inter range instrumentation group (IRIG)-B code

Info

Publication number: CN103138767A
Application number: CN2013100136952A
Authority: CN
Inventors: 贺惠农; 朱军伟; 秦巍; 陈柊
Original assignee: HANGZHOU VICON TECHNOLOGY Co Ltd
Current assignee: HANGZHOU VICON TECHNOLOGY Co Ltd
Priority date: 2013-01-14
Filing date: 2013-01-14
Publication date: 2013-06-05

Abstract

The invention belongs to the technical field of electronic communication and relates to a decoder, in particular to the decoder of an inter range instrumentation group (IRIG) code. The decoder of the IRIG-B code comprises a direct current (DC) code decoding module, an alternating current (AC) code decoding module and a field programmable gate array (FPGA) chip, wherein the DC code decoding module comprises a DC code interface and a level conversion circuit. A DC code is input to the level conversion module through the DC code interface and input to the FPGA chip to be decoded after conversion. The AC code decoding module comprises a sampling clock generation module, a signal sampling processing module and an isolation transformer, wherein the isolation transformer can achieve isolated protection of an input AC code. The decoder of the IRIG-B code has the advantages that the IRIG-B (AC) code and the IRIG-B (DC) code can be decoded simultaneously, and a unit of a micro controller unit and the FPGA are selected to conduct decoding analysis and calculation in order to solve the problems of the speed and the time precision of decoding signals and reduce decoding errors.

Description

A kind of IRIG-B code decoder

Technical field

The invention belongs to the electronic communication field, refer to especially a kind of decoder, especially a kind of IRIG-B code decoder.

Background technology

IRIG(Inter-Range Instrumentation Group target range instrument group) be the U.S. RCC(Range Commanders Council target range commandant committee) affiliated institutions, can be used for time system master station to the time, correction time, also can be by timing code to the timing equipment precision time service, the IRIG standard that it is formulated becomes general international standard.The serial timing code standard code of IRIG A, B, C, D, E, G, seven kinds of forms of H (the C code is cancelled), wherein, the B IRIG-B format time code due to the time frame period be 1 second, the demand that is fit to people, obtained using the most widely, the IRIG timing code that most occasions are used is all the B form type code, namely the IRIG-B code.Exchange because the IRIG-B code is divided into again AC() code and DC(direct current) code, in existing products scheme, a lot of designs can only decode AC code or DC code, and the single-chip microcomputer that only adopts that has in design decodes, and is prone to like this situation that code error is even made mistakes greatly of separating.Generally in decoding AC code, all adopt the device modules such as zero passage, amplification and sampling.Because the amplitude of AC code input be not fix (0.5～10Vp-p), fix when the multiplication factor of amplifier, will certainly cause the scope of AC input signal to limit to some extent.The method of sampling of the employing routine that has in sampler is carried out sampling analysis to whole AC signal, cause the data analysis amount large, affect the processor operating efficiency.Along with client's requirement is more and more higher, only design solution AC code or DC code can not satisfy the demands, should adopt two kinds of codes can separate simultaneously.In decoding design, adopt FPGA to combine deal with data with single-chip microcomputer, can reach efficiently, accurately, purpose easily.In addition, if AC code input signal amplitude range limits to some extent, also be difficult to satisfy the client, adopt the automatic gain to control, can effectively solve the amplitude problem.

Summary of the invention

The objective of the invention is to have the problems referred to above for existing technology, proposed a kind of a large amount of data analysis that reduces, raise the efficiency, can reach efficient, accurate IRIG-B code decoder.

For achieving the above object, the present invention has adopted following technical proposal: a kind of IRIG-B code decoder comprises DC code decoder module, AC code decoder module, fpga chip; DC code decoder module comprises: DC code interface, level shifting circuit.The DC code is input to level shifting circuit by DC code interface, is input to fpga chip after changing and decodes; AC code decoder module comprises: sampling clock generation module, signal sampling processing module and can realize the AC code isolating transformer that carries out insulation blocking to input; The sampling clock generation module comprises zero passage and bleeder circuit, fpga chip, and the signal of isolating transformer output produces sampled clock signal through the sampling clock generation module, as the sampling clock of single-chip microcomputer; The signal sampling processing module comprises absolute value and bleeder circuit, follower, automatic gain control, analog switch, single-chip microcomputer, signal after the isolating transformer isolation is divided into two-way by absolute value and bleeder circuit, and one the tunnel directly sends into single-chip microcomputer detects voltage peak; Another road is carried out automatic gain after by follower and is controlled, and the signal of output is input to single-chip microcomputer and samples after the analog switch protection.

In above-mentioned a kind of IRIG-B code decoder, when checking signal, described single-chip microcomputer can with uncomfortable signal feedback to the automatic gain module, regulate magnification ratio to be suitable for the specified input range of single-chip microcomputer.

Compared with prior art, the invention has the advantages that: can decode to IRIG-B (AC) code and IRIG-B (DC) code simultaneously, adopt SCM﹠FPGA to unite and carried out Decoding Analysis and calculating, improved the generation of speed, time accuracy and the minimizing decoding error of decoded signal.Unrestricted to IRIG-B (AC) code input voltage range in addition; a high amplitude detection and automatic gain control circuit have been adopted; voltage to signal automatically adjusts; signal voltage is reached can be surveyed in scope; and externally IRIG-B code input interface and single-chip microcomputer signal input interface have adopted respectively the protective circuits such as isolation and analog switch, have effectively guaranteed the reliability of circuit.

Description of drawings

In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, the below will do to introduce simply to the accompanying drawing of required use in embodiment or description of the Prior Art, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skills, under the prerequisite of not paying creative work, can also obtain according to these accompanying drawings other accompanying drawing.

Fig. 1 is DC and AC code decoding process figure;

Fig. 2 is DC code decoding process figure;

Fig. 3 is AC code decoding process figure;

Fig. 4 is zero passage comparison circuit schematic diagram;

Fig. 5 is absolute value and bleeder circuit schematic diagram.

Fig. 6 is the ACC oscillogram;

Fig. 7 is the automatic gain control principle drawing;

Embodiment

Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is clearly and completely described, obviously, described embodiment is only the present invention's part embodiment, rather than whole embodiment.Based on the embodiment in the present invention, those of ordinary skills belong to the scope of protection of the invention not making the every other embodiment that obtains under the creative work prerequisite.

As shown in Figure 1, 2, a kind of IRIG-B code decoder comprises DC code decoder module, AC code decoder module, fpga chip; DC code decoder module comprises: DC code interface, level shifting circuit.The DC code is input to level shifting circuit by DC code interface, is input to fpga chip after changing and decodes; AC code decoder module comprises: sampling clock generation module, signal sampling processing module and can realize the AC code isolating transformer that carries out insulation blocking to input.

The sampling clock generation module comprises zero passage and bleeder circuit, fpga chip, and the signal of isolating transformer output produces sampled clock signal through the sampling clock generation module, as the sampling clock of single-chip microcomputer; The signal sampling processing module comprises absolute value and bleeder circuit, follower, automatic gain control, analog switch, single-chip microcomputer, signal after the isolating transformer isolation is divided into two-way by absolute value and bleeder circuit, and one the tunnel directly sends into single-chip microcomputer detects voltage peak; Another road is carried out automatic gain after by follower and is controlled, and the signal of output is input to single-chip microcomputer and samples after the analog switch protection.

As shown in Figure 3 and Figure 4; IRIG-B alternating current code (AC) is after standard interface; carry out circuit protection by isolating transformer; signal after isolation is processed through zero passage and bleeder circuit; generation frequency 1kHz, amplitude are the pulse signal A1KC of 3V; the A1KC pulse signal is delivered to the FPGA module, and the FPGA module is carried out 1 frequency multiplication and is obtained the pulse signal that frequency is 2kHz, is that the pulse signal of 2kHz is as the sampling clock of single-chip microcomputer with this frequency.As shown in Figure 5, the signal after simultaneously isolating transformer isolation obtains signal ACC after processing through absolute value and bleeder circuit, the oscillogram of ACC signal as shown in Figure 6, the ACC signal will be divided into two-way, one road ACC signal is directly sent into single-chip microcomputer detection voltage peak; As shown in Figure 7, another road ACC signal carries out automatic gain after by follower and controls, being input to single-chip microcomputer after the signal ACC_1 of output protects by analog switch samples, wherein absolute value and bleeder circuit are that negative half axis signal with the AC code becomes positive axis signal and dividing potential drop, thereby realize reading the AC code; In addition, when checking signal, single-chip microcomputer can with uncomfortable signal feedback to the automatic gain module, regulate magnification ratio to be suitable for the specified input range of single-chip microcomputer.

The above is only preferred embodiment of the present invention, and is in order to limit the present invention, within the spirit and principles in the present invention not all, any modification of doing, is equal to replacement, improvement etc., within all should being included in protection scope of the present invention.

Claims

1. an IRIG-B code decoder, comprise DC code decoder module, AC code decoder module, fpga chip; DC code decoder module comprises: DC code interface, level shifting circuit; The DC code is input to level shifting circuit by DC code interface, is input to fpga chip after changing and decodes; AC code decoder module comprises: sampling clock generation module, signal sampling processing module and can realize the AC code isolating transformer that carries out insulation blocking to input; The sampling clock generation module comprises zero passage and bleeder circuit, fpga chip, and the signal of isolating transformer output produces sampled clock signal through the sampling clock generation module, as the sampling clock of single-chip microcomputer; The signal sampling processing module comprises absolute value and bleeder circuit, follower, automatic gain control, analog switch, single-chip microcomputer, signal after the isolating transformer isolation is divided into two-way by absolute value and bleeder circuit, and one the tunnel directly sends into single-chip microcomputer detects voltage peak; Another road is carried out automatic gain after by follower and is controlled, and the signal of output is input to single-chip microcomputer and samples after the analog switch protection.

2. a kind of IRIG-B code decoder described according to claim 1, is characterized in that, can with uncomfortable signal feedback to the automatic gain module, regulate magnification ratio to be suitable for the specified input range of single-chip microcomputer when described single-chip microcomputer checks signal.