CN203057114U - IRIG-B code decoder - Google Patents

IRIG-B code decoder Download PDF

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Publication number
CN203057114U
CN203057114U CN 201320018406 CN201320018406U CN203057114U CN 203057114 U CN203057114 U CN 203057114U CN 201320018406 CN201320018406 CN 201320018406 CN 201320018406 U CN201320018406 U CN 201320018406U CN 203057114 U CN203057114 U CN 203057114U
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CN
China
Prior art keywords
sign indicating
indicating number
signal
code
irig
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Expired - Fee Related
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CN 201320018406
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Chinese (zh)
Inventor
贺惠农
朱军伟
秦巍
陈柊
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HANGZHOU VICON TECHNOLOGY Co Ltd
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HANGZHOU VICON TECHNOLOGY Co Ltd
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Priority to CN 201320018406 priority Critical patent/CN203057114U/en
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Publication of CN203057114U publication Critical patent/CN203057114U/en
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Abstract

The utility model belongs to the technical field of electronic communication, relates to a decoder, in particular to an IRIG-B code decoder. The IRIG-B code decoder comprises a DC code decoding module, an AC code decoding module, and an FPGA chip; wherein the DC code decoding module includes a DC code interface and a level conversion circuit. The DC code is input to a level conversion module through the DC code interface and converted and then input to the FPGA chip to be decoded; the AC code decoding module comprises a sample clock generation module, a signal sample process module and an isolation transformer for performing the isolation protection of the input AC code. The IRIG-B code decoder has the following advantages that the IRIG-B(AC) code and the IRIG-B(DC) code are simultaneously decoded, in order to solve the speed of the decoded signal and the time accuracy and reduce the decoding error, a single-chip microcomputer and an FPGA are combined to perform the decoding analysis and calculation.

Description

A kind of IRIG-B sign indicating number decoder
Technical field
The utility model belongs to the electronic communication field, refers to a kind of decoder especially, especially a kind of IRIG-B sign indicating number decoder.
Background technology
IRIG(Inter-Range Instrumentation Group target range instrument group) be the U.S. RCC(Range Commanders Council target range commandant committee) affiliated institutions, can be used for time system master station to the time, correction time, also can be by timing code to the accurate time service of timing equipment, the IRIG standard that it is formulated becomes general international standard.The serial timing code standard code of IRIG A, B, C, D, E, G, seven kinds of forms of H (the C sign indicating number is cancelled), wherein, the B IRIG-B format time code since the time frame period be 1 second, the demand that is fit to people, obtained using the most widely, the IRIG timing code that most occasions are used all is the B form type code, just the IRIG-B sign indicating number.Exchange because the IRIG-B sign indicating number is divided into AC(again) sign indicating number and DC(direct current) sign indicating number, in the existing products scheme, a lot of designs can only decode AC sign indicating number or DC sign indicating number, and the single-chip microcomputer that only adopts that has in design decodes, and is prone to the situation that code error is big even make mistakes of separating like this.Generally in decoding AC sign indicating number, all adopt device modules such as zero passage, amplification and sampling.Because the amplitude of AC sign indicating number input be not fix (0.5~10Vp-p), fix when the multiplication factor of amplifier, will certainly cause the scope of AC input signal to limit to some extent.The method of sampling of the employing routine that has in sampler is carried out sampling analysis to whole AC signal, cause the data analysis amount big, influence the processor operating efficiency.Along with requirement of client is more and more higher, only design solution AC sign indicating number or DC sign indicating number can not satisfy the demands, should adopt two kinds of sign indicating numbers can separate simultaneously.In decoding design, adopt FPGA to combine deal with data with single-chip microcomputer, can reach efficiently, accurately, purpose easily.In addition, if AC sign indicating number input signal amplitude range limits to some extent, also be difficult to satisfy the client, adopt automatic gain control, can effectively solve the amplitude problem.
The utility model content
The purpose of this utility model is to have the problems referred to above at existing technology, has proposed the analysis of a kind of minimizing lot of data, raises the efficiency, and can reach efficient, accurate IRIG-B sign indicating number decoder.
For achieving the above object, the utility model has adopted following technical proposal: a kind of IRIG-B sign indicating number decoder comprises DC sign indicating number decoder module, AC sign indicating number decoder module, fpga chip; DC sign indicating number decoder module comprises: DC sign indicating number interface, level shifting circuit.The DC sign indicating number is input to level shifting circuit by DC sign indicating number interface, is input to fpga chip after changing and decodes; AC sign indicating number decoder module comprises: sampling clock generation module, signal sampling processing module and can realize the AC sign indicating number isolating transformer that carries out insulation blocking to input; The sampling clock generation module comprises zero passage and bleeder circuit, fpga chip, and the signal of isolating transformer output produces sampled clock signal through the sampling clock generation module, as the sampling clock of single-chip microcomputer; The signal sampling processing module comprises absolute value and bleeder circuit, follower, automatic gain control, analog switch, single-chip microcomputer, signal after isolating transformer is isolated is divided into two-way by absolute value and bleeder circuit, and one the tunnel directly sends into single-chip microcomputer detects voltage peak; Automatic gain control is carried out on another road after by follower, and the signal of output is input to single-chip microcomputer and samples after the analog switch protection.
In above-mentioned a kind of IRIG-B sign indicating number decoder, when checking signal, described single-chip microcomputer can give the automatic gain module with uncomfortable signal feedback, regulate magnification ratio to be suitable for the specified input range of single-chip microcomputer.
Compared with prior art, advantage of the present utility model is: can decode to IRIG-B (AC) sign indicating number and IRIG-B (DC) sign indicating number simultaneously, adopted single-chip microcomputer and FPGA to unite to decode and analyzed and calculate, improved speed, the time accuracy of decoded signal and reduced the generation of decoding error.Unrestricted to IRIG-B (AC) sign indicating number input voltage range in addition; adopted a high amplitude to detect and automatic gain control circuit; voltage of signals is automatically adjusted; signal voltage is reached can be surveyed in the scope; and externally IRIG-B sign indicating number input interface and single-chip microcomputer signal input interface have adopted protective circuits such as isolation and analog switch respectively, have effectively guaranteed the reliability of circuit.
Description of drawings
In order to be illustrated more clearly in the utility model embodiment or technical scheme of the prior art, to do to introduce simply to the accompanying drawing of required use in embodiment or the description of the Prior Art below, apparently, accompanying drawing in describing below only is embodiment more of the present utility model, for those of ordinary skills, under the prerequisite of not paying creative work, can also obtain other accompanying drawing according to these accompanying drawings.
Fig. 1 is DC and AC sign indicating number decoding process figure;
Fig. 2 is DC sign indicating number decoding process figure;
Fig. 3 is AC sign indicating number decoding process figure;
Fig. 4 is zero passage comparison circuit schematic diagram;
Fig. 5 is absolute value and bleeder circuit schematic diagram.
Fig. 6 is the ACC oscillogram;
Fig. 7 is automatic gain control principle figure;
Embodiment
Below in conjunction with the accompanying drawing among the utility model embodiment, the technical scheme among the utility model embodiment is clearly and completely described, obviously, described embodiment only is the utility model part embodiment, rather than whole embodiment.Based on the embodiment in the utility model, those of ordinary skills are not making the every other embodiment that obtains under the creative work prerequisite, all belong to the scope of the utility model protection.
As shown in Figure 1, 2, a kind of IRIG-B sign indicating number decoder comprises DC sign indicating number decoder module, AC sign indicating number decoder module, fpga chip; DC sign indicating number decoder module comprises: DC sign indicating number interface, level shifting circuit.The DC sign indicating number is input to level shifting circuit by DC sign indicating number interface, is input to fpga chip after changing and decodes; AC sign indicating number decoder module comprises: sampling clock generation module, signal sampling processing module and can realize the AC sign indicating number isolating transformer that carries out insulation blocking to input.
The sampling clock generation module comprises zero passage and bleeder circuit, fpga chip, and the signal of isolating transformer output produces sampled clock signal through the sampling clock generation module, as the sampling clock of single-chip microcomputer; The signal sampling processing module comprises absolute value and bleeder circuit, follower, automatic gain control, analog switch, single-chip microcomputer, signal after isolating transformer is isolated is divided into two-way by absolute value and bleeder circuit, and one the tunnel directly sends into single-chip microcomputer detects voltage peak; Automatic gain control is carried out on another road after by follower, and the signal of output is input to single-chip microcomputer and samples after the analog switch protection.
As shown in Figure 3 and Figure 4; IRIG-B alternating current code (AC) is behind standard interface; carry out circuit protection by isolating transformer; signal after the isolation is handled through zero passage and bleeder circuit; generation frequency 1kHz, amplitude are the pulse signal A1KC of 3V; the A1KC pulse signal is delivered to the FPGA module, and the FPGA module is carried out 1 frequency multiplication and is obtained the pulse signal that frequency is 2kHz, is that the pulse signal of 2kHz is as the sampling clock of single-chip microcomputer with this frequency.As shown in Figure 5, the signal after simultaneously isolating transformer is isolated obtains signal ACC after handling through absolute value and bleeder circuit, the oscillogram of ACC signal as shown in Figure 6, the ACC signal will be divided into two-way, one road ACC signal is directly sent into single-chip microcomputer detection voltage peak; As shown in Figure 7, another road ACC signal carries out automatic gain control after by follower, being input to single-chip microcomputer after the signal ACC_1 of output protects by analog switch samples, wherein absolute value and bleeder circuit are that negative semiaxis signal with the AC sign indicating number becomes positive axis signal and dividing potential drop, thereby realize reading the AC sign indicating number; In addition, can give the automatic gain module with uncomfortable signal feedback when single-chip microcomputer checks signal, regulate magnification ratio to be suitable for the specified input range of single-chip microcomputer.
The above only is preferred embodiment of the present utility model; not in order to limit the utility model; all within spirit of the present utility model and principle, any modification of doing, be equal to replacement, improvement etc., all should be included within the protection range of the present utility model.

Claims (2)

1. an IRIG-B sign indicating number decoder comprises DC sign indicating number decoder module, AC sign indicating number decoder module, fpga chip; DC sign indicating number decoder module comprises: DC sign indicating number interface, level shifting circuit; The DC sign indicating number is input to level shifting circuit by DC sign indicating number interface, is input to fpga chip after changing and decodes; AC sign indicating number decoder module comprises: sampling clock generation module, signal sampling processing module and can realize the AC sign indicating number isolating transformer that carries out insulation blocking to input; The sampling clock generation module comprises zero passage and bleeder circuit, fpga chip, and the signal of isolating transformer output produces sampled clock signal through the sampling clock generation module, as the sampling clock of single-chip microcomputer; The signal sampling processing module comprises absolute value and bleeder circuit, follower, automatic gain control, analog switch, single-chip microcomputer, signal after isolating transformer is isolated is divided into two-way by absolute value and bleeder circuit, and one the tunnel directly sends into single-chip microcomputer detects voltage peak; Automatic gain control is carried out on another road after by follower, and the signal of output is input to single-chip microcomputer and samples after the analog switch protection.
2. according to a kind of IRIG-B sign indicating number decoder described in the claim 1, it is characterized in that, can give the automatic gain module with uncomfortable signal feedback when described single-chip microcomputer checks signal, regulate magnification ratio to be suitable for the specified input range of single-chip microcomputer.
CN 201320018406 2013-01-14 2013-01-14 IRIG-B code decoder Expired - Fee Related CN203057114U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN 201320018406 CN203057114U (en) 2013-01-14 2013-01-14 IRIG-B code decoder

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Application Number Priority Date Filing Date Title
CN 201320018406 CN203057114U (en) 2013-01-14 2013-01-14 IRIG-B code decoder

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104639174A (en) * 2013-11-06 2015-05-20 施耐德电器工业公司 Unified low-temperature-drift conditioning circuit for IRIG-B code source signals

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104639174A (en) * 2013-11-06 2015-05-20 施耐德电器工业公司 Unified low-temperature-drift conditioning circuit for IRIG-B code source signals
CN104639174B (en) * 2013-11-06 2018-05-25 施耐德电器工业公司 For the modulate circuit of the unified Low Drift Temperature of IRIG-B code source signal

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CF01 Termination of patent right due to non-payment of annual fee
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20130710

Termination date: 20190114