CN108566104A - A kind of synchronous commutating control circuit - Google Patents
A kind of synchronous commutating control circuit Download PDFInfo
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- CN108566104A CN108566104A CN201810427388.1A CN201810427388A CN108566104A CN 108566104 A CN108566104 A CN 108566104A CN 201810427388 A CN201810427388 A CN 201810427388A CN 108566104 A CN108566104 A CN 108566104A
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/02—Conversion of ac power input into dc power output without possibility of reversal
- H02M7/04—Conversion of ac power input into dc power output without possibility of reversal by static converters
- H02M7/12—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M7/21—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M7/217—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0048—Circuits or arrangements for reducing losses
- H02M1/0054—Transistor switching losses
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Rectifiers (AREA)
Abstract
A kind of synchronous commutating control circuit, belongs to electronic circuit technology.The present invention is switched on and off rectifying tube by detecting the drain-source pressure difference of rectifying tube, including voltage detection module, synchronous rectification Logic control module and drive module, voltage detection module is used to detect the drain-source pressure difference of rectifying tube, synchronous rectification Logic control module is used to control the minimum turn-on time of rectifying tube, it avoids shaking after opening rectifying tube, drive module is for providing gate driving.Type of drive provided by the invention is simple and reliable, and the power consumption of rectifier can be greatly reduced, and reduces the temperature of rectifier bridge, lifting system reliability；Lower conduction loss can be realized simultaneously, improved generator whole efficiency, played the role of energy saving, clean environment firendly.
Description
Technical field
The invention belongs to electronic circuit technologies, particularly relate to a kind of control of the rectification circuit for electric power generation
Circuit.
Background technology
Generation current machine rectifier mainly uses silicon diode as rectifier cell, and silicon diode forward voltage drop is about
0.3~1V, on-state power consumption is very big when high current.It is a large amount of universal with automobile, by silicon diode commutating zone Lai power consumption do not allow
Ignore.
Synchronous rectification (Synchronous Rectification, SR) uses power metal-oxide of low-voltage
Semiconductor field effect transistor (Power MOSFET) can be very good to drop as rectifying device using its raceway groove on state resistance
The overall power of low rectifier module.And the main difficulty of synchronous rectification is used to be that the grid of its rectifying tube controls.
The driving of rectifying tube mainly uses pulse width modulation (PWM) mode, and realization is complex, needs to establish space arrow
Mathematical model is measured, complicated transformation is carried out and solves, therefore a large amount of logical process is needed on circuit composition, increases technology hardly possible
Degree and cost；And automobile current generator is influenced by automobile rotational speed, further increases the difficulty of control algolithm, application cost is too high, unfavorable
In the universal of synchronous rectification.
Invention content
The purpose of the present invention, aiming at asking in technical difficulty and cost present in current synchronous rectification
Topic, proposes a kind of control circuit, the rectification circuit for controlling electric power generation is simple in structure, and circuit power consumption is low, reliability is high.
Technical solution of the present invention is：
A kind of synchronous commutating control circuit, for controlling the rectifying tube in synchronous rectification system, including voltage detection module,
Synchronous rectification Logic control module and drive module,
The voltage detection module is used to detect the drain-source voltage of rectifying tube and generates first detection signal and the second detection
Signal；
The synchronous rectification Logic control module includes minimum turn-on time generation module, periodic wakeup module, minimum
Blanking time generation module, first or door T2With the 4th phase inverter T3,
The minimum turn-on time generation module includes the first d type flip flop D1, the second phase inverter G1, second or door G2, first
NAND gate G3With the first rise edge delay module, the second phase inverter G1Input terminal connect the first NAND gate G3First input end
With first or door T2Output end, output end connect the first d type flip flop D1Clock end；First or door T2First input end
Connect the first detection signal；First d type flip flop D1Data input pin connect enable signal EN, reset terminal connection second
Or door G2Output end, Q output connects the input terminal of the first rise edge delay module, Q non-output ends connection first with
NOT gate G3The second input terminal；Second or door G2First input end connection enable signal inversion signal ENB, the second input
The 4th phase inverter T of end connection3Output end, third input terminal connect the first rise edge delay module output end；4th is anti-
Phase device T3Input terminal connection it is described second detection signal；First NAND gate G3Output end produced as the minimum turn-on time
The output end of raw module；
The periodic wakeup module includes the second d type flip flop D2, the first NAND gate G4, third or door G5, first with door G6
With the second rise edge delay module,
Second d type flip flop D2Clock end connect first or door T2Output end, data input pin connects third or door G5
The second input terminal and the minimum turn-on time generation module in the first d type flip flop D1Q output, reset terminal connection the
One NAND gate G4Output end, Q output connect first or door T2The second input terminal, Q non-output ends connection third or door
G5First input end；First and door G6First input end connection third or door G5Output end and called out as the periodicity
The output end for module of waking up, the second input terminal connect the first detection signal, and output end connects the second rise edge delay mould
The input terminal of block；First NAND gate G4First input end connect the second rise edge delay module output end, second input
End connects the inversion signal ENB of the enable signal, and third input terminal connects the 4th phase inverter T3Output end；
The minimum blanking time generation module includes third d type flip flop D3, third rise edge delay module, second and door
G7, the 4th or door G8With the 5th or door G9,
Second and door G7First input end connect first or door T2Output end, the second input terminal connects the minimum
First d type flip flop D in turn-on time generation module1The non-output ends of Q, third input terminal connects the periodic wakeup module
In the second d type flip flop D2The non-output ends of Q, output end connects third d type flip flop D3Clock end and the 5th or door G9First
Input terminal；Third d type flip flop D3Data input pin connect enable signal EN, reset terminal connect the 4th or door G8Output end,
Its Q output connects the input terminal and the 5th or door G of third rise edge delay module9The second input terminal；5th or door G9It is defeated
Output end of the outlet as the minimum blanking time generation module；4th or door G8First input end connect third rising edge
The output end of Postponement module, the second input terminal connect the second d type flip flop D in the periodic wakeup module2Q output,
Its third input terminal connects the 4th phase inverter T3Output end；
The output end of minimum turn-on time generation module, the second input terminal described in the first input end of the drive module
The output end of the periodic wakeup module is connected, third input terminal connects the output of the minimum blanking time generation module
End, output end connect the grid of the rectifying tube.
Specifically, the voltage detection module includes first comparator Comp1, the second comparator Comp2, first voltage source
And the second voltage source, the in-phase input end of first comparator Comp1 connect the drain electrode of the rectifying tube, inverting input connection
The forward end of first voltage source, output end export the first detection signal；The in-phase input end of second comparator Comp2 connects
The forward end of the second voltage source is connect, inverting input connects the drain electrode of the rectifying tube, output end output second inspection
Survey signal；First voltage source connects the source electrode of the rectifying tube with the negative end of the second voltage source.
Specifically, the first comparator Comp1 is hysteresis comparator.
Specifically, the first rise edge delay module, the second rise edge delay module and third rise edge delay module
Structure having the same, the first rise edge delay module include the first current source I1, the first capacitance C1, the first metal-oxide-semiconductor M1、
Second nor gate T5, the second NAND gate T6With the first Schmidt trigger T7, the second NAND gate T6First input end be used as described in
The input terminal of first rise edge delay module, the second input terminal connect the enable signal EN, and output end connects the first MOS
Pipe M1Grid；First capacitance C1One end connect the first metal-oxide-semiconductor M1Drain electrode, the first Schmidt trigger T7Input terminal and
First current source I1Negative end, the other end connect the first metal-oxide-semiconductor M1Source electrode and ground connection；First current source I1Forward end
Connect supply voltage；Second nor gate T5Input terminal connect the first Schmidt trigger T7Output end, output end is as institute
State the output end of the first rise edge delay module.
Specifically, the synchronous rectification Logic control module further includes the inversion signal for generating the enable signal EN
The input terminal of the first phase inverter T1, the first phase inverter T1 connect the enable signal EN, output end exports the enabled letter
Number inversion signal ENB.
Specifically, the drive module includes third and door T4, the second nor gate T5 and driving output stage, third and door T4
First input end of the first input end as the drive module, the second input terminal connects the output of the second nor gate T5
End, output end connect the input terminal of the driving output stage；The first input end of second nor gate T5 is as the driving mould
Second input terminal of block, third input terminal of second input terminal as the drive module；The driving output stage includes even
Several cascade phase inverters, output end of the output end as the drive module.
Beneficial effects of the present invention are：Control circuit provided by the invention, by detecting the rectification in generator rectifier
The turn-on and turn-off of the drain-source pressure difference control rectifying tube of pipe, can realize that rectifier has lower conduction loss, improve power generation
The whole efficiency of machine, type of drive is simple and reliable, and energy saving, clean environment firendly；Control circuit provided by the invention can simultaneously
The power consumption of rectifier is greatly reduced, the temperature of rectifier bridge is reduced, system reliability is improved.
Description of the drawings
Fig. 1 is a kind of overall structure diagram of synchronous commutating control circuit provided by the invention.
Fig. 2 is a kind of particular circuit configurations schematic diagram of synchronous commutating control circuit provided by the invention in embodiment.
Fig. 3 is the electricity of rise edge delay module in embodiment in a kind of synchronous commutating control circuit provided by the invention
Line structure schematic diagram.
Fig. 4 is a kind of work flow diagram of synchronous commutating control circuit provided by the invention.
Specific implementation mode
In the following with reference to the drawings and specific embodiments, detailed description of the present invention technical solution.
A kind of synchronous commutating control circuit proposed by the present invention, by detecting rectifying tube (i.e. power in circuit of synchronous rectification
MOSFET drain-source pressure difference) is switched on and off rectifying tube.As shown in Figure 1, including voltage detection module, synchronous rectification logic control
Molding block and drive module, voltage detection module are used to detect between the drain electrode and source electrode of rectifying tube (i.e. external power MOSFET)
Voltage difference, synchronous rectification Logic control module are used to control the minimum turn-on time of power MOSFET tube, avoid opening power
It is shaken after MOSFET, drive module is for providing gate driving.
It is a kind of realization circuit form of voltage detection module as depicted in figs. 1 and 2, voltage detection module is whole for detecting
The drain-source voltage of flow tube simultaneously generates first detection signal and the second detection signal, including first comparator Comp1, the second comparator
Comp2, first voltage source and the second voltage source, the drain electrode of the in-phase input end connection rectifying tube of first comparator Comp1 are anti-
Phase input terminal connects the forward end of first voltage source, and output end exports first detection signal；The same phase of second comparator Comp2
Input terminal connects the forward end of the second voltage source, and inverting input connects the drain electrode of rectifying tube, the second inspection of output end output
Survey signal；First voltage source connects the source electrode of rectifying tube with the negative end of the second voltage source.In some embodiments, first comparator
Comp1 is hysteresis comparator, and threshold voltage is turn-on threshold voltage VTH1With shutdown threshold voltage VTH2；Second comparator
Comp2 is voltage comparator, and comparison voltage is reset threshold voltage VTH3.Turn-on threshold voltage VTH1, shutdown threshold voltage VTH2
With reset threshold voltage VTH3It can be set by adjusting the size of voltage source.
Synchronous rectification Logic control module is as shown in Fig. 2, including minimum turn-on time generation module (MOT), periodically call out
Awake module (MCC), minimum blanking time generation module (MFT), first or door T2With the 4th phase inverter T3, minimum turn-on time production
Raw module includes the first d type flip flop D1, the second phase inverter G1, second or door G2, the first NAND gate G3With the first rise edge delay mould
Block, the second phase inverter G1Input terminal connect the first NAND gate G3First input end and first or door T2Output end, output
The first d type flip flop D of end connection1Clock end；First or door T2First input end connect first detection signal；First d type flip flop
D1Data input pin connect enable signal EN, reset terminal connect second or door G2Output end, Q output connection first
The input terminal of rise edge delay module, the non-output ends of Q connect the first NAND gate G3The second input terminal；Second or door G2
One input terminal connects the inversion signal ENB of enable signal, and the second input terminal connects the 4th phase inverter T3Output end, third
Input terminal connects the output end of the first rise edge delay module；4th phase inverter T3Input terminal connection second detection signal；The
One NAND gate G3Output end of the output end as minimum turn-on time generation module.The effect of minimum turn-on time generation module
It is when rectifying tube is connected, which can allow rectifying tube to continue that one end time is connected, when the first rise edge delay module is adopted
When with circuit structure shown in Fig. 3, the length of this turn-on time is by the first rise edge delay mould current source in the block and capacitance
It determines.
Periodic wakeup module includes the second d type flip flop D2, the first NAND gate G4, third or door G5, first with door G6With
Two rise edge delay modules, the second d type flip flop D2Clock end connect first or door T2Output end, data input pin connection
Third or door G5The second input terminal and minimum turn-on time generation module in the first d type flip flop D1Q output, reset terminal
Connect the first NAND gate G4Output end, Q output connect first or door T2The second input terminal, Q non-output ends connection the
Three or door G5First input end；First and door G6First input end connection third or door G5Output end and as periodicity
The output end of wake-up module, the second input terminal connect first detection signal, and output end connects the second rise edge delay module
Input terminal；First NAND gate G4First input end connect the second rise edge delay module output end, the second input terminal
The inversion signal ENB of enable signal is connected, third input terminal connects the 4th phase inverter T3Output end.Periodic wakeup module
Effect be when the grid drive waveforms of rectifying tube are shaken, will driving output shield whithin a period of time, when second rise
When using circuit structure shown in Fig. 3 along Postponement module, the length of this shielding time is in the block by the second rise edge delay mould
Current source and capacitance determine.
Minimum blanking time generation module includes third d type flip flop D3, third rise edge delay module, second with door G7,
Four or door G8With the 5th or door G9, second and door G7First input end connect first or door T2Output end, the second input terminal
First d type flip flop D in the minimum turn-on time generation module of connection1The non-output ends of Q, third input terminal connect periodic wakeup
Second d type flip flop D in module2The non-output ends of Q, output end connects third d type flip flop D3Clock end and the 5th or door G9's
First input end；Third d type flip flop D3Data input pin connect enable signal EN, reset terminal connect the 4th or door G8It is defeated
Outlet, Q output connect the input terminal and the 5th or door G of third rise edge delay module9The second input terminal；5th or door
G9Output end of the output end as minimum blanking time generation module；4th or door G8First input end connection third rise
Along the output end of Postponement module, the second input terminal connects the second d type flip flop D in periodic wakeup module2Q output,
Third input terminal connects the 4th phase inverter T3Output end.The effect of minimum blanking time generation module is when grid driving shutdown is whole
When flow tube, driving output is shielded whithin a period of time, when third rise edge delay module uses circuit structure shown in Fig. 3
When, the length of this shielding time is determined by third rise edge delay mould current source in the block and capacitance.
Wherein enable signal EN is external given, and enable signal EN can be passed through one by the inversion signal ENB of enable signal
A phase inverter obtains, as shown in Fig. 2, synchronous rectification Logic control module further includes the first phase inverter T1, the first phase inverter T1's
Input terminal connects enable signal EN, and output end exports the inversion signal ENB of enable signal.Enable signal EN and enable signal
Inversion signal ENB is used to reset the digital circuit in synchronous rectification Logic control module.
First rise edge delay module, the second rise edge delay module and third rise edge delay module can have identical
Structure, for postponing to rising edge signal, delay time is by the first capacitance C1With the first current source I1It determines, under
Drop edge does not generate delay.It is the one of the first rise edge delay module as shown in Figure 3 below by taking the first rise edge delay module as an example
Kind realizes circuit structure, including the first current source I1, the first capacitance C1, the first metal-oxide-semiconductor M1, the second nor gate T5, the second NAND gate
T6With the first Schmidt trigger T7, the second NAND gate T6Input terminal of the first input end as the first rise edge delay module,
Its second input terminal connects enable signal EN, and output end connects the first metal-oxide-semiconductor M1Grid；First capacitance C1One end connection
First metal-oxide-semiconductor M1Drain electrode, the first Schmidt trigger T7Input terminal and the first current source I1Negative end, the other end connect
Meet the first metal-oxide-semiconductor M1Source electrode and ground connection；First current source I1Forward end connect supply voltage；Second nor gate T5Input
The first Schmidt trigger T of end connection7Output end, output end of the output end as the first rise edge delay module.
The output end of the first input end minimum turn-on time generation module of drive module, the second input terminal connect the period
Property wake-up module output end, the output end of the minimum blanking time generation module of third input terminal connection, output end connection
The grid of rectifying tube.It is a kind of realization circuit structure of drive module, including third and door T4, the second nor gate as shown in Figure 2
First input end of the first input end of T5 and driving output stage, third and door T4 as drive module, the second input terminal connect
Connect the output end of the second nor gate T5, the input terminal of output end connection driving output stage；The first input of second nor gate T5
Hold the second input terminal as drive module, third input terminal of second input terminal as drive module；Drive output stage packet
Include the cascade phase inverter of even number, output end of the output end as drive module.
Fig. 4 is the work flow diagram of the present invention, and a kind of synchronous commutating control circuit provided by the invention is integrated into chip
In, control circuit starts to work and (enters ready mode) after enable signal EN is high (i.e. enable pin is enabled), examines simultaneously
Survey chip power supply voltage VCCIt is whether normal with environment temperature；As supply voltage VCCMeet the second ratio after condition with environment temperature
Waiting for reset signal compared with device Comp2, (i.e. power MOSFET drain-sources pressure difference is more than reset threshold voltage VTH3), when the power detected
The drain-source pressure difference of MOSFET (i.e. rectifying tube) is more than reset threshold voltage VTH3, all logic resets of chip, and trigger minimum blanking
Time generation module, all logics do not work within the blanking time；The second comparator Comp2 detects power after undergoing the blanking time
Whether MOSFET drain-sources pressure difference is in shutdown threshold voltage VTH2With reset threshold voltage VTH3Between, logic exits if meeting condition
Reset, start detect power MOSFET drain-sources pressure difference whether meet turn-on condition (i.e. power MOSFET drain-sources pressure difference be less than unlatching
Threshold voltage VTH1)；When hysteresis comparator Comp1 detects that power MOSFET drain-source pressure differences are less than turn-on threshold voltage VTH1When,
Power MOSFET ON triggers minimum turn-on time MOT limitations；Terminate hysteresis comparator after minimum turn-on time MOT is limited
Comp1 starts to detect whether power MOSFET drain-sources pressure difference is more than closing threshold voltage VTH2If power MOSFET drain-source pressure differences are full
Sufficient condition then closes power MOSFET, then starts waiting for reset signal Reset, when next reset signal Reset comes
It waits and enters above-mentioned flow again.
To sum up, the present invention proposes a kind of control circuit for electric power generation rectification circuit, by detecting rectification circuit
The drain-source pressure difference control power MOSFET ON of middle rectifying tube (i.e. power MOSFET) and shutdown, by detecting power MOSFET's
Whether body diode is connected control power MOSFET, and circuit drives output height, power MOSFET are controlled when body diode is connected
Conducting controls circuit drives when body diode is reverse-biased and exports low, power MOSFET pressure resistances.By by enable signal in the present invention
EN draws high start-up operation so that power MOSFET tube is operated in backward resistance area, is mainly the ditch of MOSFET in switching process
Road resistance flows through high current, realizes lower conduction loss, improves generator whole efficiency, plays energy saving, clean environment firendly
Effect；In addition the power consumption of reorganizer in circuit of synchronous rectification can be greatly reduced in control circuit provided by the invention, reduce
The temperature of rectifier bridge, improves system reliability.
It is understood that the present invention is not limited to the accurate configuration being illustrated above and components.Claims are not being departed from
Protection domain on the basis of, can be to method and structure above the step of sequence, details and operation make various modifications, change and
Optimization.
Claims (6)
1. a kind of synchronous commutating control circuit, for controlling the rectifying tube in synchronous rectification system, which is characterized in that including voltage
Detection module, synchronous rectification Logic control module and drive module,
The voltage detection module is used to detect the drain-source voltage of rectifying tube and generates first detection signal and the second detection signal；
The synchronous rectification Logic control module includes minimum turn-on time generation module, periodic wakeup module, minimum blanking
Time generation module, first or door (T2) and the 4th phase inverter (T3),
The minimum turn-on time generation module includes the first d type flip flop (D1), the second phase inverter (G1), second or door (G2),
One NAND gate (G3) and the first rise edge delay module, the second phase inverter (G1) input terminal connect the first NAND gate (G3)
One input terminal and first or door (T2) output end, output end connect the first d type flip flop (D1) clock end；First or door
(T2) first input end connect the first detection signal；First d type flip flop (D1) data input pin connect enable signal
(EN), reset terminal connects second or door (G2) output end, Q output connect the first rise edge delay module input
End, the non-output ends of Q connect the first NAND gate (G3) the second input terminal；Second or door (G2) first input end connection it is enabled
The inversion signal (ENB) of signal, the second input terminal connect the 4th phase inverter (T3) output end, third input terminal connection the
The output end of one rise edge delay module；4th phase inverter (T3) input terminal connection it is described second detection signal；First with it is non-
Door (G3) output end of the output end as the minimum turn-on time generation module；
The periodic wakeup module includes the second d type flip flop (D2), the first NAND gate (G4), third or door (G5), first and door
(G6) and the second rise edge delay module,
Second d type flip flop (D2) clock end connect first or door (T2) output end, data input pin connects third or door
(G5) the second input terminal and the minimum turn-on time generation module in the first d type flip flop (D1) Q output, reset terminal
Connect the first NAND gate (G4) output end, Q output connect first or door (T2) the second input terminal, the non-output ends of Q connect
Meet third or door (G5) first input end；First and door (G6) first input end connection third or door (G5) output end simultaneously
As the output end of the periodic wakeup module, the second input terminal connects the first detection signal, output end connection
The input terminal of second rise edge delay module；First NAND gate (G4) first input end connect the second rise edge delay module
Output end, the second input terminal connect the inversion signal (ENB) of the enable signal, and third input terminal connects the 4th phase inverter
(T3) output end；
The minimum blanking time generation module includes third d type flip flop (D3), third rise edge delay module, second and door
(G7), the 4th or door (G8) and the 5th or door (G9),
Second and door (G7) first input end connect first or door (T2) output end, the second input terminal connects the minimum
First d type flip flop (D in turn-on time generation module1) the non-output ends of Q, third input terminal connects the periodic wakeup mould
Second d type flip flop (D in block2) the non-output ends of Q, output end connects third d type flip flop (D3) clock end and the 5th or door
(G9) first input end；Third d type flip flop (D3) data input pin connection enable signal (EN), reset terminal connection the 4th
Or door (G8) output end, Q output connect third rise edge delay module input terminal and the 5th or door (G9) it is second defeated
Enter end；5th or door (G9) output end of the output end as the minimum blanking time generation module；4th or door (G8)
One input terminal connects the output end of third rise edge delay module, and the second input terminal connects in the periodic wakeup module the
2-D trigger (D2) Q output, third input terminal connect the 4th phase inverter (T3) output end；
The output end of minimum turn-on time generation module described in the first input end of the drive module, the connection of the second input terminal
The output end of the periodic wakeup module, third input terminal connect the output end of the minimum blanking time generation module,
Its output end connects the grid of the rectifying tube.
2. synchronous commutating control circuit according to claim 1, which is characterized in that the voltage detection module includes first
Comparator (Comp1), the second comparator (Comp2), first voltage source and the second voltage source, first comparator (Comp1) it is same
Phase input terminal connects the drain electrode of the rectifying tube, and inverting input connects the forward end of first voltage source, output end output
The first detection signal；The forward end of the in-phase input end connection the second voltage source of second comparator (Comp2), reverse phase are defeated
Enter the drain electrode that end connects the rectifying tube, output end output the second detection signal；First voltage source and the second voltage source
Negative end connect the source electrode of the rectifying tube.
3. synchronous commutating control circuit according to claim 2, which is characterized in that the first comparator (Comp1) is
Hysteresis comparator.
4. synchronous commutating control circuit according to claim 1, which is characterized in that the first rise edge delay module,
Second rise edge delay module and third rise edge delay module structure having the same, the first rise edge delay module packet
Include the first current source (I1), the first capacitance (C1), the first metal-oxide-semiconductor (M1), the second nor gate (T5), the second NAND gate (T6) and first
Schmidt trigger (T7), the second NAND gate (T6) input terminal of the first input end as the first rise edge delay module,
Its second input terminal connects the enable signal (EN), and output end connects the first metal-oxide-semiconductor (M1) grid；First capacitance (C1)
One end connect the first metal-oxide-semiconductor (M1) drain electrode, the first Schmidt trigger (T7) input terminal and the first current source (I1) it is negative
Xiang Duan, the other end connect the first metal-oxide-semiconductor (M1) source electrode and ground connection；First current source (I1) forward end connect supply voltage；
Second nor gate (T5) input terminal connect the first Schmidt trigger (T7) output end, output end is as on described first
Rise the output end along Postponement module.
5. synchronous commutating control circuit according to claim 1, which is characterized in that the synchronous rectification Logic control module
Further include the first phase inverter (T1) of the inversion signal for generating the enable signal (EN), the input of the first phase inverter (T1)
End connects the enable signal (EN), and output end exports the inversion signal (ENB) of the enable signal.
6. synchronous commutating control circuit according to claim 1, which is characterized in that the drive module includes third and door
(T4), the second nor gate (T5) and driving output stage, the first input end of third and door (T4) as the drive module the
One input terminal, the second input terminal connect the output end of the second nor gate (T5), and output end connects the driving output stage
Input terminal；Second input terminal of the first input end of second nor gate (T5) as the drive module, the second input terminal are made
For the third input terminal of the drive module；The driving output stage includes the cascade phase inverter of even number, output end conduct
The output end of the drive module.
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| US11757366B2 (en) | 2020-05-29 | 2023-09-12 | On-Bright Electronics (Shanghai) Co., Ltd. | Systems and methods for synchronous rectification of power supply systems |
| US12047007B2 (en) | 2021-03-11 | 2024-07-23 | On-Bright Electronics (Shanghai) Co., Ltd. | Systems and methods for controlling gate voltage increase on primary side to reduce voltage spike on secondary side of switching power supplies |
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| US12047007B2 (en) | 2021-03-11 | 2024-07-23 | On-Bright Electronics (Shanghai) Co., Ltd. | Systems and methods for controlling gate voltage increase on primary side to reduce voltage spike on secondary side of switching power supplies |
| US12095379B2 (en) | 2021-07-07 | 2024-09-17 | On-Bright Electronics (Shanghai) Co., Ltd. | Systems and methods for controlling synchronous rectification with variable voltage regulation |
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