CN108538921A - A kind of thin film transistor (TFT) and preparation method thereof, array substrate - Google Patents
A kind of thin film transistor (TFT) and preparation method thereof, array substrate Download PDFInfo
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- CN108538921A CN108538921A CN201810380871.9A CN201810380871A CN108538921A CN 108538921 A CN108538921 A CN 108538921A CN 201810380871 A CN201810380871 A CN 201810380871A CN 108538921 A CN108538921 A CN 108538921A
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- 239000010409 thin film Substances 0.000 title claims abstract description 60
- 239000000758 substrate Substances 0.000 title claims abstract description 40
- 238000002360 preparation method Methods 0.000 title claims abstract description 14
- 238000009413 insulation Methods 0.000 claims abstract description 135
- 239000012212 insulator Substances 0.000 claims abstract description 54
- OFIYHXOOOISSDN-UHFFFAOYSA-N tellanylidenegallium Chemical compound [Te]=[Ga] OFIYHXOOOISSDN-UHFFFAOYSA-N 0.000 claims abstract description 50
- 239000010408 film Substances 0.000 claims description 135
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 22
- 239000000463 material Substances 0.000 claims description 21
- 229920002120 photoresistant polymer Polymers 0.000 claims description 19
- 238000005530 etching Methods 0.000 claims description 17
- 238000000034 method Methods 0.000 claims description 17
- 239000004020 conductor Substances 0.000 claims description 14
- 230000000903 blocking effect Effects 0.000 claims description 10
- 238000000059 patterning Methods 0.000 claims description 9
- 230000005611 electricity Effects 0.000 claims description 8
- 238000001039 wet etching Methods 0.000 claims description 8
- 230000015572 biosynthetic process Effects 0.000 claims description 5
- 239000011810 insulating material Substances 0.000 claims description 5
- GPRLSGONYQIRFK-UHFFFAOYSA-N hydron Chemical compound [H+] GPRLSGONYQIRFK-UHFFFAOYSA-N 0.000 claims description 4
- 230000003628 erosive effect Effects 0.000 claims 1
- 230000003071 parasitic effect Effects 0.000 abstract description 9
- 229910052751 metal Inorganic materials 0.000 description 9
- 239000002184 metal Substances 0.000 description 9
- 230000000694 effects Effects 0.000 description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 7
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 4
- 239000010949 copper Substances 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 3
- 229910004205 SiNX Inorganic materials 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 239000011888 foil Substances 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- MRNHPUHPBOKKQT-UHFFFAOYSA-N indium;tin;hydrate Chemical compound O.[In].[Sn] MRNHPUHPBOKKQT-UHFFFAOYSA-N 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 239000011787 zinc oxide Substances 0.000 description 2
- 229910017107 AlOx Inorganic materials 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910003070 TaOx Inorganic materials 0.000 description 1
- LGQLWSVDRFRGCP-UHFFFAOYSA-N [Mo].[Nd] Chemical compound [Mo].[Nd] LGQLWSVDRFRGCP-UHFFFAOYSA-N 0.000 description 1
- NIXOWILDQLNWCW-UHFFFAOYSA-N acrylic acid group Chemical group C(C=C)(=O)O NIXOWILDQLNWCW-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- VVTQWTOTJWCYQT-UHFFFAOYSA-N alumane;neodymium Chemical compound [AlH3].[Nd] VVTQWTOTJWCYQT-UHFFFAOYSA-N 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 229910000449 hafnium oxide Inorganic materials 0.000 description 1
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- HRHKULZDDYWVBE-UHFFFAOYSA-N indium;oxozinc;tin Chemical compound [In].[Sn].[Zn]=O HRHKULZDDYWVBE-UHFFFAOYSA-N 0.000 description 1
- 239000012774 insulation material Substances 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 1
- 230000024241 parasitism Effects 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 229920001296 polysiloxane Polymers 0.000 description 1
- -1 polysiloxanes Polymers 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 230000002269 spontaneous effect Effects 0.000 description 1
- 229910001936 tantalum oxide Inorganic materials 0.000 description 1
- 230000000007 visual effect Effects 0.000 description 1
- YVTHLONGBIQYBO-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) Chemical compound [O--].[Zn++].[In+3] YVTHLONGBIQYBO-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
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- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
Abstract
A kind of thin film transistor (TFT) of the embodiment of the present invention offer and preparation method thereof, array substrate, are related to display technology field, can improve and lead to the problem of parasitic capacitance.A kind of thin film transistor (TFT), including：It is set in turn in bottom gate thin film on substrate, the first gate insulation layer, active layer, the second gate insulation layer, top-gated electrode, organic insulator and source electrode, drain electrode；The bottom gate thin film, first gate insulation layer, second gate insulation layer and the top-gated electrode are between the source electrode and the drain electrode；The active layer includes channel region between first gate insulation layer and second gate insulation layer, the source area for being located at the channel region both sides and drain region；The source area and the drain region are supported by the organic insulator；The source electrode is contacted by via with the drain region by via and the source region contact, the drain electrode.
Description
Technical field
The present invention relates to display technology field more particularly to a kind of thin film transistor (TFT) and preparation method thereof, array substrates.
Background technology
Organic electroluminescent LED (Organic Light-Emitting Diode, OLED) display has spontaneous
Light, reaction be fast, visual angle light, high, frivolous brightness the advantages that, it is considered to be next-generation display technology.Since OLED display relies on
Electric current drives, therefore big driving current is to ensure to show quality, carries high-resolution basis.
Double-gate structure thin film transistor (TFT) (Thin Film Transistor, TFT) is big with ON state current, grid-control ability is strong
Advantages such as (subthreshold behavior are preferable) meet requirement of the OLED display to driving current, but there are larger parasitic capacitances.
Currently, double-gate structure TFT, as shown in Figure 1, bottom gate thin film 20, bottom gate insulation including being set in turn in substrate 10
Layer 31, active layer 40, source electrode 51 and drain electrode 52, top-gated insulating layer 32 and top-gated electrode 60；Bottom gate insulating layer 31 and top-gated
Insulating layer 32 is laid on substrate.
Invention content
A kind of thin film transistor (TFT) of the embodiment of the present invention offer and preparation method thereof, array substrate, it is parasitic can to improve generation
The problem of capacitance.
In order to achieve the above objectives, the embodiment of the present invention adopts the following technical scheme that：
In a first aspect, a kind of thin film transistor (TFT) is provided, including：Bottom gate thin film, the first grid being set in turn on substrate are exhausted
Edge layer, active layer, the second gate insulation layer, top-gated electrode, organic insulator and source electrode, drain electrode；It is the bottom gate thin film, described
First gate insulation layer, second gate insulation layer and the top-gated electrode are between the source electrode and the drain electrode；Institute
Active layer is stated to include channel region between first gate insulation layer and second gate insulation layer, be located at the ditch
The source area of the both sides Dao Qu and drain region；The source area and the drain region are supported by the organic insulator；The source electricity
Pole is contacted by via with the drain region by via and the source region contact, the drain electrode.
Optionally, the thin film transistor (TFT) further include be set to the bottom gate thin film close to the one side of substrate and with it is described
Conductive layer, the auxiliary electrode with the source electrode and the drain electrode same layer of bottom gate thin film electrical connection；The auxiliary electrode point
It is not electrically connected with the top-gated electrode, the conductive layer；The orthographic projection covering of the conductive layer over the substrate is described active
The orthographic projection of layer over the substrate.
Further alternative, the conductive layer is transparency conducting layer；The transparency conducting layer and the bottom gate thin film are direct
Contact.
Optionally, the thin film transistor (TFT) further includes being set to the organic insulator close to the source electrode and the leakage
The inorganic insulation layer of electrode side；The source electrode by through the via of the organic insulator and the inorganic insulation layer with
The source region contact, the drain electrode pass through through the via of the organic insulator and the inorganic insulation layer and the leakage
Region contacts.
Optionally, the material of the organic insulator is black organic insulating material.
Optionally, the thickness of the active layer is within the scope of 30~80nm.
Second aspect provides a kind of array substrate, including the thin film transistor (TFT) described in first aspect.
The third aspect provides a kind of preparation method of thin film transistor (TFT), including：The first metal foil is sequentially formed on substrate
Film, the first grid insulating film, semiconductive thin film, the second grid insulating film, the second metallic film, photoresist；Utilize mask plate pair
The photoresist exposure, and after development, keep the shape of the photoresist of reservation consistent with the pattern of active layer to be formed；With photoresist
It is continuously exhausted to second metallic film, second grid insulating film, the semiconductive thin film, the first grid for blocking
Edge film and first metallic film perform etching；It is blocking with photoresist, using wet-etching technology, respectively to described the
Two grid insulating films, first grid insulating film, second metallic film and first metallic film carry out second
Etching, so that second grid insulating film is formed the second gate insulation layer, first grid insulating film forms the first gate insulation layer,
Second metallic film forms top-gated electrode, first metallic film forms bottom gate thin film, and second gate insulation layer,
First gate insulation layer, the top-gated electrode and the bottom gate thin film are between source electrode and drain electrode to be formed；It is right
Part of the semiconductive thin film beyond first gate insulation layer and second gate insulation layer is formed active into column conductor
Layer, the active layer include channel layer between first gate insulation layer and second gate insulation layer, are located at
Source area and drain region of the channel region both sides after conductor；Photoresist is removed, and is formed with by a patterning processes
Machine insulating layer；The source area and the drain region are supported by the organic insulator；Source electricity is formed by a patterning processes
Pole and drain electrode, the source electrode pass through via and the drain region by via and the source region contact, the drain electrode
Contact.
Optionally, using wet-etching technology, respectively to second grid insulating film, first grid insulating film,
Second metallic film and first metallic film carry out second and etch, and second grid insulating film is made to form second
Gate insulation layer, first grid insulating film form the first gate insulation layer, second metallic film forms top-gated electrode, described
First metallic film forms bottom gate thin film, including：Using hydrofluoric acid to second grid insulating film and first gate insulation
Film carries out second and etches, and second grid insulating film is made to form the second gate insulation layer, the first grid insulating film shape
At the first gate insulation layer；On the basis of forming second gate insulation layer and first gate insulation layer, to second gold medal
Belong to film and first metallic film performs etching, second metallic film is made to form top-gated electrode, first metal
Film forms bottom gate thin film.
Based on this, to part of the semiconductive thin film beyond first gate insulation layer and second gate insulation layer into
Column conductor forms active layer, including：Using hydrofluoric acid to second grid insulating film and first grid insulating film into
When row second etches, the hydrogen ion in hydrofluoric acid enters the semiconductive thin film beyond first gate insulation layer and described the
Conductor is realized in the part of two gate insulation layers, forms active layer.
Optionally, before forming first metallic film, the method further includes：It is formed by a patterning processes
Transparency conducting layer；First metallic film is formed directly into above the transparency conducting layer；Forming the source electrode and institute
While stating drain electrode, the method further includes：Form auxiliary electrode；The auxiliary electrode passes through via and the top-gated electrode
Electrical connection, is electrically connected by via with the transparency conducting layer；The orthographic projection covering of the transparency conducting layer over the substrate
The orthographic projection of the active layer over the substrate.
The embodiment of the present invention provides a kind of thin film transistor (TFT) and preparation method thereof, array substrate, by make bottom gate thin film,
First gate insulation layer, the second gate insulation layer and top-gated electrode make active layer extend to source between source electrode and drain electrode
It below electrode and drain electrode, and is supported by organic insulator, realizes the source electrode and drain electrode contact with active layer respectively, to
The performance of thin film transistor (TFT) can be achieved, and can improve and lead to the problem of parasitic capacitance.
Description of the drawings
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technology description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
Some embodiments of invention for those of ordinary skill in the art without creative efforts, can be with
Obtain other attached drawings according to these attached drawings.
Fig. 1 is a kind of structural schematic diagram for thin film transistor (TFT) that the prior art provides；
Fig. 2 is a kind of schematic top plan view one of thin film transistor (TFT) provided by the invention；
Fig. 3 be in Fig. 2 AA ' to schematic cross-sectional view one；
Fig. 4 is a kind of schematic top plan view two of thin film transistor (TFT) provided by the invention；
Fig. 5 be in Fig. 4 BB ' to schematic cross-sectional view one；
Fig. 6 be in Fig. 2 AA ' to schematic cross-sectional view two；
Fig. 7 be in Fig. 4 BB ' to schematic cross-sectional view two；
Fig. 8 is a kind of flow diagram of film crystal tube preparation method provided by the invention；
Fig. 9 (a)~9 (f) is a kind of process schematic preparing thin film transistor (TFT) provided by the invention；
Figure 10 is to carry out second to the second grid insulating film and the first grid insulating film to etch, and surpass semiconductive thin film
Go out the part of the second grid insulating film and the first grid insulating film into the schematic diagram after column conductor.
Reference numeral：
10- substrates；20- bottom gate thin films；31- bottom gate insulating layers；32- top-gated insulating layers；40- active layers；41- channel regions；
42- source areas；The drain regions 43-；51- source electrodes；52- drain electrodes；60- top-gated electrodes；The first gate insulation layers of 71-；72- second gates
Insulating layer；81- organic insulators；82- inorganic insulation layers；90- (transparent) conductive layer；100- photoresists；The first metal foils of 200-
Film；400- semiconductive thin films；The second metallic films of 600-；The first grid insulating films of 710-；The second grid insulating films of 720-.
Specific implementation mode
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation describes, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, it is obtained by those of ordinary skill in the art without making creative efforts every other
Embodiment shall fall within the protection scope of the present invention.
The embodiment of the present invention provides a kind of thin film transistor (TFT), as shown in Figures 2 and 3, including：It is set in turn on substrate 10
Bottom gate thin film 20, the first gate insulation layer 71, active layer 40, the second gate insulation layer 72, top-gated electrode 60,81 and of organic insulator
Source electrode 51, drain electrode 52.
Wherein, bottom gate thin film 20, the first gate insulation layer 71, the second gate insulation layer 72 and top-gated electrode 60 are located at source electrode 51
Between drain electrode 52.
Active layer 40 includes channel region 41 between the first gate insulation layer 71 and the second gate insulation layer 72, is located at
The source area 42 of 41 both sides of channel region and drain region 43；Source area 42 and drain region 43 are supported by organic insulator 81；Source electrode
51 are contacted by via (left-hand broken line circle in Fig. 2) with source area 42, drain electrode 52 by via (in Fig. 2 right side virtual coil) with
Drain region 43 contacts.
It will be understood by those skilled in the art that reduce the contact of source electrode 51 and source area 42, drain electrode 52 and drain region 43
Resistance needs (to be alternatively referred to as metal into column conductor in addition to channel region 41 to active layer 40 when forming active layer 40
Change), to be respectively formed source area 42 and drain region 43 in 41 both sides of channel region.
Bottom gate thin film 20, the first gate insulation layer 71, the second gate insulation layer 72 and top-gated electrode 60 are located at source electrode 51 and leakage
Between electrode 52, that is, bottom gate thin film 20, the first gate insulation layer 71, the second gate insulation layer 72 and top-gated electrode 60 are on substrate 10
Orthographic projection and the orthographic projection no overlap of source electrode 51 and drain electrode 52 on substrate 10.
Source area 42 and drain region 43 are supported by organic insulator 81, i.e.,：Source area 42 and drain region 43 are beyond bottom gate electricity
Pole 20, the first gate insulation layer 71, the second gate insulation layer 72 and top-gated electrode 60, and extend respectively to source electrode 51 and drain electrode 52
Lower section.Wherein, the size of bottom gate thin film 20, the first gate insulation layer 71, the second gate insulation layer 72 and top-gated electrode 60 can phase
Deng and be overlapped.
In the case of there was only organic insulator 81 between source electrode 51 and drain electrode 52 and active layer 40,51 He of source electrode
Drain electrode 52 is contacted by the via being set on organic insulator 81 with the source area 42 of active layer 40 and drain region 43 respectively；
Between source electrode 51 and drain electrode 52 and active layer 40 in addition to there are organic insulator 81, the case where there is also other insulating layers
Under, source electrode 51 and drain electrode 52 pass through the via and active layer 40 on organic insulator 81 and other insulating layers respectively
Source area 42 and drain region 43 contact.
The structure of the thin film transistor (TFT) based on the embodiment of the present invention, the first gate insulation layer 71 and the second gate insulation layer 72
Size determined by 41 size of channel region set.
The embodiment of the present invention provides a kind of thin film transistor (TFT), by making bottom gate thin film 20, the first gate insulation layer 71, second gate
Insulating layer 72 and top-gated electrode 60 make active layer 40 extend to source electrode 51 and leakage between source electrode 51 and drain electrode 52
The lower section of electrode 52, and being supported by organic insulator 81, realize source electrode 51 and drain electrode 52 respectively with the contact of active layer 40, from
And can realize the performance of thin film transistor (TFT), and can improve and lead to the problem of parasitic capacitance.
Optionally, as shown in Figure 4 and Figure 5, the thin film transistor (TFT) further includes being set to bottom gate thin film 20 close to substrate 10
Side and conductive layer 90, the auxiliary electrode 53 with 52 same layer of source electrode 51 and drain electrode being electrically connected with bottom gate thin film 20；Auxiliary
Electrode 53 is electrically connected with top-gated electrode 60, conductive layer 90 respectively；Orthographic projection of the conductive layer 90 on substrate 10 covers active layer 40
Orthographic projection on substrate 10.
That is, by conductive layer 90 and auxiliary electrode 53, top-gated electrode 60 and bottom gate thin film 20 are electrically connected, realize top-gated electricity
20 equipotential of pole 60 and bottom gate thin film.Auxiliary electrode 53 is electrically connected by via with conductive layer 90, and auxiliary electrode 53 passes through via
It is electrically connected with top-gated electrode 60.
Wherein, due to active layer 40 extend to source electrode 51 and the lower section of drain electrode 52 source area 42 and drain region 43 by having
Machine insulating layer 81 supports so that there are organic insulator 81 between source electrode 51, drain electrode 52 and conductive layer 90, thus,
In the case of conductive layer 90 is arranged, organic insulator 81, which may also function as, reduces source electrode 51 and drain electrode 52 and 90 parasitism of conductive layer
The effect of capacitance.
It should be noted that bottom gate thin film 20 and conductive layer 90 are electrically connected, be not limited to illustrate in Fig. 5 be in direct contact and
Electrical connection, can be electrically connected by via.
In the embodiment of the present invention, the setting of conductive layer 90, on the one hand, auxiliary electrode 53 can be coordinated to make top-gated electrode 60 and bottom
Gate electrode 20 is electrically connected, and on the other hand, be can be used as light shield layer, is played the effect for blocking ambient light.
It is further preferred that conductive layer 90 is transparency conducting layer；Transparency conducting layer is in direct contact with bottom gate thin film 20.That is,
Bottom gate thin film 20 is formed directly on transparency conducting layer.
Wherein, transparent conductive oxide material may be used in the material of transparency conducting layer, such as ITO (tin indium oxide), IZO
(indium zinc oxide) etc..
It should be noted that when conductive layer 90 is transparency conducting layer, it can absorb ambient light and panel itself short wavelength
Light, therefore, transparency conducting layer also can be used as light shield layer.Wherein, when conductive layer 90 is metal conducting layer, metal conducting layer is logical
Reflection environment light is crossed to realize the effect for blocking ambient light, and it is transparency conducting layer to work as conductive layer 90, passes through and absorbs ambient light
To realize the effect for blocking ambient light.
The embodiment of the present invention, it is opposite to set conductive layer 90 to metal conducting layer, set conductive layer 90 to electrically conducting transparent
Layer can be not necessarily to consider the influence to conductive layer 90 when etching forms bottom gate thin film 20.
Optionally, as shown in Figure 6 and Figure 7, the thin film transistor (TFT) further includes being set to organic insulator 81 close to source electricity
The inorganic insulation layer 82 of 52 side of pole 51 and drain electrode；Source electrode 51 passes through through organic insulator 81 and inorganic insulation layer 82
Via is contacted with source area 42, and drain electrode 52 passes through through the via of organic insulator 81 and inorganic insulation layer 82 and drain region 43
Contact.
Wherein, the material of inorganic insulation layer 82 for example can be SiOx(silica) and/or SiNx(silicon nitride) etc..
In view of organic insulating material insulating properties compared with inorganic insulation poor insulativity, therefore, for reduce by 51 He of source electrode
The short-circuit risks of drain electrode 52 and top-gated electrode 60 are arranged inorganic between organic insulator 81 and source electrode 51 and drain electrode 52
Insulating layer 82.
Optionally, the material of organic insulator 81 is black organic insulating material.
Transparent organic material is used compared to organic insulator 81, when the material of organic insulator 81 is black organic insulation
Material may also function as interception, play a protective role from far from 10 side of substrate to active layer 40.
Optionally, the thickness of active layer 40 is within the scope of 30~80nm.
Since before forming organic insulator 81, the source area 42 of active layer 40 and drain region 43 exceed bottom gate thin film
20, the first gate insulation layer 71, the second gate insulation layer 72 and top-gated electrode 60 and be in vacant state, when 40 thinner thickness of active layer
When, there is the risk to fracture, therefore, its intensity can be improved by suitably increasing the thickness of active layer 40, and by active layer 40
Thickness be arranged within the scope of 30~80nm when, can avoid the generation to fracture substantially.
Optionally, the material of active layer 40 is oxide.Oxide for example can be IGZO (indium gallium zinc oxide), ZnON
(zinc oxide of N doping), IZTO (indium zinc tin oxide) etc..
Certainly, the material of active layer 40 may be silicon materials.
Material using oxide as active layer 40 can make thin film transistor (TFT) have higher mobility.
Based on the above-mentioned description to thin film transistor (TFT), optionally, bottom gate thin film 20, top-gated electrode 60, source electrode 51 and leakage
The material of electrode 52 can be selected from Ag (silver), Cu (copper), Al (aluminium), the metals such as Mo (molybdenum) or AlNd (aluminium neodymium), MoNb (molybdenum neodymium)
Equal alloys.Bottom gate thin film 20, top-gated electrode 60, source electrode 51 and drain electrode 52 can be one layer of structure, or two layers or
Two layers or more of multilayered structure.
Wherein, when top-gated electrode 60 is using Cu materials, organic insulator 81 also has the function of preventing Cu from aoxidizing.
Optionally, the first gate insulation layer 71, the second gate insulation layer 72 material can be selected from SiOx、SiNx, SiON (nitrogen oxidations
Silicon) etc.；Alternatively, also selected from such as AlOx(aluminium oxide), HfOx(hafnium oxide), TaOxThe insulation of high-ks such as (tantalum oxide)
Material.First gate insulation layer 71, the second gate insulation layer 72 can be one layer of structure, or two layers or two layers or more of multilayer
Structure.
Optionally, the material of organic insulator 81 can be selected from polysiloxanes based material, acrylic based material, polyimides system
Material etc. has the material of flattening effect.Organic insulator 81 can be one layer of structure, or two layers or two layers or more
Multilayered structure.
The embodiment of the present invention also provides a kind of array substrate, including above-mentioned thin film transistor (TFT).
The array substrate can be used for LCD (Liquid Crystal Display, liquid crystal display), it can also be used to
OLED (Organic Light-Emitting Diode, Organic Light Emitting Diode) display.
Array substrate provided in an embodiment of the present invention has technique effect identical with the thin film transistor (TFT), herein not
It repeats again.
The embodiment of the present invention also provides a kind of preparation method of thin film transistor (TFT), as shown in figure 8, including：
Shown in S11, such as Fig. 9 (a), sequentially formed on substrate 10 first metallic film 200, the first grid insulating film 710,
Semiconductive thin film 400, the second grid insulating film 720, the second metallic film 600, photoresist 100.
Shown in S12, such as Fig. 9 (b), photoresist 100 is exposed using mask plate, and after development, make the photoresist 100 of reservation
Shape it is consistent with the pattern of active layer to be formed.
It is blocking with photoresist 100 shown in S13, such as Fig. 9 (c), it is continuously thin to the second metallic film 600, the second gate insulation
Film 720, semiconductive thin film 400, the first grid insulating film 710 and the first metallic film 200 perform etching.
It is blocking with photoresist, using wet-etching technology, respectively to the second grid insulating film shown in S14, such as Fig. 9 (d)
720, the first grid insulating film 710, the second metallic film 600 and the first metallic film 200 carry out second of etching, make second gate
Insulation film 720 forms the second gate insulation layer 72, the first grid insulating film 710 forms the first gate insulation layer 71, the second metal foil
Film 600 forms top-gated electrode 60, the first metallic film 200 forms bottom gate thin film 20, and the second gate insulation layer 72, the first gate insulation
Layer 71, top-gated electrode 60 and bottom gate thin film 20 are between source electrode and drain electrode to be formed.
In S14, can second first be carried out to the second grid insulating film 720 and the first grid insulating film 710 and etched, then
Second is carried out to the second metallic film 600 and the first metallic film 200 to etch；Can also be first to the second metallic film 600
Second is carried out with the first metallic film 200 to etch, then the second grid insulating film 720 and the first grid insulating film 710 are carried out
Second of etching.
Shown in S15, such as Fig. 9 (e), the first gate insulation layer 71 and the second gate insulation layer are exceeded to the semiconductive thin film 400
72 part forms active layer 40 into column conductor, and active layer 40 includes being located at the first gate insulation layer 71 and the second gate insulation layer
Channel region 41 between 72 is located at source area 42 and drain region 43 of 41 both sides of channel region after conductor.
Wherein, the size of the first gate insulation layer 71 and the second gate insulation layer 72 is determined by 41 size of channel region set.
Shown in S16, such as Fig. 9 (f), photoresist 100 is removed, and organic insulator 81 is formed by a patterning processes；Source
Polar region 42 and drain region 43 are supported by organic insulator 81.
Source area 42 and drain region 43 are supported by organic insulator 81, i.e.,：Source area 42 and drain region 43 are beyond bottom gate electricity
Pole 20, the first gate insulation layer 71, the second gate insulation layer 72 and top-gated electrode 60, and extend respectively to source electrode 51 and drain electrode 52
Lower section.Wherein, the size of bottom gate thin film 20, the first gate insulation layer 71, the second gate insulation layer 72 and top-gated electrode 60 can phase
Deng and be overlapped.
S17, refering to what is shown in Fig. 3, forming source electrode 51 by patterning processes and drain electrode 52, source electrode 51 passed through
Hole is contacted with source area 42, and drain electrode 52 is contacted by via with drain region 53.
In the case of there was only organic insulator 81 between source electrode 51 and drain electrode 52 and active layer 40,51 He of source electrode
Drain electrode 52 is contacted by the via being set on organic insulator 81 with the source area 42 of active layer 40 and drain region 43 respectively；
Between source electrode 51 and drain electrode 52 and active layer 40 in addition to there are organic insulator 81, the case where there is also other insulating layers
Under, source electrode 51 and drain electrode 52 pass through the via and active layer 40 on organic insulator 81 and other insulating layers respectively
Source area 42 and drain region 43 contact.
The embodiment of the present invention provides a kind of preparation method of thin film transistor (TFT), by making bottom gate thin film 20, the first gate insulation
The 71, second gate insulation layer 72 of layer and top-gated electrode 60 make active layer 40 extend between source electrode 51 and drain electrode 52
Source electrode 51 and the lower section of drain electrode 52, and supported by organic insulator 81, realize source electrode 51 and drain electrode 52 respectively with it is active
The contact of layer 40 to realize the performance of thin film transistor (TFT), and can improve and lead to the problem of parasitic capacitance.Wherein, due to
During forming bottom gate thin film 20, the first gate insulation layer 71, the second gate insulation layer 72 and top-gated electrode 60, only it has been applicable in primary
Therefore mask, exposure technology can reduce technology difficulty, save cost.
In above-mentioned S14 use wet-etching technology, respectively to the second grid insulating film 720, the first grid insulating film 710,
Second metallic film 600 and the first metallic film 200 carry out second and etch, and the second grid insulating film 720 is made to form second gate
Insulating layer 72, the first grid insulating film 710 form the first gate insulation layer 71, the second metallic film 600 forms top-gated electrode 60, the
One metallic film 200 forms bottom gate thin film 20, can specifically include：
S131, as shown in Figure 10, is carried out using hydrofluoric acid pair the second grid insulating film 720 and the first grid insulating film 710
Second of etching makes the second grid insulating film 720 form the second gate insulation layer 72, the first grid insulating film 710 formation first grid
Insulating layer 71.
Specifically, substrate can be put into hf etching liquid, the second grid insulating film 720 and the first grid insulating film
710 corroded after generate lateral undercutting.Wherein, the depth inwardly etched is determined by the final channel length set.
S132, with reference to shown in figure 9 (e), forming the second gate insulation layer 72 and on the basis of the first gate insulation layer 71, to the
Two metallic films 600 and the first metallic film 200 perform etching, and the second metallic film 600 is made to form top-gated electrode 60, the first gold medal
Belong to film 200 and forms bottom gate thin film 20.
Specifically, when the second metallic film 600 and the first metallic film 200 carry out wet etching, due to losing second
The protection of gate insulation layer 72 and the first gate insulation layer 71, final top-gated electrode 60 and bottom gate thin film 20 are etched to exhausted with second gate
71 identical size of edge layer 72 and the first gate insulation layer realizes self-alignment structure.
Wherein, as shown in Figure 10, it is carried out using hydrofluoric acid pair the second grid insulating film 720 and the first grid insulating film 710
When second of etching, the hydrogen ion in hydrofluoric acid enters semiconductive thin film 400 and exceeds the first gate insulation layer 71 and the second gate insulation
Conductor is realized in the part of layer 72, forms active layer 40.
That is, while the second gate insulation layer 72 and the first gate insulation layer 71 are etched, the semiconductive thin film 400 that exposes
Material is impregnated in hydrogen ion, realizes conductor.
On the one hand, it is carried out second by using hydrofluoric acid pair the second grid insulating film 720 and the first grid insulating film 710
Etching while forming the first gate insulation layer 71 and the second gate insulation layer 72, also makes semiconductive thin film 400 exceed the first gate insulation
The part of layer 71 and the second gate insulation layer 72 realizes that conductorization forms active layer 40, is compared to powerful plasma road
For topicization scheme, technology difficulty and cost are lower；On the other hand, the second grid insulating film of hydrofluoric acid pair 720 and first is utilized
Grid insulating film 710 carries out the undercutting formed in wet etching course, to the second metallic film 600 and the first metallic film
200 carry out second that self-alignment structure may be implemented in etching, and reduce parasitic capacitance (gate-source parasitic capacitance).
Optionally, before forming the first metallic film 200, the method further includes：It is formed by a patterning processes
Transparency conducting layer 90；First metallic film 200 is formed directly into 90 top of transparency conducting layer.On this basis, as shown in figure 5,
While forming source electrode 51 and drain electrode 52, the method further includes forming auxiliary electrode 53；Auxiliary electrode 53 passed through
Hole is electrically connected with top-gated electrode 60, is electrically connected with transparency conducting layer 90 by via；Transparency conducting layer 90 on substrate 10 just
Orthographic projection of the projection covering active layer 40 on substrate 10.
That is, by transparency conducting layer 90 and auxiliary electrode 53, top-gated electrode 60 and bottom gate thin film 20 are electrically connected, realize top
20 equipotential of gate electrode 60 and bottom gate thin film.
Wherein, due to active layer 40 extend to source electrode 51 and the lower section of drain electrode 52 source area 42 and drain region 43 by having
Machine insulating layer 81 supports so that there are organic insulator 81 between source electrode 51 and drain electrode 52 and transparency conducting layer 90, because
And in the case where forming transparency conducting layer 90, organic insulator 81 may also function as reduce source electrode 51 and drain electrode 52 with thoroughly
The effect of 90 parasitic capacitance of bright conductive layer.
In the embodiment of the present invention, the formation of transparency conducting layer 90, on the one hand, auxiliary electrode 53 can be coordinated to make top-gated electrode 60
It is electrically connected with bottom gate thin film 20；On the other hand, light shield layer is can be used as, the effect for blocking ambient light is played；In another aspect, etching
When forming bottom gate thin film 20, it can be not necessarily to consider the influence to transparency conducting layer 90.
Optionally, as shown in Figure 6 and Figure 7, the thin film transistor (TFT) further includes in organic insulator 81 close to source electrode 51
Inorganic insulation layer 82 is formed with 52 side of drain electrode；Source electrode 51 passes through the mistake through organic insulator 81 and inorganic insulation layer 82
Hole is contacted with source area 42, and drain electrode 52 through the via of organic insulator 81 and inorganic insulation layer 82 and drain region 43 by connecing
It touches.
Wherein, the material of inorganic insulation layer 82 for example can be SiOx(silica) and/or SiNx(silicon nitride).
In view of organic insulating material insulating properties compared with inorganic insulation poor insulativity, therefore, for reduce by 51 He of source electrode
The short-circuit risks of drain electrode 52 and top-gated electrode 60 are formed inorganic between organic insulator 81 and source electrode 51 and drain electrode 52
Insulating layer 82.
The above description is merely a specific embodiment, but scope of protection of the present invention is not limited thereto, any
Those familiar with the art in the technical scope disclosed by the present invention, can easily think of the change or the replacement, and should all contain
Lid is within protection scope of the present invention.Therefore, protection scope of the present invention should be based on the protection scope of the described claims.
Claims (10)
1. a kind of thin film transistor (TFT), which is characterized in that including：Be set in turn in bottom gate thin film on substrate, the first gate insulation layer,
Active layer, the second gate insulation layer, top-gated electrode, organic insulator and source electrode, drain electrode；
The bottom gate thin film, first gate insulation layer, second gate insulation layer and the top-gated electrode are located at source electricity
Between pole and the drain electrode；
The active layer includes channel region between first gate insulation layer and second gate insulation layer, is located at
The source area of the channel region both sides and drain region；The source area and the drain region are supported by the organic insulator；Institute
Source electrode is stated by via and the source region contact, the drain electrode is contacted by via with the drain region.
2. thin film transistor (TFT) according to claim 1, which is characterized in that further include being set to the bottom gate thin film close to institute
It states one side of substrate and the conductive layer being electrically connected with the bottom gate thin film and the auxiliary of the source electrode and the drain electrode same layer is electric
Pole；
The auxiliary electrode is electrically connected with the top-gated electrode, the conductive layer respectively；The conductive layer is over the substrate
Orthographic projection covers the orthographic projection of the active layer over the substrate.
3. thin film transistor (TFT) according to claim 2, which is characterized in that the conductive layer is transparency conducting layer；
The transparency conducting layer is in direct contact with the bottom gate thin film.
4. thin film transistor (TFT) according to claim 1, which is characterized in that further include that be set to the organic insulator close
The inorganic insulation layer of the source electrode and the drain electrode side；
The source electrode passes through through the via of the organic insulator and the inorganic insulation layer and the source region contact, institute
Drain electrode is stated by being contacted with the drain region through the via of the organic insulator and the inorganic insulation layer.
5. thin film transistor (TFT) according to claim 1, which is characterized in that the material of the organic insulator is that black is organic
Insulating materials.
6. according to claim 1-5 any one of them thin film transistor (TFT)s, which is characterized in that the thickness of the active layer 30~
Within the scope of 80nm.
7. a kind of array substrate, which is characterized in that including claim 1-6 any one of them thin film transistor (TFT)s.
8. a kind of preparation method of thin film transistor (TFT), which is characterized in that including：
The first metallic film, the first grid insulating film, semiconductive thin film, the second grid insulating film, are sequentially formed on substrate
Two metallic films, photoresist；
The photoresist is exposed using mask plate, and after development, makes the shape of the photoresist of reservation and active layer to be formed
Pattern is consistent；
With photoresist be blocking, continuously to second metallic film, second grid insulating film, the semiconductive thin film,
First grid insulating film and first metallic film perform etching；
It is blocking with photoresist, it is thin to second grid insulating film, first gate insulation respectively using wet-etching technology
Film, second metallic film and first metallic film carry out second and etch, and second grid insulating film is made to be formed
Second gate insulation layer, first grid insulating film form the first gate insulation layer, second metallic film forms top-gated electrode,
First metallic film forms bottom gate thin film, and second gate insulation layer, first gate insulation layer, the top-gated electrode
And the bottom gate thin film is between source electrode and drain electrode to be formed；
To part of the semiconductive thin film beyond first gate insulation layer and second gate insulation layer into column conductor, shape
At active layer, the active layer include channel layer between first gate insulation layer and second gate insulation layer, point
It Wei Yu not source area and drain region of the channel region both sides after conductor；
Photoresist is removed, and organic insulator is formed by a patterning processes；The source area and the drain region are by described
Organic insulator supports；
Source electrode and drain electrode is formed by a patterning processes, the source electrode passes through via and the source region contact, institute
Drain electrode is stated to contact with the drain region by via.
9. preparation method according to claim 8, which is characterized in that wet-etching technology is used, respectively to described second
Grid insulating film, first grid insulating film, second metallic film and first metallic film carry out second and carve
Erosion makes second grid insulating film form the second gate insulation layer, the first gate insulation layer of first grid insulating film formation, institute
It states the second metallic film and forms top-gated electrode, first metallic film formation bottom gate thin film, including：
Second is carried out to second grid insulating film and first grid insulating film to etch, make described the using hydrofluoric acid
Two grid insulating films form the second gate insulation layer, first grid insulating film forms the first gate insulation layer；
Forming second gate insulation layer and on the basis of first gate insulation layer, to second metallic film and described
First metallic film performs etching, and second metallic film is made to form top-gated electrode, first metallic film formation bottom gate
Electrode；
To part of the semiconductive thin film beyond first gate insulation layer and second gate insulation layer into column conductor, shape
At active layer, including：
When carrying out second of etching to second grid insulating film and first grid insulating film using hydrofluoric acid, hydrofluoric acid
In hydrogen ion enter the semiconductive thin film exceed first gate insulation layer and second gate insulation layer part, realize
Conductor forms active layer.
10. preparation method according to claim 8 or claim 9, which is characterized in that before forming first metallic film,
The method further includes：Transparency conducting layer is formed by a patterning processes；First metallic film is formed directly into described
Above transparency conducting layer；
While forming the source electrode and the drain electrode, the method further includes：Form auxiliary electrode；The auxiliary electricity
Pole is electrically connected by via with the top-gated electrode, is electrically connected with the transparency conducting layer by via；The transparency conducting layer
Orthographic projection over the substrate covers the orthographic projection of the active layer over the substrate.
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| CN113451332A (en) * | 2021-06-21 | 2021-09-28 | 昆山国显光电有限公司 | Array substrate and display panel |
| CN113629072A (en) * | 2021-07-26 | 2021-11-09 | 深圳市华星光电半导体显示技术有限公司 | Array substrate, preparation method thereof and display panel |
| US12074221B2 (en) | 2021-07-26 | 2024-08-27 | Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd. | Array substrate and manufacturing method thereof, display panel |
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