CN108538921B - Thin film transistor, preparation method thereof and array substrate - Google Patents

Thin film transistor, preparation method thereof and array substrate Download PDF

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CN108538921B
CN108538921B CN201810380871.9A CN201810380871A CN108538921B CN 108538921 B CN108538921 B CN 108538921B CN 201810380871 A CN201810380871 A CN 201810380871A CN 108538921 B CN108538921 B CN 108538921B
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gate insulating
insulating layer
electrode
layer
gate
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CN108538921A (en
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宋振
王国英
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BOE Technology Group Co Ltd
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BOE Technology Group Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel

Abstract

The embodiment of the invention provides a thin film transistor, a preparation method thereof and an array substrate, relates to the technical field of display, and can solve the problem of parasitic capacitance. A thin film transistor, comprising: the organic light-emitting diode comprises a bottom gate electrode, a first gate insulating layer, an active layer, a second gate insulating layer, a top gate electrode, an organic insulating layer, a source electrode and a drain electrode which are sequentially arranged on a substrate; the bottom gate electrode, the first gate insulating layer, the second gate insulating layer and the top gate electrode are positioned between the source electrode and the drain electrode; the active layer comprises a channel region positioned between the first gate insulating layer and the second gate insulating layer, and a source region and a drain region which are respectively positioned at two sides of the channel region; the source region and the drain region are supported by the organic insulating layer; the source electrode is in contact with the source region through a via hole, and the drain electrode is in contact with the drain region through a via hole.

Description

Thin film transistor, preparation method thereof and array substrate
Technical Field
The invention relates to the technical field of display, in particular to a thin film transistor, a preparation method thereof and an array substrate.
Background
An Organic Light-Emitting Diode (OLED) display has advantages of self-luminescence, fast response, viewing angle Light, high brightness, lightness, thinness, and the like, and is considered as a next generation display technology. Since the OLED display is driven by current, a large driving current is the basis for ensuring display quality and improving resolution.
A Thin Film Transistor (TFT) with a double-gate structure has the advantages of large on-state current, strong gate control capability (good subthreshold characteristic), and the like, and meets the requirement of an OLED display on driving current, but has larger parasitic capacitance.
Currently, a dual gate structure TFT, as shown in fig. 1, includes a bottom gate electrode 20, a bottom gate insulating layer 31, an active layer 40, a source electrode 51, a drain electrode 52, a top gate insulating layer 32, and a top gate electrode 60, which are sequentially disposed on a substrate 10; a bottom gate insulating layer 31 and a top gate insulating layer 32 are laid down on the substrate.
Disclosure of Invention
Embodiments of the present invention provide a thin film transistor, a method for manufacturing the same, and an array substrate, which can improve the problem of parasitic capacitance.
In order to achieve the above purpose, the embodiment of the invention adopts the following technical scheme:
in a first aspect, a thin film transistor is provided, including: the organic light-emitting diode comprises a bottom gate electrode, a first gate insulating layer, an active layer, a second gate insulating layer, a top gate electrode, an organic insulating layer, a source electrode and a drain electrode which are sequentially arranged on a substrate; the bottom gate electrode, the first gate insulating layer, the second gate insulating layer and the top gate electrode are positioned between the source electrode and the drain electrode; the active layer comprises a channel region positioned between the first gate insulating layer and the second gate insulating layer, and a source region and a drain region which are respectively positioned at two sides of the channel region; the source region and the drain region are supported by the organic insulating layer; the source electrode is in contact with the source region through a via hole, and the drain electrode is in contact with the drain region through a via hole.
Optionally, the thin film transistor further includes a conductive layer disposed on one side of the bottom gate electrode close to the substrate and electrically connected to the bottom gate electrode, and an auxiliary electrode on the same layer as the source electrode and the drain electrode; the auxiliary electrode is electrically connected with the top gate electrode and the conducting layer respectively; an orthographic projection of the conductive layer on the substrate covers an orthographic projection of the active layer on the substrate.
Further optionally, the conductive layer is a transparent conductive layer; the transparent conductive layer is in direct contact with the bottom gate electrode.
Optionally, the thin film transistor further includes an inorganic insulating layer disposed on a side of the organic insulating layer adjacent to the source electrode and the drain electrode; the source electrode is in contact with the source region through a via hole penetrating the organic insulating layer and the inorganic insulating layer, and the drain electrode is in contact with the drain region through a via hole penetrating the organic insulating layer and the inorganic insulating layer.
Optionally, the organic insulating layer is made of a black organic insulating material.
Optionally, the thickness of the active layer is within a range of 30-80 nm.
In a second aspect, an array substrate is provided, which includes the thin film transistor of the first aspect.
In a third aspect, a method for manufacturing a thin film transistor is provided, including: sequentially forming a first metal film, a first gate insulating film, a semiconductor film, a second gate insulating film, a second metal film and photoresist on a substrate; exposing the photoresist by using a mask plate, and after developing, enabling the shape of the reserved photoresist to be consistent with the pattern of the active layer to be formed; continuously etching the second metal film, the second gate insulating film, the semiconductor film, the first gate insulating film and the first metal film by taking photoresist as a barrier; using photoresist as a barrier, and respectively performing secondary etching on the second gate insulating film, the first gate insulating film, the second metal film and the first metal film by adopting a wet etching process, so that the second gate insulating film forms a second gate insulating layer, the first gate insulating film forms a first gate insulating layer, the second metal film forms a top gate electrode, the first metal film forms a bottom gate electrode, and the second gate insulating layer, the first gate insulating layer, the top gate electrode and the bottom gate electrode are positioned between a source electrode and a drain electrode to be formed; conducting the part of the semiconductor thin film, which exceeds the first gate insulating layer and the second gate insulating layer, to form an active layer, wherein the active layer comprises a channel layer positioned between the first gate insulating layer and the second gate insulating layer, and a source region and a drain region which are respectively positioned at two sides of the channel region and subjected to conductor treatment; removing the photoresist, and forming an organic insulating layer by a one-time composition process; the source region and the drain region are supported by the organic insulating layer; and forming a source electrode and a drain electrode by a one-time composition process, wherein the source electrode is contacted with the source region through a via hole, and the drain electrode is contacted with the drain region through the via hole.
Optionally, a wet etching process is adopted to perform second etching on the second gate insulating film, the first gate insulating film, the second metal film and the first metal film, so that the second gate insulating film forms a second gate insulating layer, the first gate insulating film forms a first gate insulating layer, the second metal film forms a top gate electrode, and the first metal film forms a bottom gate electrode, including: performing second etching on the second gate insulating film and the first gate insulating film by using hydrofluoric acid to enable the second gate insulating film to form a second gate insulating layer and the first gate insulating film to form a first gate insulating layer; on the basis of forming the second gate insulating layer and the first gate insulating layer, etching the second metal film and the first metal film to enable the second metal film to form a top gate electrode and the first metal film to form a bottom gate electrode.
Based on this, the portion of the semiconductor thin film beyond the first gate insulating layer and the second gate insulating layer is conducted to form an active layer, including: and when hydrofluoric acid is used for carrying out secondary etching on the second gate insulating film and the first gate insulating film, hydrogen ions in the hydrofluoric acid enter the part of the semiconductor film, which exceeds the first gate insulating layer and the second gate insulating layer, so that the conductor is realized, and an active layer is formed.
Optionally, before forming the first metal film, the method further includes: forming a transparent conductive layer through a one-time composition process; the first metal film is directly formed above the transparent conducting layer; while forming the source electrode and the drain electrode, the method further includes: forming an auxiliary electrode; the auxiliary electrode is electrically connected with the top gate electrode through a via hole and is electrically connected with the transparent conducting layer through a via hole; the orthographic projection of the transparent conducting layer on the substrate covers the orthographic projection of the active layer on the substrate.
Embodiments of the present invention provide a thin film transistor, a method for manufacturing the same, and an array substrate, in which a bottom gate electrode, a first gate insulating layer, a second gate insulating layer, and a top gate electrode are located between a source electrode and a drain electrode, and an active layer extends to below the source electrode and the drain electrode and is supported by an organic insulating layer, so that the source electrode and the drain electrode are respectively in contact with the active layer, and thus, performance of the thin film transistor can be achieved, and a problem of parasitic capacitance can be improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a thin film transistor provided in the prior art;
fig. 2 is a first schematic top view of a thin film transistor according to the present invention;
FIG. 3 is a schematic sectional view along AA' of FIG. 2;
fig. 4 is a second schematic top view of a thin film transistor according to the present invention;
FIG. 5 is a schematic sectional view along the direction BB' in FIG. 4;
FIG. 6 is a schematic view of AA' shown in FIG. 2;
FIG. 7 is a schematic sectional view taken along line BB' in FIG. 4;
FIG. 8 is a schematic flow chart of a method for fabricating a thin film transistor according to the present invention;
FIGS. 9(a) -9 (f) are schematic views illustrating a process for fabricating a thin film transistor according to the present invention;
fig. 10 is a schematic view after the second etching is performed on the second gate insulating film and the first gate insulating film, and the portion of the semiconductor film beyond the second gate insulating film and the first gate insulating film is subjected to the conductor formation.
Reference numerals:
10-a substrate; 20-a bottom gate electrode; 31-a bottom gate insulating layer; 32-top gate insulating layer; 40-an active layer; 41-channel region; 42-a source region; 43-drain region; 51-a source electrode; 52-drain electrode; 60-a top gate electrode; 71-a first gate insulating layer; 72-a second gate insulating layer; 81-organic insulating layer; 82-inorganic insulating layer; 90- (transparent) conductive layer; 100-photoresist; 200-a first metal film; 400-a semiconductor thin film; 600-a second metal film; 710-a first gate insulating film; 720-second gate insulating film.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
An embodiment of the present invention provides a thin film transistor, as shown in fig. 2 and 3, including: a bottom gate electrode 20, a first gate insulating layer 71, an active layer 40, a second gate insulating layer 72, a top gate electrode 60, an organic insulating layer 81, and a source electrode 51 and a drain electrode 52, which are sequentially disposed on the substrate 10.
Wherein the bottom gate electrode 20, the first gate insulating layer 71, the second gate insulating layer 72, and the top gate electrode 60 are positioned between the source electrode 51 and the drain electrode 52.
The active layer 40 includes a channel region 41 between the first and second gate insulating layers 71 and 72, and source and drain regions 42 and 43 on both sides of the channel region 41, respectively; the source region 42 and the drain region 43 are supported by the organic insulating layer 81; the source electrode 51 contacts the source region 42 through a via (left dotted circle in fig. 2), and the drain electrode 52 contacts the drain region 43 through a via (right dotted circle in fig. 2).
As is apparent to those skilled in the art, in order to reduce the contact resistance between the source electrode 51 and the source region 42, and between the drain electrode 52 and the drain region 43, when the active layer 40 is formed, it is necessary to conduct a conductor (which may also be referred to as a metallization) on the active layer 40 except for the channel region 41, so as to form the source region 42 and the drain region 43 on both sides of the channel region 41.
The bottom gate electrode 20, the first gate insulating layer 71, the second gate insulating layer 72, and the top gate electrode 60 are located between the source electrode 51 and the drain electrode 52, i.e., an orthographic projection of the bottom gate electrode 20, the first gate insulating layer 71, the second gate insulating layer 72, and the top gate electrode 60 on the substrate 10 does not overlap with an orthographic projection of the source electrode 51 and the drain electrode 52 on the substrate 10.
The source region 42 and the drain region 43 are supported by the organic insulating layer 81, that is: the source region 42 and the drain region 43 extend beyond the bottom gate electrode 20, the first gate insulating layer 71, the second gate insulating layer 72, and the top gate electrode 60 to below the source electrode 51 and the drain electrode 52, respectively. Wherein the bottom gate electrode 20, the first gate insulating layer 71, the second gate insulating layer 72, and the top gate electrode 60 may be equal in size and overlap.
In the case where only the organic insulating layer 81 is provided between the source and drain electrodes 51 and 52 and the active layer 40, the source and drain electrodes 51 and 52 are in contact with the source and drain regions 42 and 43 of the active layer 40 through vias provided on the organic insulating layer 81, respectively; in the case where other insulating layers are present between the source and drain electrodes 51 and 52 and the active layer 40 in addition to the organic insulating layer 81, the source and drain electrodes 51 and 52 are in contact with the source and drain regions 42 and 43 of the active layer 40, respectively, through vias that penetrate the organic insulating layer 81 and the other insulating layers.
Based on the structure of the thin film transistor according to the embodiment of the present invention, the sizes of the first gate insulating layer 71 and the second gate insulating layer 72 are determined by the set size of the channel region 41.
Embodiments of the present invention provide a thin film transistor, in which a bottom gate electrode 20, a first gate insulating layer 71, a second gate insulating layer 72, and a top gate electrode 60 are located between a source electrode 51 and a drain electrode 52, and an active layer 40 extends to below the source electrode 51 and the drain electrode 52 and is supported by an organic insulating layer 81, so that the source electrode 51 and the drain electrode 52 are respectively in contact with the active layer 40, and thus, the performance of the thin film transistor can be achieved, and the problem of parasitic capacitance can be improved.
Optionally, as shown in fig. 4 and fig. 5, the thin film transistor further includes a conductive layer 90 disposed on one side of the bottom gate electrode 20 close to the substrate 10 and electrically connected to the bottom gate electrode 20, and an auxiliary electrode 53 on the same layer as the source electrode 51 and the drain electrode 52; the auxiliary electrode 53 is electrically connected to the top gate electrode 60 and the conductive layer 90, respectively; the orthographic projection of the conductive layer 90 on the substrate 10 covers the orthographic projection of the active layer 40 on the substrate 10.
That is, the top gate electrode 60 and the bottom gate electrode 20 are electrically connected through the conductive layer 90 and the auxiliary electrode 53, and the top gate electrode 60 and the bottom gate electrode 20 have the same potential. The auxiliary electrode 53 is electrically connected to the conductive layer 90 through a via hole, and the auxiliary electrode 53 is electrically connected to the top gate electrode 60 through a via hole.
Here, since the source region 42 and the drain region 43, in which the active layer 40 extends to below the source electrode 51 and the drain electrode 52, are supported by the organic insulating layer 81 such that the organic insulating layer 81 exists between the source electrode 51, the drain electrode 52, and the conductive layer 90, in the case where the conductive layer 90 is provided, the organic insulating layer 81 may also function to reduce parasitic capacitance between the source electrode 51 and the drain electrode 52 and the conductive layer 90.
The electrical connection between the bottom gate electrode 20 and the conductive layer 90 is not limited to the electrical connection by direct contact illustrated in fig. 5, and may be an electrical connection through a via.
In the embodiment of the present invention, the conductive layer 90 is disposed to electrically connect the top gate electrode 60 and the bottom gate electrode 20 in cooperation with the auxiliary electrode 53, and to serve as a light shielding layer to shield ambient light.
Further preferably, the conductive layer 90 is a transparent conductive layer; the transparent conductive layer is in direct contact with the bottom gate electrode 20. That is, the bottom gate electrode 20 is directly formed on the transparent conductive layer.
The transparent conductive layer may be made of a transparent conductive oxide material, such as ITO (indium tin oxide), IZO (indium zinc oxide), and the like.
When the conductive layer 90 is a transparent conductive layer, it can absorb ambient light and short-wavelength light inside the panel, and therefore, the transparent conductive layer can also serve as a light shielding layer. When the conductive layer 90 is a metal conductive layer, the metal conductive layer reflects ambient light to shield the ambient light, and when the conductive layer 90 is a transparent conductive layer, the conductive layer absorbs the ambient light to shield the ambient light.
In the embodiment of the present invention, the conductive layer 90 is set as a metal conductive layer, and the conductive layer 90 is set as a transparent conductive layer, so that the influence on the conductive layer 90 is not required to be considered when the bottom gate electrode 20 is formed by etching.
Alternatively, as shown in fig. 6 and 7, the thin film transistor further includes an inorganic insulating layer 82 disposed on a side of the organic insulating layer 81 close to the source electrode 51 and the drain electrode 52; the source electrode 51 contacts the source region 42 through a via hole penetrating the organic insulating layer 81 and the inorganic insulating layer 82, and the drain electrode 52 contacts the drain region 43 through a via hole penetrating the organic insulating layer 81 and the inorganic insulating layer 82.
The material of the inorganic insulating layer 82 may be, for example, SiOx(silicon oxide) and/or SiNx(silicon nitride), and the like.
In view of the fact that the insulating property of the organic insulating material is inferior to that of the inorganic insulating material, an inorganic insulating layer 82 is provided between the organic insulating layer 81 and the source and drain electrodes 51 and 52 in order to reduce the risk of short-circuiting between the source and drain electrodes 51 and 52 and the top gate electrode 60.
Optionally, the organic insulating layer 81 is made of a black organic insulating material.
Compared with the organic insulating layer 81 made of a transparent organic material, when the organic insulating layer 81 is made of a black organic insulating material, the light-shielding effect can be achieved, and the active layer 40 can be protected from the side far away from the substrate 10.
Optionally, the thickness of the active layer 40 is in the range of 30 to 80 nm.
Since the source region 42 and the drain region 43 of the active layer 40 are in a floating state beyond the bottom gate electrode 20, the first gate insulating layer 71, the second gate insulating layer 72, and the top gate electrode 60 before the organic insulating layer 81 is formed, there is a risk of breakage when the active layer 40 is thin, and thus, the strength of the active layer 40 can be improved by appropriately increasing the thickness thereof, and the occurrence of breakage can be substantially prevented when the thickness of the active layer 40 is set within a range of 30 to 80 nm.
Optionally, the material of the active layer 40 is an oxide. The oxide may be, for example, IGZO (indium gallium zinc oxide), ZnON (nitrogen-doped zinc oxide), IZTO (indium zinc tin oxide), or the like.
Of course, the material of the active layer 40 may also be a silicon material.
The thin film transistor can have higher mobility by using an oxide as a material of the active layer 40.
Based on the above description of the thin film transistor, the material of the bottom gate electrode 20, the top gate electrode 60, the source electrode 51, and the drain electrode 52 may be selected from Ag (silver), Cu (copper), Al (aluminum), Mo (molybdenum), and other metals, or alloys of AlNd (aluminum neodymium), MoNb (molybdenum neodymium), and other metals. The bottom gate electrode 20, the top gate electrode 60, the source electrode 51, and the drain electrode 52 may have a one-layer structure, or may have a multilayer structure of two or more layers.
Here, when the top gate electrode 60 is made of a Cu material, the organic insulating layer 81 also has an effect of preventing Cu from being oxidized.
Alternatively, the materials of the first and second gate insulating layers 71 and 72 may be selected from SiOx、SiNxSiON (silicon oxynitride), etc.; alternatively, it can be selected from, for example, AlOx(aluminum oxide), HfOx(hafnium oxide), TaOxAn insulating material having a high dielectric constant such as tantalum oxide. The first gate insulating layer 71 and the second gate insulating layer 72 may have a single-layer structure, or may have a multilayer structure of two or more layers.
Alternatively, the material of the organic insulating layer 81 may be selected from materials having a planarization effect, such as a silicone-based material, an acryl-based material, and a polyimide-based material. The organic insulating layer 81 may have a single-layer structure, or may have a multilayer structure of two or more layers.
The embodiment of the invention also provides an array substrate which comprises the thin film transistor.
The array substrate can be used for an LCD (Liquid Crystal Display) and an OLED (Organic Light-Emitting Diode) Display.
The array substrate provided by the embodiment of the invention has the same technical effect as the thin film transistor, and is not described herein again.
An embodiment of the present invention further provides a method for manufacturing a thin film transistor, as shown in fig. 8, including:
s11, as shown in fig. 9(a), a first metal thin film 200, a first gate insulating thin film 710, a semiconductor thin film 400, a second gate insulating thin film 720, a second metal thin film 600, and a photoresist 100 are sequentially formed on a substrate 10.
S12, as shown in fig. 9(b), after exposing the photoresist 100 to light using a mask and developing, the shape of the remaining photoresist 100 is made to conform to the pattern of the active layer to be formed.
S13, as shown in fig. 9(c), the second metal film 600, the second gate insulating film 720, the semiconductor film 400, the first gate insulating film 710, and the first metal film 200 are continuously etched with the photoresist 100 as a barrier.
S14, as shown in fig. 9(d), the second gate insulating film 720, the first gate insulating film 710, the second metal film 600 and the first metal film 200 are etched for the second time by using the photoresist as a barrier and using a wet etching process, so that the second gate insulating film 720 forms the second gate insulating layer 72, the first gate insulating film 710 forms the first gate insulating layer 71, the second metal film 600 forms the top gate electrode 60, the first metal film 200 forms the bottom gate electrode 20, and the second gate insulating layer 72, the first gate insulating layer 71, the top gate electrode 60 and the bottom gate electrode 20 are located between the source electrode and the drain electrode to be formed.
In S14, the second gate insulating film 720 and the first gate insulating film 710 may be etched for the second time, and then the second metal film 600 and the first metal film 200 may be etched for the second time; or the second metal film 600 and the first metal film 200 may be etched for the second time, and then the second gate insulating film 720 and the first gate insulating film 710 may be etched for the second time.
S15, as shown in fig. 9(e), the semiconductor thin film 400 is conducted to form an active layer 40 by forming a conductor on the portion beyond the first gate insulating layer 71 and the second gate insulating layer 72, where the active layer 40 includes a channel region 41 between the first gate insulating layer 71 and the second gate insulating layer 72, and a source region 42 and a drain region 43 which are respectively located on both sides of the channel region 41 and are conducted.
The dimensions of the first gate insulating layer 71 and the second gate insulating layer 72 are determined by the set dimension of the channel region 41.
S16, as shown in fig. 9(f), removing the photoresist 100, and forming an organic insulating layer 81 by a one-time patterning process; the source region 42 and the drain region 43 are supported by the organic insulating layer 81.
The source region 42 and the drain region 43 are supported by the organic insulating layer 81, that is: the source region 42 and the drain region 43 extend beyond the bottom gate electrode 20, the first gate insulating layer 71, the second gate insulating layer 72, and the top gate electrode 60 to below the source electrode 51 and the drain electrode 52, respectively. Wherein the bottom gate electrode 20, the first gate insulating layer 71, the second gate insulating layer 72, and the top gate electrode 60 may be equal in size and overlap.
S17, referring to fig. 3, the source electrode 51 and the drain electrode 52 are formed by a single patterning process, the source electrode 51 is in contact with the source region 42 through a via, and the drain electrode 52 is in contact with the drain region 53 through a via.
In the case where only the organic insulating layer 81 is provided between the source and drain electrodes 51 and 52 and the active layer 40, the source and drain electrodes 51 and 52 are in contact with the source and drain regions 42 and 43 of the active layer 40 through vias provided on the organic insulating layer 81, respectively; in the case where other insulating layers are present between the source and drain electrodes 51 and 52 and the active layer 40 in addition to the organic insulating layer 81, the source and drain electrodes 51 and 52 are in contact with the source and drain regions 42 and 43 of the active layer 40, respectively, through vias that penetrate the organic insulating layer 81 and the other insulating layers.
Embodiments of the present invention provide a method for manufacturing a thin film transistor, in which a bottom gate electrode 20, a first gate insulating layer 71, a second gate insulating layer 72, and a top gate electrode 60 are located between a source electrode 51 and a drain electrode 52, so that an active layer 40 extends to below the source electrode 51 and the drain electrode 52 and is supported by an organic insulating layer 81, and the source electrode 51 and the drain electrode 52 are respectively in contact with the active layer 40, thereby implementing performance of the thin film transistor and improving a problem of parasitic capacitance. In the process of forming the bottom gate electrode 20, the first gate insulating layer 71, the second gate insulating layer 72 and the top gate electrode 60, only one mask and exposure process is applied, so that the process difficulty can be reduced, and the cost can be saved.
In the above S14, the wet etching process is adopted to perform the second etching on the second gate insulating film 720, the first gate insulating film 710, the second metal film 600, and the first metal film 200, respectively, so that the second gate insulating film 720 forms the second gate insulating layer 72, the first gate insulating film 710 forms the first gate insulating layer 71, the second metal film 600 forms the top gate electrode 60, and the first metal film 200 forms the bottom gate electrode 20, which may specifically include:
s131, as shown in fig. 10, performing a second etching on the second gate insulating film 720 and the first gate insulating film 710 by using hydrofluoric acid, so that the second gate insulating film 720 forms the second gate insulating layer 72, and the first gate insulating film 710 forms the first gate insulating layer 71.
Specifically, the substrate may be placed in a hydrofluoric acid etching solution, and the second gate insulating film 720 and the first gate insulating film 710 are etched to form lateral undercuts. Wherein the depth of the inward etch is determined by the final channel length that is set.
S132, referring to fig. 9(e), after the second gate insulating layer 72 and the first gate insulating layer 71 are formed, the second metal thin film 600 and the first metal thin film 200 are etched, so that the top gate electrode 60 is formed on the second metal thin film 600, and the bottom gate electrode 20 is formed on the first metal thin film 200.
Specifically, when the second metal film 600 and the first metal film 200 are subjected to wet etching, the protection of the second gate insulating layer 72 and the first gate insulating layer 71 is lost, and finally the top gate electrode 60 and the bottom gate electrode 20 are etched to have the same size as the second gate insulating layer 72 and the first gate insulating layer 71, so that a self-aligned structure is realized.
As shown in fig. 10, when the second gate insulating film 720 and the first gate insulating film 710 are etched for the second time by using hydrofluoric acid, hydrogen ions in the hydrofluoric acid enter the semiconductor film 400 beyond the first gate insulating layer 71 and the second gate insulating layer 72, so as to form a conductor, thereby forming the active layer 40.
That is, while the second gate insulating layer 72 and the first gate insulating layer 71 are etched, hydrogen ions are doped into the exposed material of the semiconductor thin film 400, thereby realizing a conductor.
On one hand, the second gate insulating film 720 and the first gate insulating film 710 are etched for the second time by using hydrofluoric acid to form the first gate insulating layer 71 and the second gate insulating layer 72, and simultaneously, the semiconductor film 400 exceeds the first gate insulating layer 71 and the second gate insulating layer 72, so that the active layer 40 is formed by conductor, and compared with a high-power plasma treatment scheme, the process difficulty and the cost are lower; on the other hand, the undercut formed during the wet etching process of the second gate insulating film 720 and the first gate insulating film 710 with hydrofluoric acid can realize a self-aligned structure during the second etching process of the second metal film 600 and the first metal film 200, thereby reducing the parasitic capacitance (gate-source parasitic capacitance).
Optionally, before forming the first metal thin film 200, the method further includes: forming a transparent conductive layer 90 through a one-time patterning process; the first metal film 200 is formed directly over the transparent conductive layer 90. On this basis, as shown in fig. 5, while forming the source electrode 51 and the drain electrode 52, the method further includes forming an auxiliary electrode 53; the auxiliary electrode 53 is electrically connected to the top gate electrode 60 through a via hole, and is electrically connected to the transparent conductive layer 90 through a via hole; an orthographic projection of the transparent conductive layer 90 on the substrate 10 covers an orthographic projection of the active layer 40 on the substrate 10.
That is, the top gate electrode 60 and the bottom gate electrode 20 are electrically connected through the transparent conductive layer 90 and the auxiliary electrode 53, and the top gate electrode 60 and the bottom gate electrode 20 are equipotential.
Here, since the source region 42 and the drain region 43, in which the active layer 40 extends to below the source electrode 51 and the drain electrode 52, are supported by the organic insulating layer 81 such that the organic insulating layer 81 exists between the source electrode 51 and the drain electrode 52 and the transparent conductive layer 90, in the case of forming the transparent conductive layer 90, the organic insulating layer 81 may also function to reduce parasitic capacitance of the source electrode 51 and the drain electrode 52 with the transparent conductive layer 90.
In the embodiment of the present invention, the transparent conductive layer 90 is formed, on one hand, to cooperate with the auxiliary electrode 53 to electrically connect the top gate electrode 60 and the bottom gate electrode 20; on the other hand, the light-shielding layer can be used as a light-shielding layer to play a role in shielding the ambient light; on the other hand, when the bottom gate electrode 20 is formed by etching, the influence on the transparent conductive layer 90 may not be considered.
Alternatively, as shown in fig. 6 and 7, the thin film transistor further includes an inorganic insulating layer 82 formed on the organic insulating layer 81 on the side close to the source electrode 51 and the drain electrode 52; the source electrode 51 contacts the source region 42 through a via hole penetrating the organic insulating layer 81 and the inorganic insulating layer 82, and the drain electrode 52 contacts the drain region 43 through a via hole penetrating the organic insulating layer 81 and the inorganic insulating layer 82.
The material of the inorganic insulating layer 82 may be, for example, SiOx(silicon oxide) and/or SiNx(silicon nitride).
In view of the fact that the insulating property of the organic insulating material is inferior to that of the inorganic insulating material, the inorganic insulating layer 82 is formed between the organic insulating layer 81 and the source and drain electrodes 51 and 52 in order to reduce the risk of short-circuiting between the source and drain electrodes 51 and 52 and the top gate electrode 60.
The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and all the changes or substitutions should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.

Claims (10)

1. A thin film transistor, comprising: the organic light-emitting diode comprises a bottom gate electrode, a first gate insulating layer, an active layer, a second gate insulating layer, a top gate electrode, an organic insulating layer, a source electrode and a drain electrode which are sequentially arranged on a substrate;
the bottom gate electrode, the first gate insulating layer, the second gate insulating layer and the top gate electrode are positioned between the source electrode and the drain electrode; orthographic projections of the bottom gate electrode, the first gate insulating layer, the second gate insulating layer and the top gate electrode on the substrate are not overlapped with orthographic projections of the source electrode and the drain electrode on the substrate;
the active layer comprises a channel region positioned between the first gate insulating layer and the second gate insulating layer, and a source region and a drain region which are respectively positioned at two sides of the channel region; the source region and the drain region are supported by the organic insulating layer; the source electrode is in contact with the source region through a via hole, and the drain electrode is in contact with the drain region through a via hole.
2. The thin film transistor according to claim 1, further comprising a conductive layer disposed on a side of the bottom gate electrode adjacent to the substrate and electrically connected to the bottom gate electrode, and an auxiliary electrode on a same layer as the source electrode and the drain electrode;
the auxiliary electrode is electrically connected with the top gate electrode and the conducting layer respectively; an orthographic projection of the conductive layer on the substrate covers an orthographic projection of the active layer on the substrate.
3. The thin film transistor according to claim 2, wherein the conductive layer is a transparent conductive layer;
the transparent conductive layer is in direct contact with the bottom gate electrode.
4. The thin film transistor according to claim 1, further comprising an inorganic insulating layer provided on a side of the organic insulating layer adjacent to the source electrode and the drain electrode;
the source electrode is in contact with the source region through a via hole penetrating the organic insulating layer and the inorganic insulating layer, and the drain electrode is in contact with the drain region through a via hole penetrating the organic insulating layer and the inorganic insulating layer.
5. The thin film transistor according to claim 1, wherein a material of the organic insulating layer is a black organic insulating material.
6. The thin film transistor according to any one of claims 1 to 5, wherein the thickness of the active layer is in the range of 30 to 80 nm.
7. An array substrate comprising the thin film transistor according to any one of claims 1 to 6.
8. A method for manufacturing a thin film transistor includes:
sequentially forming a first metal film, a first gate insulating film, a semiconductor film, a second gate insulating film, a second metal film and photoresist on a substrate;
exposing the photoresist by using a mask plate, and after developing, enabling the shape of the reserved photoresist to be consistent with the pattern of the active layer to be formed;
continuously etching the second metal film, the second gate insulating film, the semiconductor film, the first gate insulating film and the first metal film by taking photoresist as a barrier;
using photoresist as a barrier, and respectively performing secondary etching on the second gate insulating film, the first gate insulating film, the second metal film and the first metal film by adopting a wet etching process, so that the second gate insulating film forms a second gate insulating layer, the first gate insulating film forms a first gate insulating layer, the second metal film forms a top gate electrode, the first metal film forms a bottom gate electrode, and the second gate insulating layer, the first gate insulating layer, the top gate electrode and the bottom gate electrode are positioned between a source electrode and a drain electrode to be formed; orthographic projections of the bottom gate electrode, the first gate insulating layer, the second gate insulating layer and the top gate electrode on the substrate are not overlapped with orthographic projections of the source electrode and the drain electrode on the substrate;
conducting the part of the semiconductor thin film, which exceeds the first gate insulating layer and the second gate insulating layer, to form an active layer, wherein the active layer comprises a channel layer positioned between the first gate insulating layer and the second gate insulating layer, and a source region and a drain region which are respectively positioned at two sides of the channel region and subjected to conductor treatment;
removing the photoresist, and forming an organic insulating layer by a one-time composition process; the source region and the drain region are supported by the organic insulating layer;
and forming a source electrode and a drain electrode by a one-time composition process, wherein the source electrode is contacted with the source region through a via hole, and the drain electrode is contacted with the drain region through the via hole.
9. The method according to claim 8, wherein a wet etching process is used to perform a second etching on the second gate insulating film, the first gate insulating film, the second metal film and the first metal film, so that the second gate insulating film forms a second gate insulating layer, the first gate insulating film forms a first gate insulating layer, the second metal film forms a top gate electrode, and the first metal film forms a bottom gate electrode, and the method comprises:
performing second etching on the second gate insulating film and the first gate insulating film by using hydrofluoric acid to enable the second gate insulating film to form a second gate insulating layer and the first gate insulating film to form a first gate insulating layer;
on the basis of forming the second gate insulating layer and the first gate insulating layer, etching the second metal film and the first metal film to enable the second metal film to form a top gate electrode and the first metal film to form a bottom gate electrode;
conducting a portion of the semiconductor thin film beyond the first gate insulating layer and the second gate insulating layer to form an active layer, including:
and when hydrofluoric acid is used for carrying out secondary etching on the second gate insulating film and the first gate insulating film, hydrogen ions in the hydrofluoric acid enter the part of the semiconductor film, which exceeds the first gate insulating layer and the second gate insulating layer, so that the conductor is realized, and an active layer is formed.
10. The production method according to claim 8 or 9, characterized in that, before forming the first metal thin film, the method further comprises: forming a transparent conductive layer through a one-time composition process; the first metal film is directly formed above the transparent conducting layer;
while forming the source electrode and the drain electrode, the method further includes: forming an auxiliary electrode; the auxiliary electrode is electrically connected with the top gate electrode through a via hole and is electrically connected with the transparent conducting layer through a via hole; the orthographic projection of the transparent conducting layer on the substrate covers the orthographic projection of the active layer on the substrate.
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