CN108520880A - Three-dimensional storage and its manufacturing method - Google Patents
Three-dimensional storage and its manufacturing method Download PDFInfo
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- CN108520880A CN108520880A CN201810417746.0A CN201810417746A CN108520880A CN 108520880 A CN108520880 A CN 108520880A CN 201810417746 A CN201810417746 A CN 201810417746A CN 108520880 A CN108520880 A CN 108520880A
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
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Abstract
The present invention relates to technical field of manufacturing semiconductors more particularly to a kind of three-dimensional storage and its manufacturing methods.The three-dimensional storage includes：Storage region, including at least one block memory block；Identify structure, including at least one mark；The mark is positioned at the storage region or positioned at the periphery of the storage region, for indicating address of the storage region in the three-dimensional storage.The present invention can quickly navigate to destination address, greatly improve work efficiency and position success rate, reduce the cost of failure analysis.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors more particularly to a kind of three-dimensional storage and its manufacturing methods.
Background technology
With the development of technology, semi-conductor industry is constantly sought new mode and is produced, so that every in memory device
One memory die has the memory cell of greater number.In the nonvolatile memory, such as nand memory, increase are deposited
A kind of mode of reservoir density is by using vertical memory array, i.e. 3D NAND (three dimensional NAND) memory；With integrated
That spends is higher and higher, and 3D nand memories develop to 64 layers from 32 layers, the even higher number of plies.
Failure analysis is that the mechanism of failure is found out by physical and chemical experiment to ineffective part and theory analysis, propose to reduce or
Eliminate the overall process with failure mechanism correlation failure modes.The design of semiconductor devices, development, production, reliability test and
During quality information feedback etc., it all be unable to do without failure analysis.
During carrying out failure analysis to memory, being accurately positioned for failpoint is a basic premise.It is positioning
In the process, it is often necessary to navigate to a certain piece of memory block (Block), the even specific array common source of some in block memory block
Pole (Array Common Source, ACS).But existing localization method can only be by artificially counting address and in FIB
(forward information database, forwarding information storehouse) opens Mark (label) to be positioned.But artificial number
The mode of address is time-consuming and laborious and error-prone, the time of failure analysis is increased using FIB positioning, and to the one of FIB resources
Kind waste.
Therefore, how to realize and destination address in memory is fast and accurately positioned, be that technology urgently to be resolved hurrily at present is asked
Topic.
Invention content
The present invention provides a kind of three-dimensional storage and its manufacturing method, to realize to destination address in memory quickly,
Accurately positioning, improves the production efficiency of memory.
To solve the above-mentioned problems, the present invention provides a kind of three-dimensional storages, including：
Storage region, including at least one block memory block；
Identify structure, including at least one mark；
The mark is positioned at the storage region or positioned at the periphery of the storage region, for indicating the memory block
Address of the domain in the three-dimensional storage.
Preferably, the three-dimensional storage includes multiple storage regions being arranged in array；The mark structure includes more
A mutually different mark, the multiple mutually different mark is corresponded with the multiple storage region, each to indicate
Address of the storage region in the three-dimensional storage.
Preferably, the mark includes an at least sub-mark, and the sub-mark is used to indicate the block in the storage region
Address of the memory block in the three-dimensional storage.
Preferably, described piece of memory block includes several finger memory blocks made of grid line separate slot Division；
The three-dimensional storage further includes：Positioned at the spaced grid of several layers for referring to memory block；
Array common source positioned at grid line separate slot area.
Preferably, the sub-mark is located at the finger memory block；Alternatively, the sub-mark is located at grid line separate slot area；
Alternatively, the sub-mark is located at the periphery in grid line separate slot area.
Preferably, it is located at the sub-mark of grid line separate slot area periphery from from the end of the array common source to remote
If the direction from grid described in dried layer extends to form.
Preferably, further include being located at the dielectric layer for referring to memory block, if grid described in dielectric layer covering dried layer；
It is located in the dielectric layer positioned at the sub-mark for referring to memory block.
Preferably, the mark is configured to pattern.
Preferably, the pattern is character.
Preferably, described to be identified as the figuratum graph block of tool.
Preferably, the three-dimensional storage is 3D nand memories.
To solve the above-mentioned problems, the present invention also provides a kind of manufacturing method of three-dimensional storage, include the following steps：
Mark structure, the mark structure are formed in the storage region of the three-dimensional storage or the periphery of storage region
Including at least one mark, for indicating address of the storage region in the three-dimensional storage, the storage region packet
Include at least one block memory block.
Preferably, the mark includes an at least sub-mark, and the sub-mark is used to indicate the block in the storage region
Address of the memory block in the three-dimensional storage.
Preferably, further include following steps：
One piece of memory block is provided；
Described piece of memory block is etched, grid line separate slot area is formed, if described piece of memory block is divided by grid line separate slot area
Dry to refer to memory block, the finger memory block includes the spaced grid of several layers；
Conductive layer is filled in grid line separate slot area, forms array common source.
Preferably, further include the logo slot being connected to the grid line separate slot in grid line separate slot area, the logo slot is described in
If the end of grid line separate slot extends to the direction of grid described in separate dried layer；
The step of forming the sub-mark include：
Conductive layer is deposited, the conductive layer is filled in grid line separate slot area and logo slot, is filled in the logo slot
Conductive layer is as the sub-mark.
Preferably, further include following steps：
Dielectric layer is formed, if grid described in dielectric layer covering dried layer；
The dielectric layer is etched, the sub-mark is formed.
Three-dimensional storage provided by the invention and its manufacturing method, by being set in the periphery of storage region or storage region
The mark structure for including at least one mark is set, to indicate address of the storage region in three-dimensional storage so that staff exists
During failure analysis, destination address can be quickly navigated to, is greatly improved work efficiency and position success rate, is reduced
The cost of failure analysis.
Description of the drawings
Attached drawing 1A is the overlooking structure diagram of three-dimensional storage in the first specific implementation mode of the invention；
Attached drawing 1B is the overlooking structure diagram of block memory block in the first specific implementation mode of the invention；
Attached drawing 2 is the schematic cross-sectional view of three-dimensional storage in the first specific implementation mode of the invention；
Attached drawing 3 is the overlooking structure diagram of three-dimensional storage in the second specific implementation mode of the invention.
Specific implementation mode
The specific implementation mode of three-dimensional storage provided by the invention and its manufacturing method is done in detail below in conjunction with the accompanying drawings
Explanation.
First specific implementation mode
Present embodiment provides a kind of three-dimensional storage, and attached drawing 1A is three in the first specific implementation mode of the invention
The overlooking structure diagram of memory is tieed up, attached drawing 1B is that the plan structure of block memory block in the first specific implementation mode of the invention is shown
It is intended to, attached drawing 2 is the schematic cross-sectional view of three-dimensional storage in the first specific implementation mode of the invention.
In three-dimensional storage, comprising in array in the large scale boxed area (Giant Block) of each bare die (Die)
Multiple pieces of memory blocks (Block) of arrangement, such as 1024 block memory blocks being arranged in array include again in each block memory block
One or more array common source (ACS), since the big polylith memory block in bare die is repetitive structure, in block memory block
Array common source is also repetitive structure, therefore there is no apparent areas between these block memory blocks and corresponding array common source
Point.And during carrying out failure analysis to memory, it needs to be accurately positioned and arrives a certain piece of memory block or some array
Common source, artificial number address and the mode for combining FIB to position, not only time-consuming and laborious at present, but also easily malfunctions, and leads to failure point
Analyse the delay of time and the reduction of accuracy rate.
In order to improve the accuracy rate of failure analysis, and shorten the time of failure analysis, reduces human cost, this specific implementation
Mode provides a kind of three-dimensional storage.Three-dimensional storage in present embodiment can be but not limited to 3D NAND and deposit
Reservoir.As shown in Figure 1A, Figure 1B and Fig. 2, the three-dimensional storage that present embodiment provides, including：Storage region 20 and mark
Know structure.The storage region 20, including at least one block memory block 10.
The mark structure includes at least one mark；The mark is positioned at the storage region 20 or is located at the storage
The periphery in region 20, for indicating address of the storage region 20 in the three-dimensional storage.Wherein, the storage region
20 address in the three-dimensional storage refers to location information of the storage region 20 in the three-dimensional storage.
By increasing the mark structure for indicating storage area address in three-dimensional storage so that staff is right
During three-dimensional storage carries out failure analysis, destination address can fast and accurately be navigated to according to mark structure, greatly
Improve location efficiency and the accuracy rate of failure analysis, save human resources, reduce the waste of FIB resources.
In order to further increase the location efficiency in failure analysis, it is preferred that it is in battle array that the three-dimensional storage, which includes multiple,
Arrange the storage region 20 of arrangement；The mark structure includes multiple mutually different marks, the multiple mutually different mark
It is corresponded with the multiple storage region 20, to indicate address of each storage region 20 in the three-dimensional storage.It is logical
It crosses and several block memory blocks in three-dimensional storage is divided into multiple storage regions, and multiple mutually different marks are set,
It is for the ease of determining corresponding storage region in the three-dimensional storage specifically faster according to the mark
Location.For example, user quickly can navigate to target storage domain according to mark, and then target is navigated to by target storage domain
Block memory block.
Wherein, each storage region can only include a block memory block 10, at this point, the quantity of mark and block memory block 10
Quantity it is equal, to further increase the efficiency of precise positioning；Each storage region can also include multiple pieces of memory blocks 10,
At this point, the quantity of mark is less than the quantity of block memory block 10, so as to simplify the manufacturing process of three-dimensional storage.
Preferably, the mark includes an at least sub-mark, and the sub-mark is for indicating in the storage region 20
Address of the block memory block 10 in the three-dimensional storage.Address of the block memory block in the three-dimensional storage refers to described
Location information of the block memory block in the three-dimensional storage.Using sub-mark structure, storage region can be not only navigated to
Address further can also quickly navigate to the address of block memory block, further improve the efficiency positioned in failure analysis.No
Only in this way, the knowledge of an at least minute mark can also be arranged in those skilled in the art in each sub-mark, the minute mark is known for indicating
Address of the array common source in the three-dimensional storage in described piece of memory block 10.Array common source is in the three-dimensional storage
Address in device refers to location information of the array common source in the three-dimensional storage.Being known by the minute mark can be with
It is directly targeted to Target Aerial Array common source so that location efficiency further increases.
As shown in Figure 1A, 1B, 2, described piece of memory block 10 includes several finger memory blocks made of grid line separate slot Division
(Finger)101；The three-dimensional storage further includes：Positioned at the spaced grid of several layers for referring to memory block 101
1011, and the array common source 102 positioned at grid line separate slot area.Wherein, refer to included in described piece of memory block 10 and deposit
The specific number of storage area 101, can be two or more, present embodiment with described piece of memory block 10 include by
It is illustrated for four finger memory blocks 101 made of three grid line separate slot Divisions.
Described piece of memory block 10 includes the nucleus 201 stored for data and is set around the nucleus 201
The stepped area set.Specifically, the memory block 101 that refers to includes the stacked structure being formed on substrate 22, the stacking knot
Structure includes along the grid 1011 and insulating layer 1012 being alternately stacked perpendicular to the direction of the substrate 22.The stacked structure includes
Step structure area 2021 and nuclear structure area 2011, wherein the step structure area 2021 is located at the end of the stacked structure.
If the step structure area 2021 includes along the dried layer step stacked perpendicular to the direction of the substrate 22, every layer of step has one
A grid/insulating layer pair or multiple grid/insulating layers pair, and grid/insulating layer in lower layer's step to protruding in the horizontal direction
Grid/insulating layer pair in the step of upper layer.The step structure area 2021 is described for being connect with one end of metal plug 23
The other end of metal plug 23 is connect with interconnection structure (not shown).In the stacked structure except the step structure area 2021 it
Outer region is the nuclear structure area 2011, and the nuclear structure area 2011 is used for the storage of data.The stacked structure
For stacking number such as can be 32 layers, 64 layers, the stacking number of stacked structure be more, can more improve the integrated of three-dimensional storage
Degree.It adjacent finger memory block 101 in described piece of memory block 10 is distinguished every and the array common source 102 by the grid line separate slot
It is filled in grid line separate slot area.
In this embodiment, the sub-mark 25 is located at the finger memory block 101.
Specifically, as shown in Fig. 2, the finger memory block 101 further includes dielectric layer 26, the dielectric layer 26 covers several
The layer grid 1011；It is located in the dielectric layer 26 positioned at the sub-mark 25 for referring to memory block.The dielectric layer 26 covers
The stacked structure；The sub-mark 25 can be located in the dielectric layer 26 of 2011 top of the nuclear structure area, also may be used
With in the dielectric layer 26 above the step structure area 2021.
It is identified for the ease of user, it is preferred that described identify with the sub-mark can be pattern.It is furthermore preferred that described
Pattern is character.Alternatively, in order to simplify manufacturing process, it is preferred that the mark can be that tool is figuratum with the sub-mark
Graph block.
To solve the above-mentioned problems, present embodiment additionally provides a kind of manufacturing method of three-dimensional storage.This tool
The structure for the three-dimensional storage that body embodiment manufactures is as shown in Figure 1A, 1B, 2.
The manufacturing method for the three-dimensional storage that present embodiment provides, includes the following steps：
Mark structure, the mark are formed in the storage region 20 of the three-dimensional storage or the periphery of storage region 20
Structure includes at least one mark, for indicating address of the storage region 20 in the three-dimensional storage, the storage
Region 20 includes at least one block memory block 10.
In order to further increase location efficiency, it is preferred that the mark includes an at least sub-mark, and the sub-mark is used for
Indicate address of the block memory block in the three-dimensional storage in the storage region.It, can be direct according to the sub-mark
Object block memory block is navigated to, due to the negligible amounts of array common source in each piece of memory block, and then can also quickly be positioned
To Target Aerial Array common source.
Preferably, the manufacturing method of the three-dimensional storage further includes following steps：
(a) one piece of memory block 10 is provided.Described piece of memory block includes the stacked structure being formed on substrate 22, the stacking
Structure includes along the grid 1011 and insulating layer 1012 being alternately stacked perpendicular to the direction of the substrate 22.
(b) described piece of memory block 10 is etched, forms grid line separate slot area, described piece of memory block 10 is drawn in grid line separate slot area
It is divided into several finger memory blocks 101, the finger memory block 101 includes the spaced grid of several layers 1011.Wherein, described in etching
The specific method of block memory block 10 can be dry etching, can also be wet etching.
(c) filling conductive layer forms array common source 102 in grid line separate slot area.
The step of forming the sub-mark includes the following steps：
(I) dielectric layer 26 is formed, if the dielectric layer 26 covers grid 1011 described in dried layer；
(II) dielectric layer 26 is etched, the sub-mark 25 is formed.
The three-dimensional storage and its manufacturing method that present embodiment provides, by storage region or storage region
Periphery setting comprising at least one mark mark structure, to indicate address of the storage region in three-dimensional storage so that work
Make personnel during failure analysis, can quickly navigate to destination address, greatly improves work efficiency and position successfully
Rate reduces the cost of failure analysis.
Second specific implementation mode
A kind of three-dimensional storage of present embodiment offer and its manufacturing method, attached drawing 3 are that the present invention second is specific real
Apply the overlooking structure diagram of three-dimensional storage in mode.For with the first specific implementation mode something in common, this specific implementation
Mode repeats no more, below the difference of main narration and the first specific implementation mode.
Sub-mark in present embodiment is located at the periphery in grid line separate slot area.As shown in figure 3, block memory block 30 is by institute
It states grid line separate slot zoning and is divided into several finger memory blocks 301, array common source 302 is located at grid line separate slot area.The sub-mark
If 35 from the end of the array common source 302 to the direction of grid described in separate dried layer from extending to form.
The three-dimensional storage further includes the logo slot II being connected to the grid line separate slot I in grid line separate slot area, the mark
If knowing slot II from the end of the grid line separate slot I to the direction of grid described in separate dried layer to extend；Form the sub-mark 35
Step includes：
Conductive layer is deposited, the conductive layer is filled in grid line separate slot area and logo slot II, is filled in the logo slot
II conductive layer is as the sub-mark 35.
In present embodiment, the conductive layer being filled in the grid line separate slot constitutes the array common source
302, the conductive layer in the logo slot is filled in as the sub-mark 35.The array common source 302 and the sub-mark
35 are completed at the same time in a step depositing operation, greatly simplify the manufacturing step of three-dimensional storage, improve three-dimensional storage
Production efficiency.
Third specific implementation mode
Present embodiment provides a kind of three-dimensional storage and its manufacturing method.For with the first specific implementation mode
Something in common, present embodiment repeat no more, below the difference of main narration and the first specific implementation mode.
Sub-mark in present embodiment is located at grid line separate slot area.Specifically, the block in the three-dimensional storage
Memory block is divided into several finger memory blocks by grid line separate slot zoning；Array common source is filled in grid line separate slot area, the sub- mark
Know positioned at the end of the array common source.
Formed sub-mark the step of include：
Conductive layer is filled in grid line separate slot area, forms array common source；
The end for etching the array common source, forms the sub-mark.
In present embodiment, the finger memory block includes the stacked structure to be formed on substrate, the stacked structure
Include along the grid and insulating layer being alternately stacked perpendicular to the direction of the substrate.Grid line separate slot area is located at the storage of adjacent finger
Between the stacked structure in area and extend the stacked structure, the conductive layer is filled in entire grid line separate slot area, is formed
Array common source.The sub-mark is to perform etching shape by the end for extending the stacked structure to the array common source
At.
The above is only a preferred embodiment of the present invention, it is noted that for the ordinary skill people of the art
Member, various improvements and modifications may be made without departing from the principle of the present invention, these improvements and modifications also should be regarded as
Protection scope of the present invention.
Claims (16)
1. a kind of three-dimensional storage, which is characterized in that including：
Storage region, including at least one block memory block；
Identify structure, including at least one mark；
The mark exists positioned at the storage region or positioned at the periphery of the storage region for indicating the storage region
Address in the three-dimensional storage.
2. three-dimensional storage according to claim 1, which is characterized in that the three-dimensional storage includes multiple in array row
The storage region of cloth；The mark structure includes multiple mutually different marks, it is the multiple it is mutually different mark with it is described
Multiple storage regions correspond, to indicate address of each storage region in the three-dimensional storage.
3. three-dimensional storage according to claim 1, which is characterized in that the mark includes an at least sub-mark, described
Sub-mark is used to indicate address of the block memory block in the three-dimensional storage in the storage region.
4. three-dimensional storage according to claim 3, which is characterized in that described piece of memory block includes by grid line separate slot zoning
Several finger memory blocks made of point；
The three-dimensional storage further includes：Positioned at the spaced grid of several layers for referring to memory block；
Array common source positioned at grid line separate slot area.
5. three-dimensional storage according to claim 4, which is characterized in that the sub-mark is located at the finger memory block；Or
Person, the sub-mark are located at grid line separate slot area；Alternatively, the sub-mark is located at the periphery in grid line separate slot area.
6. three-dimensional storage according to claim 5, which is characterized in that be located at the son of grid line separate slot area periphery
If mark from the end of the array common source to the direction of grid described in separate dried layer from extending to form.
7. three-dimensional storage according to claim 5, which is characterized in that further include being located at the medium for referring to memory block
Layer, if grid described in dielectric layer covering dried layer；
It is located in the dielectric layer positioned at the sub-mark for referring to memory block.
8. three-dimensional storage according to any one of claims 1 to 7, which is characterized in that the mark is configured to pattern.
9. three-dimensional storage according to claim 8, which is characterized in that the pattern is character.
10. three-dimensional storage according to any one of claims 1 to 7, which is characterized in that it is described be identified as tool it is figuratum
Graph block.
11. three-dimensional storage according to claim 1, which is characterized in that the three-dimensional storage is 3DNAND memories.
12. a kind of manufacturing method of three-dimensional storage, which is characterized in that include the following steps：
Mark structure is formed in the storage region of the three-dimensional storage or the periphery of storage region, the mark structure includes
At least one mark, for indicating address of the storage region in the three-dimensional storage, the storage region includes extremely
A few block memory block.
13. the manufacturing method of three-dimensional storage according to claim 12, which is characterized in that the mark includes at least one
Sub-mark, the sub-mark are used to indicate address of the block memory block in the three-dimensional storage in the storage region.
14. the manufacturing method of three-dimensional storage according to claim 13, which is characterized in that further include following steps：
One piece of memory block is provided；
Described piece of memory block is etched, forms grid line separate slot area, described piece of memory block is divided into several fingers by grid line separate slot area
Memory block, the finger memory block include the spaced grid of several layers；
Conductive layer is filled in grid line separate slot area, forms array common source.
15. the manufacturing method of three-dimensional storage according to claim 14, which is characterized in that further include with the grid line every
The logo slot of the grid line separate slot connection in slot area, if the logo slot is from the end of the grid line separate slot to grid described in separate dried layer
Direction extend；
The step of forming the sub-mark include：
Conductive layer is deposited, the conductive layer is filled in grid line separate slot area and logo slot, is filled in the conduction of the logo slot
Layer is used as the sub-mark.
16. the manufacturing method of three-dimensional storage according to claim 14, which is characterized in that further include following steps：
Dielectric layer is formed, if grid described in dielectric layer covering dried layer；
The dielectric layer is etched, the sub-mark is formed.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810417746.0A CN108520880B (en) | 2018-05-04 | 2018-05-04 | Three-dimensional memory and manufacturing method thereof |
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| CN201810417746.0A CN108520880B (en) | 2018-05-04 | 2018-05-04 | Three-dimensional memory and manufacturing method thereof |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05335519A (en) * | 1992-06-02 | 1993-12-17 | Mitsubishi Electric Corp | Semiconductor memory device |
| JPH11135742A (en) * | 1997-10-27 | 1999-05-21 | Nec Kyushu Ltd | Semiconductor device |
| CN106847822A (en) * | 2017-03-08 | 2017-06-13 | 长江存储科技有限责任公司 | 3D nand memories part, manufacture method and step calibration method |
-
2018
- 2018-05-04 CN CN201810417746.0A patent/CN108520880B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05335519A (en) * | 1992-06-02 | 1993-12-17 | Mitsubishi Electric Corp | Semiconductor memory device |
| JPH11135742A (en) * | 1997-10-27 | 1999-05-21 | Nec Kyushu Ltd | Semiconductor device |
| CN106847822A (en) * | 2017-03-08 | 2017-06-13 | 长江存储科技有限责任公司 | 3D nand memories part, manufacture method and step calibration method |
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| CN108520880B (en) | 2020-08-21 |
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