CN108520880B - Three-dimensional memory and manufacturing method thereof - Google Patents
Three-dimensional memory and manufacturing method thereof Download PDFInfo
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- CN108520880B CN108520880B CN201810417746.0A CN201810417746A CN108520880B CN 108520880 B CN108520880 B CN 108520880B CN 201810417746 A CN201810417746 A CN 201810417746A CN 108520880 B CN108520880 B CN 108520880B
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Abstract
The invention relates to the technical field of semiconductor manufacturing, in particular to a three-dimensional memory and a manufacturing method thereof. The three-dimensional memory includes: a storage area including at least one block storage area; an identification structure comprising at least one identification; the mark is positioned in the storage area or at the periphery of the storage area and is used for marking the address of the storage area in the three-dimensional memory. The invention can quickly position the target address, greatly improves the working efficiency and the positioning success rate, and reduces the cost of failure analysis.
Description
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to a three-dimensional memory and a manufacturing method thereof.
Background
As technology develops, the semiconductor industry continues to seek new ways to produce such that each memory die in a memory device has a greater number of memory cells. In non-volatile memories, such as NAND memories, one way to increase memory density is through the use of vertical memory arrays, i.e., 3D NAND (three-dimensional NAND) memories; with higher and higher integration, 3D NAND memories have evolved from 32 layers to 64 layers, and even higher.
Failure analysis is the whole process of reducing or eliminating failure modes related to failure mechanisms by finding out failure mechanisms through physicochemical experiments and theoretical analysis of failed devices. Failure analysis cannot be avoided in the processes of design, development, production, reliability test, quality information feedback and the like of the semiconductor device.
In the failure analysis of a memory, the precise location of the failure point is a basic prerequisite. In the locating process, it is often necessary to locate a certain Block of memory (Block), even a certain specific Array Common Source (ACS) in the Block of memory. However, the conventional positioning method can perform positioning only by opening Mark (Mark) in FIB (forward information database) by an artificial number of addresses. However, the method of counting addresses manually is time-consuming, labor-consuming and error-prone, and the use of FIB positioning increases the time for failure analysis, which is also a waste of FIB resources.
Therefore, how to realize the fast and accurate positioning of the target address in the memory is a technical problem to be solved at present.
Disclosure of Invention
The invention provides a three-dimensional memory and a manufacturing method thereof, which are used for realizing the quick and accurate positioning of a target address in the memory and improving the production efficiency of the memory.
In order to solve the above problems, the present invention provides a three-dimensional memory including:
a storage area including at least one block storage area;
an identification structure comprising at least one identification;
the mark is positioned in the storage area or at the periphery of the storage area and is used for marking the address of the storage area in the three-dimensional memory.
Preferably, the three-dimensional memory comprises a plurality of memory regions arranged in an array; the identification structure comprises a plurality of different identifications, and the different identifications correspond to the storage areas one to indicate the address of each storage area in the three-dimensional memory.
Preferably, the identifier includes at least one sub identifier, and the sub identifier is used to identify an address of a block storage area in the three-dimensional memory.
Preferably, the block storage area comprises a plurality of finger storage areas formed by dividing the grid line partition groove areas;
the three-dimensional memory further includes: several layers of grid electrodes arranged at intervals are positioned in the finger storage area;
and the array common source is positioned in the grid line isolation groove region.
Preferably, the sub-identifier is located in the finger storage area; or, the sub-mark is located in the grid line groove separating region; or, the sub-mark is located at the periphery of the gate line slot region.
Preferably, the sub-mark located at the periphery of the gate line slot region is formed by extending from the tail end of the array common source to a direction away from the plurality of layers of gates.
Preferably, the storage device further comprises a dielectric layer positioned in the finger storage region, and the dielectric layer covers a plurality of layers of the grid electrodes;
the sub-identifier located in the finger storage area is located in the media layer.
Preferably, the indicia is configured as a pattern.
Preferably, the pattern is a character.
Preferably, the mark is a graphic block with a pattern.
Preferably, the three-dimensional memory is a 3D NAND memory.
In order to solve the above problems, the present invention further provides a method for manufacturing a three-dimensional memory, comprising the steps of:
forming an identification structure on a storage area or the periphery of the storage area of the three-dimensional memory, wherein the identification structure comprises at least one identification used for identifying the address of the storage area in the three-dimensional memory, and the storage area comprises at least one block storage area.
Preferably, the identifier includes at least one sub identifier, and the sub identifier is used to identify an address of a block storage area in the three-dimensional memory.
Preferably, the method further comprises the following steps:
providing a memory area;
etching the block storage region to form a grid line groove separating region, wherein the grid line groove separating region divides the block storage region into a plurality of finger storage regions, and each finger storage region comprises a plurality of layers of grid electrodes arranged at intervals;
and filling a conducting layer in the grid line isolation groove region to form an array common source.
Preferably, the grid line partition structure further comprises an identification groove communicated with the grid line partition groove of the grid line partition groove region, wherein the identification groove extends from the tail end of the grid line partition groove to the direction far away from the plurality of layers of grids;
the step of forming the sub-identity comprises:
and depositing a conductive layer, wherein the conductive layer is filled in the grid line separating groove area and the identification groove, and the conductive layer filled in the identification groove is used as the sub-identification.
Preferably, the method further comprises the following steps:
forming a dielectric layer, wherein the dielectric layer covers a plurality of layers of the grid electrodes;
and etching the dielectric layer to form the sub-mark.
According to the three-dimensional memory and the manufacturing method thereof, the identification structure comprising at least one identification is arranged on the periphery of the storage area or the storage area to indicate the address of the storage area in the three-dimensional memory, so that a worker can quickly locate a target address in the failure analysis process, the working efficiency and the locating success rate are greatly improved, and the cost of the failure analysis is reduced.
Drawings
FIG. 1A is a schematic top view of a three-dimensional memory according to a first embodiment of the present invention;
FIG. 1B is a schematic top view of a block storage area according to a first embodiment of the present invention;
FIG. 2 is a schematic cross-sectional structure diagram of a three-dimensional memory according to a first embodiment of the present invention;
fig. 3 is a schematic top view of a three-dimensional memory according to a second embodiment of the present invention.
Detailed Description
The following describes in detail a specific embodiment of a three-dimensional memory and a method for manufacturing the same according to the present invention with reference to the accompanying drawings.
First embodiment
Fig. 1A is a schematic top-view structure diagram of a three-dimensional memory according to a first embodiment of the present invention, fig. 1B is a schematic top-view structure diagram of a block storage area according to the first embodiment of the present invention, and fig. 2 is a schematic cross-sectional structure diagram of the three-dimensional memory according to the first embodiment of the present invention.
In the three-dimensional memory, a large-size Block area (Giant Block) of each Die (Die) includes a plurality of Block memory areas (blocks) arranged in an array, for example 1024 Block memory areas arranged in an array, each Block memory area includes one or more Array Common Sources (ACS), and as most of the Block memory areas in the Die are of a repetitive structure and the array common sources in the Block memory areas are of a repetitive structure, no obvious distinction is made between the Block memory areas and the corresponding array common sources. In the process of failure analysis of the memory, a certain storage area or a certain array common source needs to be accurately positioned, and the current mode of manually counting addresses and combining FIB positioning not only wastes time and labor, but also is easy to make mistakes, so that the delay of failure analysis time and the reduction of accuracy are caused.
In order to improve the accuracy of failure analysis, shorten the time of failure analysis, and reduce the labor cost, the present embodiment provides a three-dimensional memory. The three-dimensional memory in this embodiment may be, but is not limited to, a 3D NAND memory. As shown in fig. 1A, 1B and 2, the three-dimensional memory according to the present embodiment includes: a storage area 20 and an identification structure. The storage area 20 includes at least one block storage area 10.
The mark structure comprises at least one mark; the identifier is located in the storage area 20 or at the periphery of the storage area 20, and is used for indicating the address of the storage area 20 in the three-dimensional memory. The address of the storage area 20 in the three-dimensional memory refers to the location information of the storage area 20 in the three-dimensional memory.
By adding the identification structure for marking the address of the storage area in the three-dimensional memory, a worker can quickly and accurately position the target address according to the identification structure in the process of failure analysis of the three-dimensional memory, so that the positioning efficiency and the failure analysis accuracy are greatly improved, the human resources are saved, and the waste of FIB resources is reduced.
In order to further improve the positioning efficiency in the failure analysis, it is preferable that the three-dimensional memory includes a plurality of memory regions 20 arranged in an array; the identification structure includes a plurality of different identifications, and the different identifications correspond to the storage areas 20 one to indicate an address of each storage area 20 in the three-dimensional memory. The specific address of the storage area corresponding to the identifier in the three-dimensional memory is determined more quickly according to the identifier by dividing the block storage areas in the three-dimensional memory into a plurality of storage areas and setting a plurality of different identifiers. For example, the user can quickly locate the target storage area according to the identification, and then locate the target block storage area through the target storage area.
Each storage area may only include one block storage area 10, and at this time, the number of the identifiers is equal to the number of the block storage areas 10, so as to further improve the efficiency of accurate positioning; each memory region may also contain a plurality of block memory regions 10, in which case the number of flags is smaller than the number of block memory regions 10, so that the manufacturing process of the three-dimensional memory can be simplified.
Preferably, the identifier includes at least one sub identifier, and the sub identifier is used to identify an address of the block storage area 10 in the storage area 20 in the three-dimensional memory. The address of the block storage area in the three-dimensional memory refers to the position information of the block storage area in the three-dimensional memory. By adopting the sub-identification structure, the address of the storage area can be positioned, the address of the block storage area can be further and quickly positioned, and the positioning efficiency in failure analysis is further improved. Furthermore, one skilled in the art can set at least one sub-flag in each sub-flag, where the sub-flag is used to indicate the address of the array common source in the block memory area 10 in the three-dimensional memory. The address of the array common source in the three-dimensional memory refers to the position information of the array common source in the three-dimensional memory. The target array common source can be directly positioned through the sub-identifier, so that the positioning efficiency is further improved.
As shown in fig. 1A, 1B, and 2, the block storage area 10 includes a plurality of Finger storage areas (fingers) 101 partitioned by gate line partition areas; the three-dimensional memory further includes: several layers of spaced gates 1011 located in the finger storage region 101, and an array common source 102 located in the gate-line-spacer region. The specific number of the finger storage areas 101 included in the block storage area 10 may be two or more, and this specific embodiment is described by taking an example that the block storage area 10 includes four finger storage areas 101 divided by three gate line partition groove areas.
The block memory area 10 includes a core area 201 for data storage and a step area provided around the core area 201. Specifically, the finger storage region 101 includes a stacked structure formed on a substrate 22, the stacked structure including gate electrodes 1011 and insulating layers 1012 alternately stacked in a direction perpendicular to the substrate 22. The stack structure includes a step structure region 2021 and a core structure region 2011, wherein the step structure region 2021 is located at an end of the stack structure. The step structure region 2021 includes several layers of steps stacked in a direction perpendicular to the substrate 22, each layer of steps has one gate/insulating layer pair or a plurality of gate/insulating layer pairs, and the gate/insulating layer pair in the lower layer of steps protrudes from the gate/insulating layer pair in the upper layer of steps in a horizontal direction. The step structure region 2021 is used to connect with one end of the metal plug 23, and the other end of the metal plug 23 is connected with an interconnect structure (not shown). The region of the stack structure other than the step structure region 2021 is the core structure region 2011, and the core structure region 2011 is used for storing data. The number of stacked layers of the stacked structure may be 32 layers, 64 layers, or the like, for example, and the greater the number of stacked layers of the stacked structure, the more the integration of the three-dimensional memory can be improved. Adjacent finger storage regions 101 in the block storage region 10 are separated by the gate-line slot region, and the array common source 102 is filled in the gate-line slot region.
In this embodiment, the sub identifier 25 is located in the finger storage area 101.
Specifically, as shown in fig. 2, the storage region 101 further includes a dielectric layer 26, and the dielectric layer 26 covers several layers of the gate 1011; the sub-identifier 25 located in the finger storage area is located in the dielectric layer 26. The dielectric layer 26 covers the stacked structure; the sub-mark 25 may be located in the dielectric layer 26 above the core structure region 2011, or may be located in the dielectric layer 26 above the step structure region 2021.
For the convenience of user identification, preferably, the identifier and the sub-identifier may be both patterns. More preferably, the pattern is a character. Alternatively, in order to simplify the manufacturing process, it is preferable that both the mark and the sub-mark may be a pattern block having a pattern.
In order to solve the above problems, the present embodiment also provides a method for manufacturing a three-dimensional memory. The structure of the three-dimensional memory manufactured in the present embodiment is shown in fig. 1A, 1B, and 2.
The method for manufacturing a three-dimensional memory according to the present embodiment includes the steps of:
forming an identification structure on the storage area 20 of the three-dimensional memory or on the periphery of the storage area 20, wherein the identification structure comprises at least one identification for identifying the address of the storage area 20 in the three-dimensional memory, and the storage area 20 comprises at least one block storage area 10.
In order to further improve the positioning efficiency, it is preferable that the identifier includes at least one sub identifier, and the sub identifier is used for identifying an address of a block storage area in the three-dimensional memory. According to the sub-identifiers, the target block storage area can be directly located, and due to the fact that the number of the array common sources in each block storage area is small, the target array common sources can be rapidly located.
Preferably, the method for manufacturing the three-dimensional memory further includes the steps of:
(a) a block of memory 10 is provided. The block storage region includes a stacked structure formed on a substrate 22, the stacked structure including gate electrodes 1011 and insulating layers 1012 alternately stacked in a direction perpendicular to the substrate 22.
(b) And etching the block storage region 10 to form a gate line groove separating region, wherein the gate line groove separating region divides the block storage region 10 into a plurality of finger storage regions 101, and each finger storage region 101 comprises a plurality of layers of gates 1011 arranged at intervals. The specific method for etching the block storage region 10 may be dry etching or wet etching.
(c) And filling a conducting layer in the grid line isolation groove region to form the array common source 102.
The step of forming the sub-identifier comprises the steps of:
forming a dielectric layer 26, wherein the dielectric layer 26 covers a plurality of layers of the grid 1011;
and (II) etching the dielectric layer 26 to form the sub-mark 25.
In the three-dimensional memory and the manufacturing method thereof provided by the specific embodiment, the identification structure including at least one identifier is arranged on the storage area or on the periphery of the storage area to indicate the address of the storage area in the three-dimensional memory, so that a worker can quickly locate a target address in the failure analysis process, the work efficiency and the location success rate are greatly improved, and the cost of the failure analysis is reduced.
Second embodiment
Fig. 3 is a schematic top view structure diagram of a three-dimensional memory according to a second embodiment of the present invention. The same parts as those in the first embodiment will not be described again, and the differences from the first embodiment will be mainly described below.
The sub mark in this embodiment is located at the periphery of the gate line spacer region. As shown in fig. 3, the block storage region 30 is divided into a plurality of finger storage regions 301 by the gate line slot regions, and the array common source 302 is located in the gate line slot regions. The sub-mark 35 is formed by extending from the end of the array common source 302 to a direction away from the layers of the gate.
The three-dimensional memory further comprises an identification groove II communicated with the grid line separation groove I of the grid line separation groove region, and the identification groove II extends from the tail end of the grid line separation groove I to the direction far away from the plurality of layers of grids; the step of forming the sub-identity 35 comprises:
and depositing a conductive layer, wherein the conductive layer is filled in the grid line separating groove area and the identification groove II, and the conductive layer filled in the identification groove II is used as the sub-identification 35.
In this embodiment, the conductive layer filled in the gate line isolation trench constitutes the array common source 302, and the conductive layer filled in the mark trench is used as the sub-mark 35. The array common source 302 and the sub-mark 35 are simultaneously completed in a one-step deposition process, so that the manufacturing steps of the three-dimensional memory are greatly simplified, and the production efficiency of the three-dimensional memory is improved.
Third embodiment
The present embodiments provide a three-dimensional memory and a method of manufacturing the same. The same parts as those in the first embodiment will not be described again, and the differences from the first embodiment will be mainly described below.
The sub mark in this embodiment is located in the gate line spacer region. Specifically, a block storage area in the three-dimensional memory is divided into a plurality of finger storage areas by a grid line partition groove area; the array common source is filled in the grid line isolation groove area, and the sub-mark is positioned at the tail end of the array common source.
The step of forming the sub-identifier comprises:
filling a conducting layer in the grid line isolation groove region to form an array common source;
and etching the tail end of the array common source to form the sub-mark.
In this embodiment, the finger storage region includes a stacked structure formed on a substrate, the stacked structure including gate electrodes and insulating layers alternately stacked in a direction perpendicular to the substrate. The grid line spacer groove area is located between the stacked structures of the adjacent finger storage areas and extends out of the stacked structures, and the conducting layer is filled in the whole grid line spacer groove area to form an array common source. The sub-mark is formed by etching the tail end of the array common source extending out of the stacked structure.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.
Claims (13)
1. A three-dimensional memory, comprising:
the storage area comprises at least one block storage area, and the block storage area comprises a plurality of finger storage areas formed by dividing the grid line partition groove areas;
an identification structure comprising at least one identification;
the mark is positioned in the storage area or at the periphery of the storage area and is used for marking the address of the storage area in the three-dimensional memory;
the identifier comprises at least one sub identifier, and the sub identifier is used for marking the address of a block storage area in the storage areas in the three-dimensional memory;
the sub-identifier is positioned in the finger storage area; or, the sub-mark is located in the grid line groove separating region;
or, the sub-mark is located at the periphery of the gate line slot region.
2. The three-dimensional memory according to claim 1, wherein the three-dimensional memory comprises a plurality of memory regions arranged in an array; the identification structure comprises a plurality of different identifications, and the different identifications correspond to the storage areas one to indicate the address of each storage area in the three-dimensional memory.
3. The three-dimensional memory according to claim 1, further comprising: several layers of grid electrodes arranged at intervals are positioned in the finger storage area;
and the array common source is positioned in the grid line isolation groove region.
4. The three-dimensional memory according to claim 3, wherein the sub-mark located at the periphery of the gate line slot region is formed by extending from the end of the array common source to a direction away from the plurality of layers of the gate.
5. The three-dimensional memory according to claim 3, further comprising a dielectric layer located in the finger storage region, the dielectric layer covering a plurality of layers of the gate;
the sub-identifier located in the finger storage area is located in the media layer.
6. The three-dimensional memory according to any one of claims 1 to 5, wherein the mark is a pattern.
7. The three-dimensional memory according to claim 6, wherein the pattern is a character.
8. The three-dimensional memory according to any one of claims 1 to 5, wherein the mark is a patterned block.
9. The three-dimensional memory according to claim 1, wherein the three-dimensional memory is a 3DNAND memory.
10. A method of fabricating a three-dimensional memory, comprising the steps of:
forming an identification structure on a storage area of the three-dimensional memory or the periphery of the storage area, wherein the identification structure comprises at least one identification used for identifying the address of the storage area in the three-dimensional memory, the storage area comprises at least one block storage area, and the block storage area comprises a plurality of finger storage areas formed by dividing a grid line partition groove area;
the identifier comprises at least one sub identifier, and the sub identifier is used for marking the address of a block storage area in the storage areas in the three-dimensional memory;
the sub-identifier is positioned in the finger storage area; or, the sub-mark is located in the grid line groove separating region;
or, the sub-mark is located at the periphery of the gate line slot region.
11. The method of manufacturing a three-dimensional memory according to claim 10, further comprising the steps of:
providing a memory area;
etching the block storage region to form a grid line groove separating region, wherein the grid line groove separating region divides the block storage region into a plurality of finger storage regions, and each finger storage region comprises a plurality of layers of grid electrodes arranged at intervals;
and filling a conducting layer in the grid line isolation groove region to form an array common source.
12. The method of claim 11, further comprising a mark trench in communication with the gate line spacer trench of the gate line spacer region, the mark trench extending from an end of the gate line spacer trench in a direction away from the plurality of layers of the gate electrode;
the step of forming the sub-identity comprises:
and depositing a conductive layer, wherein the conductive layer is filled in the grid line separating groove area and the identification groove, and the conductive layer filled in the identification groove is used as the sub-identification.
13. The method of manufacturing a three-dimensional memory according to claim 11, further comprising the steps of:
forming a dielectric layer, wherein the dielectric layer covers a plurality of layers of the grid electrodes;
and etching the dielectric layer to form the sub-mark.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| JPH05335519A (en) * | 1992-06-02 | 1993-12-17 | Mitsubishi Electric Corp | Semiconductor memory device |
| JPH11135742A (en) * | 1997-10-27 | 1999-05-21 | Nec Kyushu Ltd | Semiconductor device |
| CN106847822A (en) * | 2017-03-08 | 2017-06-13 | 长江存储科技有限责任公司 | 3D nand memories part, manufacture method and step calibration method |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05335519A (en) * | 1992-06-02 | 1993-12-17 | Mitsubishi Electric Corp | Semiconductor memory device |
| JPH11135742A (en) * | 1997-10-27 | 1999-05-21 | Nec Kyushu Ltd | Semiconductor device |
| CN106847822A (en) * | 2017-03-08 | 2017-06-13 | 长江存储科技有限责任公司 | 3D nand memories part, manufacture method and step calibration method |
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