CN108520726B - Gate drive circuit of ultra-narrow frame - Google Patents
Gate drive circuit of ultra-narrow frame Download PDFInfo
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- CN108520726B CN108520726B CN201810622474.8A CN201810622474A CN108520726B CN 108520726 B CN108520726 B CN 108520726B CN 201810622474 A CN201810622474 A CN 201810622474A CN 108520726 B CN108520726 B CN 108520726B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
- G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
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Abstract
The invention discloses a gate driving circuit with an ultra-narrow frame, which belongs to the technical field of electronics and comprises a multi-stage driving unit, wherein the driving unit comprises an Nth pixel module, a switch module and an (N + 1) th pixel module, N is a positive integer, and the switch module is respectively and electrically connected with the Nth pixel module and the (N + 1) th pixel module. According to the invention, through special pixel design, one gate line is used for driving two rows of pixels, so that half gate wiring is reduced, meanwhile, the GOA unit can be designed by using double height, the width of the GOA unit is indirectly reduced, narrow frame design is realized, and half gate wiring space can be saved for non-GOA products. Meanwhile, as the actual pixels are controlled by 2 TFT switches, the leakage current is small when the TFTs are closed, the voltage holding ratio is high, and lower power consumption can be achieved by using lower frequency drive.
Description
[ technical field ] A method for producing a semiconductor device
The invention relates to the field of electronic circuits, in particular to a gate driving circuit with an ultra-narrow frame.
[ background of the invention ]
With the generalization of products such as mobile phones and the like, the requirements of people on the appearance of the products are increasingly improved, the concepts of full-screen and borderless/narrow-frame screen are also in depth, and low-power-consumption products generally have more grid wires and are difficult to meet the requirements of narrow frames and the like. The occupation of the space of the gate lines often hinders the capacity increase of the capacitor, and therefore, a driving circuit with fewer gate lines needs to be designed. Meanwhile, the narrow frame and the low-power-consumption drive cannot be combined together by the conventional circuit design, so that the requirements of low power consumption, narrow frame and the like cannot be met by the drive circuit and the integrated circuit design.
[ summary of the invention ]
The invention aims to disclose a gate drive circuit with an ultra-narrow frame.A gate line is used for driving two rows of pixels, so that half gate wiring is reduced, a GOA unit can be designed by using double height, the width of the GOA unit is indirectly reduced, the narrow frame design is realized, and half gate wiring space can be saved for non-GOA products; meanwhile, as the actual pixels are controlled by 2 TFT switches, the leakage current is small when the TFTs are closed, the voltage holding ratio is high, and lower power consumption can be achieved by using lower frequency drive.
The technical scheme adopted by the invention is as follows:
a Gate driving circuit of an ultra-narrow bezel, the Gate driving circuit comprising a multi-stage driving unit, the driving unit comprising an Nth pixel module, a switch module and an (N + 1) th pixel module, wherein N is a positive integer, the switch module is electrically connected with the Nth pixel module and the (N + 1) th pixel module respectively, the Nth pixel module is connected with the (N + 1) th pixel module, the switch module is further connected with a Gate terminal, a Source terminal, a first Gcom terminal and a second Gcom terminal respectively, the Nth pixel module is connected with a VCOM terminal, the (N + 1) th pixel module is connected with a VCOM terminal,
the switching module is used for respectively charging the Nth pixel module and the (N + 1) th pixel module at different moments;
and the Nth pixel module and the (N + 1) th pixel module are respectively used for carrying out interaction charging and controlling an external pixel display area according to the signal of the VCOM end and the matching of the switch module.
Further, the switch module comprises a first thin film transistor, a second thin film transistor and a third thin film transistor, wherein the Gate of the second thin film transistor is electrically connected with the Gate end, the drain of the second thin film transistor is electrically connected with the nth pixel module and the (N + 1) th pixel module respectively, the Source of the second thin film transistor is connected with the Source end, the Gate of the first thin film transistor is connected with the first Gcom end, the Source of the first thin film transistor is electrically connected with the drain of the second thin film transistor, the drain of the first thin film transistor is connected with the nth pixel module, the Gate of the third thin film transistor is connected with the second Gcom end, the drain of the third thin film transistor is electrically connected with the drain of the second thin film transistor and the Source of the first thin film transistor, and the Source of the third thin film transistor is.
Furthermore, the nth pixel module comprises a first capacitor and a second capacitor, the first capacitor and the second capacitor are connected in parallel, one end of the first capacitor and one end of the second capacitor are both connected with the VCOM end, and the other end of the first capacitor and the other end of the second capacitor are both connected with the drain electrode of the first thin film transistor.
Furthermore, the (N + 1) th pixel module comprises a third capacitor and a fourth capacitor, the third capacitor and the fourth capacitor are connected in parallel, one end of the third capacitor and one end of the fourth capacitor are both connected with the VCOM end, and the other end of the third capacitor and the other end of the fourth capacitor are both connected with the source electrode of the third thin film transistor.
Further, the first capacitor and the third capacitor are liquid crystal capacitors, and the second capacitor and the fourth capacitor are pixel capacitors.
The technical scheme of the invention has the following advantages:
1. according to the invention, through special pixel design, one gate line is used for driving two rows of pixels, so that half gate wiring is reduced, meanwhile, a GOA unit can be designed by using double height, the width of the GOA unit is indirectly reduced, narrow frame design is realized, and half gate wiring space can be saved for non-GOA products; meanwhile, as the actual pixels are controlled by 2 TFT switches, the leakage current is small when the TFTs are closed, the voltage holding ratio is high, and lower power consumption can be achieved by using lower frequency drive. On the premise of not changing the number of Source lines and the overall pattern, the halving of the gate signal lines can be realized by adding two common signal lines, and one gate line drives two rows of pixels; for GOA products, the number of half of GOAs can be reduced, so that the height of a GOA unit is increased, and the GOA design of an ultra-narrow frame is realized; meanwhile, as the actual pixels are controlled by 2 TFT switches, the leakage current is small when the TFTs are closed, the voltage holding ratio is high, the lower driving frequency can be used, and the power consumption can be lower.
2. The number of gate lines can be reduced by half, a narrow frame can be better realized, and meanwhile, the voltage holding and the power consumption are also improved to a certain extent.
[ description of the drawings ]
FIG. 1 is a schematic diagram of a gate driving circuit with ultra-narrow bezel according to an embodiment of the present invention;
FIG. 2 is a block diagram of a gate driving circuit with ultra-narrow bezel according to the present invention;
FIG. 3 is a schematic diagram of a waveform of the present invention;
FIG. 4 is a schematic diagram of a general GOA screen design according to the present invention;
FIG. 5 is a schematic diagram of the general design of the non-GOA screen according to the present invention.
Description of the main elements
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The (N + 1) |
The following detailed description will further illustrate the invention in conjunction with the above-described figures.
[ detailed description ] embodiments
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It is to be understood that the terminology used in the embodiments of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in the examples of the present invention and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.
The terms "including" and "having," and any variations thereof, in the description and claims of this invention and the above-described drawings are intended to cover non-exclusive inclusions. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those steps or elements listed, but may alternatively include other steps or elements not listed, or inherent to such process, method, article, or apparatus.
It is noted that the following detailed description describes embodiments of the invention, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the drawings are illustrative only and should not be construed as limiting the invention.
The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. To simplify the disclosure of the present invention, the components and arrangements of specific examples are described below. Of course, they are merely examples and are not intended to limit the present invention. Furthermore, the present invention may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Referring to fig. 2, which is a block diagram of a gate driving circuit with an ultra-narrow frame according to an embodiment of the present invention, as shown in fig. 2, a driving unit includes an nth pixel module 1, a switch module 2, and an N +1 th pixel module 3, where N is a positive integer. The switch module 2 is electrically connected with the nth pixel module 1 and the (N + 1) th pixel module 3 respectively. The nth pixel module 1 is connected with the (N + 1) th pixel module 3. The switch module 2 is also connected with a Gate terminal, a first Gcom terminal Gcom1, a second Gcom terminal Gcom2 and a Source terminal respectively. The nth pixel module 1 is connected to the VCOM terminal. The (N + 1) th pixel module 3 is connected with a VCOM terminal. The switch module 2 is used for charging the nth pixel module 1 and the (N + 1) th pixel module 3 respectively at different moments. The nth pixel module 1 and the (N + 1) th pixel module 3 are respectively used for carrying out interaction charging and controlling an external pixel display area according to the signal of the switch module 2 and the matching of the switch module.
It can be seen that in the gate driving circuit with an ultra-narrow frame in the technical solution of the embodiment of the present invention, each stage of driving unit includes an nth pixel module, a switch module, and an N +1 th pixel module.
And (3) Gate: the scanning line is connected with the grid electrode of the TFT and controls the switch of the TFT;
source: and the data line is connected with the source electrode or the drain electrode of the TFT and controls the charging and discharging of the pixel capacitor.
Gcom1, Gcom2 are a pair of high frequency clock signals, which are turned on in sequence without overlapping parts
Fig. 1 is a schematic diagram of a gate driving circuit with an ultra-narrow bezel according to an embodiment of the present invention.
Each circuit block is described in detail below.
The switching module 2 includes a first thin film transistor T1, a second thin film transistor T2, and a third thin film transistor T3. The grid electrode of the second thin film transistor T2 is electrically connected with the Gate end, the drain electrode is respectively and electrically connected with the Nth pixel module 1 and the (N + 1) th pixel module 3, and the Source electrode is connected with the Source end. The gate of the first thin film transistor T1 is connected to the first Gcom terminal, and the source is electrically connected to the drain of the second thin film transistor T2. The gate of the third thin film transistor T3 is connected to the second Gcom terminal, and the drain is electrically connected to the drain of the second thin film transistor T2 and the source of the first thin film transistor T1.
The nth pixel module 1 comprises a first capacitor C1 and a second capacitor C2, wherein the first capacitor C1 and the second capacitor C2 are connected in parallel, one end of each of the first capacitor C1 and the second capacitor C2 is connected with a VCOM end, and the other end of each of the first capacitor C1 and the second capacitor C2 is connected with a drain electrode of the first thin film transistor T1.
The (N + 1) th pixel module 3 comprises a third capacitor C3 and a fourth capacitor C4, wherein the third capacitor C3 and the fourth capacitor C4 are connected in parallel, one end of each of the third capacitor C3 and the fourth capacitor C4 is connected with a VCOM end, and the other end of each of the third capacitor C3 and the fourth capacitor C4 is connected with a source electrode of a third thin film transistor T3. The first capacitor and the third capacitor are liquid crystal capacitors, and the second capacitor and the fourth capacitor are pixel capacitors.
The working process is explained according to fig. 3-5 and fig. 1:
due to special pixel structure design, each row of pixels is actually controlled by two signal lines, a Gcom1 signal controls the opening of a T1, a Gcom2 controls the opening of a T3, and a Gate signal controls the opening of an intermediate TFT (T2); in gate scanning, the charging of the pixels in the previous row can be completed only when the T1 and the T2 are simultaneously turned on, and the T2 and the T3 are simultaneously turned on to control the charging of the pixels in the next row; in one frame time, T2 is turned on only once, 2 times the Gcom1/Gcom2 pulse width.
In addition, because the Gcom1/Gcom2 signals are common signals of all pixel rows, actually only 2 gate routing lines need to be added, the gate signals of two rows of pixels can share the common gate routing lines, the number of the gate routing lines can be reduced by about half, the peripheral gate routing lines for non-GOA products can be directly reduced by about half, the GOA design height for GOA products can be directly doubled, the GOA width is indirectly reduced, and the ultra-narrow frame is realized.
Meanwhile, as the actual pixels are controlled by 2 TFT switches, the leakage current is very small when the TFTs are turned off, and the voltage holding ratio is high, the display effect can be ensured, meanwhile, the lower frequency can be used for driving, and the lower power consumption can be realized.
For some products with narrow frame requirements, on the premise of not changing the number of Source lines and the overall structure, two shared signal lines are added to realize half reduction of a gate signal line, and one gate line drives two rows of pixels; for GOA products, the number of half of GOAs can be reduced, so that the height of a GOA unit is increased, and the GOA design of an ultra-narrow frame is realized; meanwhile, as the actual pixels are controlled by 2 TFT switches, the leakage current is small when the TFTs are closed, the voltage holding ratio is high, the lower driving frequency can be used, and the power consumption can be lower.
Note: c1 and C2 are the liquid crystal capacitance and the pixel capacitance of the liquid crystal display, respectively.
Gcom1, Gcom2 are a pair of high frequency clock signals that turn on sequentially without overlapping portions.
A TFT: a thin film transistor;
GOA: gate Driver On Array Gate integrated circuit.
For some products with narrow frame requirements, on the premise of not changing the number of Source lines and the overall structure, two shared signal lines are added to realize half reduction of a gate signal line, and one gate line drives two rows of pixels; for GOA products, the number of half of GOAs can be reduced, so that the height of a GOA unit is increased, and the GOA design of an ultra-narrow frame is realized; meanwhile, as the actual pixels are controlled by 2 TFT switches, the leakage current is small when the TFTs are closed, the voltage holding ratio is high, the lower driving frequency can be used, and the power consumption can be lower.
The basic scheme is as follows: on the premise of keeping the number of Source lines and the overall pattern unchanged, two shared signal lines are added, and then two rows of pixels are driven through gating with one gate line, so that halving of the gate signal lines is achieved, the height of a GOA unit is increased, and GOA design of an ultra-narrow frame is achieved; for non-GOA products, the number of gate wiring is reduced by half, and the peripheral space of the gate can be saved by half.
The circuit source line charges the upper and lower rows of pixels respectively at different moments simultaneously, charges the Nth pixel module when T1 and T2 are turned on simultaneously, charges the (N + 1) th pixel module when T2 and T3 are turned on simultaneously, and connects Gcom1 and Gcom2 with high-frequency clock signals and Gate with a common GOA output signal.
Gcom1 and Gcom2 are connected with high-frequency clock signals, the amplitude is consistent with the Gate, the time before and after the Gate is opened is respectively used for charging the pixels in the upper row and the lower row, and the maximum charging time of each row of pixels is consistent with the Gcom pulse width.
As shown in fig. 4, the GOA circuit is designed in two sides, one GOA output drives two rows of pixels, and N/2 GOA units are required for a screen with N rows of pixels, which is half the number of GOA units compared to the ordinary GOA screen.
As shown in fig. 5, for non-GOA screens, the GOA cells are replaced by normal wires, and the gate wires can be reduced by about half (N/2-2 reduction).
The invention is a Gate line halving driving scheme and simultaneously realizes a lower frequency driving scheme.
The invention has the following beneficial effects:
according to the invention, through special pixel design, one gate line is used for driving two rows of pixels, so that half gate wiring is reduced, meanwhile, a GOA unit can be designed by using double height, the width of the GOA unit is indirectly reduced, narrow frame design is realized, and half gate wiring space can be saved for non-GOA products; meanwhile, as the actual pixels are controlled by 2 TFT switches, the leakage current is small when the TFTs are closed, the voltage holding ratio is high, and lower power consumption can be achieved by using lower frequency drive. On the premise of not changing the number of Source lines and the overall pattern, the halving of the gate signal lines can be realized by adding two common signal lines, and one gate line drives two rows of pixels; for GOA products, the number of half of GOAs can be reduced, so that the height of a GOA unit is increased, and the GOA design of an ultra-narrow frame is realized; meanwhile, as the actual pixels are controlled by 2 TFT switches, the leakage current is small when the TFTs are closed, the voltage holding ratio is high, the lower driving frequency can be used, and the power consumption can be lower. The number of gate lines can be reduced by half, a narrow frame can be better realized, and meanwhile, the voltage holding and the power consumption are also improved to a certain extent.
Finally, it should be noted that the above embodiments are only used for illustrating the technical solutions of the embodiments of the present invention and not for limiting the same, and although the embodiments of the present invention are described in detail with reference to the preferred embodiments, it should be understood by those skilled in the art that modifications or equivalent substitutions can be made on the technical solutions of the embodiments of the present invention, and these modifications or equivalent substitutions cannot make the modified technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.
Claims (4)
1. The utility model provides a gate drive circuit of super narrow frame which characterized in that: the Gate driving circuit comprises a multistage driving unit, the driving unit comprises an Nth pixel module, a switch module and an (N + 1) th pixel module, wherein N is a positive integer, the switch module is respectively and electrically connected with the Nth pixel module and the (N + 1) th pixel module, the Nth pixel module is connected with the (N + 1) th pixel module, the switch module is also respectively connected with a Gate end, a Source end, a first Gcom end and a second Gcom end, the Nth pixel module is connected with a VCOM end, and the (N + 1) th pixel module is connected with the VCOM end, wherein the switch module is used for respectively charging the Nth pixel module and the (N + 1) th pixel module at different moments; the N pixel module and the (N + 1) pixel module are respectively used for carrying out interaction charging and controlling an external pixel display area according to the signal of the VCOM end and the matching of the switch module;
the switch module comprises a first thin film transistor, a second thin film transistor and a third thin film transistor, wherein the grid electrode of the second thin film transistor is electrically connected with a Gate end, the drain electrode of the second thin film transistor is electrically connected with the Nth pixel module and the (N + 1) th pixel module respectively, the Source electrode of the second thin film transistor is connected with a Source end, the grid electrode of the first thin film transistor is connected with a first Gcom end, the Source electrode of the first thin film transistor is electrically connected with the drain electrode of the second thin film transistor, the drain electrode of the first thin film transistor is connected with the Nth pixel module, the grid electrode of the third thin film transistor is connected with a second Gcom end, the drain electrode of the third thin film transistor is electrically connected with the drain electrode of the second thin film transistor and the Source electrode of the first thin.
2. The gate driving circuit of claim 1, wherein: the N pixel module comprises a first capacitor and a second capacitor, the first capacitor and the second capacitor are connected in parallel, one end of the first capacitor and one end of the second capacitor are both connected with a VCOM end, and the other end of the first capacitor and the other end of the second capacitor are both connected with a drain electrode of the first thin film transistor.
3. The gate driving circuit of claim 2, wherein: the N +1 th pixel module comprises a third capacitor and a fourth capacitor, the third capacitor and the fourth capacitor are connected in parallel, one end of the third capacitor and one end of the fourth capacitor are both connected with the VCOM end, and the other end of the third capacitor and the other end of the fourth capacitor are both connected with the source electrode of the third thin film transistor.
4. The gate driving circuit of claim 3, wherein: the first capacitor and the third capacitor are liquid crystal capacitors, and the second capacitor and the fourth capacitor are pixel capacitors.
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| KR20120120761A (en) * | 2011-04-25 | 2012-11-02 | 삼성디스플레이 주식회사 | Liquid crsytal display |
| CN202210402U (en) * | 2011-09-22 | 2012-05-02 | 京东方科技集团股份有限公司 | Driving unit, display panel and liquid crystal display |
| CN103021359B (en) * | 2012-12-10 | 2015-11-25 | 京东方科技集团股份有限公司 | A kind of array base palte and drived control method thereof and display device |
| CN103956131B (en) * | 2014-04-16 | 2017-03-15 | 京东方科技集团股份有限公司 | A kind of pixel-driving circuit and driving method, display floater, display device |
| KR102593456B1 (en) * | 2016-09-30 | 2023-10-24 | 엘지디스플레이 주식회사 | Virtual reality display device and method for driving the same |
| CN206563861U (en) * | 2017-03-28 | 2017-10-17 | 信利半导体有限公司 | The dot structure and liquid crystal display device of a kind of liquid crystal display device |
| CN107991800B (en) * | 2018-01-09 | 2019-10-29 | 昆山龙腾光电有限公司 | Array substrate and liquid crystal display device and driving method |
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