CN109559698A - A kind of GOA circuit - Google Patents
A kind of GOA circuit Download PDFInfo
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- CN109559698A CN109559698A CN201811605197.6A CN201811605197A CN109559698A CN 109559698 A CN109559698 A CN 109559698A CN 201811605197 A CN201811605197 A CN 201811605197A CN 109559698 A CN109559698 A CN 109559698A
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- goa circuit
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
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- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Liquid Crystal Display Device Control (AREA)
Abstract
The present invention relates to field of display technology, more particularly to a kind of GOA circuit, the GOA circuit includes cascade multiple GOA circuit units, first data signal line, second data signal line, N grades of GOA circuit output signal Sn, N grades of gate output signal line Gn, N+2 grades of gate output signal line Gn+2, the thin film transistor (TFT) that multiple groups N-type is connect with p-type.The common signal is also connected with the source electrode of the field-effect tube.By the thin film transistor (TFT) for increasing multiple N-types and p-type in cascade multiple GOA circuits, to realize in the case where grid signal output series is constant, reduce the arrangement of line, reduce the number of GOA circuit, to save layout design space, it realizes the design of ultra-narrow frame panel, and reduces the production cost of product.
Description
Technical field
The present invention relates to field of display technology more particularly to a kind of GOA circuits.
Background technique
GOA (Gate Drive On Array) technology, that is, array substrate row actuation techniques is to utilize thin film transistor (TFT)
Gated sweep driving circuit is produced on film crystal by (Thin Film Transistor, TFT) LCD (Liquid Crystal Display) array processing procedure
On pipe array substrate, to realize the mode of the driving of progressive scan, such design, it can both save the integrated electricity of grid
The cost on road can also reduce the width of panel border, highly beneficial to present ultra-narrow frame design, be that the following panel designs
One important technology.In GOA circuit, it is basic that it has the function of two, first is that exporting scanning drive signal, second is displacement
Function is deposited, after the completion of the output of n-th scanning drive signal, N+1 is carried out by clock control and successively hands on.
However, existing GOA product needs multiple groups clock signal (Clock cycle, CK) when realizing grid signal output
It is also, existing with the collective effect of low frequency signal (Low Complexity, LC) and GOA circuit (18 TFT and capacitors)
The requirement that product charged and resumed ability to GOA circuit is also continuously improved, to wanting for the performance parameters such as frequency, the resolution ratio of device
Ask also higher and higher, the increase of simultaneous number of devices, the size of TFT and the number of clock signal increase, so that circuit
Layout become complicated, the area for placing the panel of circuit also increases accordingly, and the grid frame of available circuit panel is caused to become larger.
Therefore, in existing GOA circuit, circuit number is more and the design layout area of circuit is larger, is unfavorable for face
The design of plate ultra-narrow frame, and the problem of higher cost, it needs to propose further to improve scheme.
Summary of the invention
The present invention provides a kind of GOA circuit, and circuit number is more in GOA circuit to solve in state of the art, circuit
Design layout take up space it is larger, and the problem of higher cost.
In order to solve the above technical problems, technical solution provided by the invention is as follows:
According to the embodiment of the present disclosure, the present invention provides a kind of GOA circuit, the GOA circuit includes:
Cascade multiple GOA circuit units, GOA circuit output signal, selection circuit unit, gate output signal,
N is positive integer, and N grades of GOA circuit units are connect with N grades of GOA circuit output signal line Sn, the N grades of GOA
Circuit output signal line Sn is connect with N grades of selection circuit units, and the N grades of selection circuit units and N grades of grids export
Signal wire Gn and N+2 grades of gate output signal line Gn+2 connections,
Wherein, in selection circuit unit further include: the first data signal line, the second data signal line, multiple groups N-type and p-type
The thin film transistor (TFT) of connection.
According to a preferred embodiment of the invention, in the selection circuit unit further include: the first N-type TFT,
First P-type TFT, the second N-type TFT, the second P-type TFT, first N-type TFT
Drain electrode connects second data signal line, and the grid of first N-type TFT connects the first p-type film crystal
The grid of pipe simultaneously connects the N grades of GOA circuit output signal line Sn, and the source electrode of first N-type TFT connects institute
It states the drain electrode of the first P-type TFT and connects the N grades of gate output signals line Gn, the first p-type film crystal
The source electrode of pipe connects the drain electrode of second N-type TFT and connects first data signal line, and second N-type is thin
The grid of film transistor connects the grid of second P-type TFT and connects the N grades of GOA circuit output signal line
Sn, the source electrode of second N-type TFT connect the drain electrode of second P-type TFT and connect the N+2
The source electrode of grade gate output signal line Gn+2, second P-type TFT connect second data signal line.
According to a preferred embodiment of the invention, the GOA circuit further includes clock control signal line, clock when described
Signal wire processed includes the first clock signal CK1, second clock signal CK2, wherein cascade multiple GOA circuit units are handed over
That replaces is connected with the first clock signal CK1 and second clock signal CK2.
According to a preferred embodiment of the invention, each described GOA circuit unit realizes the output of two grid signals.
According to a preferred embodiment of the invention, there are two direct current signals in the GOA circuit unit.
According to a preferred embodiment of the invention, first data signal line is the direct current signal of voltage -6V.
According to a preferred embodiment of the invention, second data signal line is the direct current signal of voltage 28V.
According to a preferred embodiment of the invention, the width that the domain of the GOA circuit occupies is 500um -1000um.
In conclusion the invention has the benefit that
By being improved to existing circuit, by increasing multiple N-types and p-type in cascade multiple GOA circuits
Thin film transistor (TFT) reduces the arrangement of line, reduces GOA circuit to realize in the case where grid signal output series is constant
Number realizes the design of ultra-narrow frame panel to save layout design area, and reduces the production cost of product.
Detailed description of the invention
It, below will be to embodiment or the prior art in order to illustrate more clearly of embodiment or technical solution in the prior art
Attached drawing needed in description is briefly described, it should be apparent that, the accompanying drawings in the following description is only some of invention
Embodiment for those of ordinary skill in the art without creative efforts, can also be attached according to these
Figure obtains other attached drawings.
Fig. 1 is that the panel grid in the embodiment of the present invention exports schematic diagram；
Fig. 2 is the internal circuit diagram of selection circuit unit in GOA circuit of the present invention；
Fig. 3 is the working timing figure of selection circuit unit in GOA circuit of the present invention.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description.Obviously, described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, those skilled in the art's every other implementation obtained without creative efforts
Example, shall fall within the protection scope of the present invention.
In the description of the present invention, it is to be understood that, term " center ", " longitudinal direction ", " transverse direction ", " length ", " width ",
" thickness ", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outside", etc. instruction
Orientation or positional relationship be based on the orientation or positional relationship shown in the drawings, be merely for convenience of description the present invention and simplification retouch
It states, rather than the device or element of indication or suggestion meaning must have a particular orientation, be constructed and operated in a specific orientation,
Therefore it is not considered as limiting the invention.In addition, term " first ", " second " are used for description purposes only, and cannot understand
For indication or suggestion relative importance or implicitly indicate the quantity of indicated technical characteristic.Define as a result, " first ",
The feature of " second " can explicitly or implicitly include one or more feature.In the description of the present invention, " more
It is a " it is meant that two or more, unless otherwise specifically defined.
In the present embodiment, as shown in FIG. 1, FIG. 1 is the panel grids in the embodiment of the present invention to export schematic diagram.Fig. 1's
In circuit, including, clock control signal line (CK1) 1, clock control signal line (CK2) 2, low frequency reversion AC signal line (LC1)
3, low frequency invert AC signal line (LC2) 4, VSS direct current signal line 5, multistage GOA circuit, with GOA circuit connection and export it is defeated
The multiple film crystal pipe units of signal S1, S2 ... out, and N grades of gate output signal line Gn of output.GOA circuit Gn class
It is similar to the function of a shift register, clock signal passes through clock control signal line 1, clock control signal line 2, low frequency reversion
AC signal line 3 and low frequency invert AC signal line 4, are transferred in GOA circuit Gn, then transmit out grid signal for the first time
Sn at this point, in the present invention, the grid signal of output is not directly inputted in pixel, but is also needed by multiple electricity
Road unit, after the conversion inside each selection circuit unit, it is defeated that each circuit unit exports two grids again
Signal Gn, Gn+2 out.Specifically, grid signal S1 passes through the work of circuit unit after exporting grid signal S1 in GOA circuit 1
With, then grid signal G1, grid signal G3 are exported respectively.
In this way, so that the GOA circuit of every level-one is exported two gate output signals respectively with different signal sequences, because
This, the series of GOA circuit reduces, and the number that can effectively reduce circuit more has so that the space of circuit layout becomes much larger
Conducive to the design of ultra-narrow frame circuit.
As shown in Fig. 2, Fig. 2 is the internal circuit diagram of circuit unit in GOA circuit in Fig. 1 of the present invention.GOA described in every level-one
Circuit includes GOA circuit unit, the first data signal line 1, the second data signal line 2, selection circuit unit 3, in selection circuit
3 inside of unit is specific further include: the first N-type TFT T1, the first P-type TFT T2, the second N-type TFT
T3 and the second P-type TFT T4, gate output signal S1, gate output signal G1, gate output signal G3.
It is formed in selection circuit unit 3 by the either series connection in parallel between multiple N-types and P-type TFT, from
And multiple thin film transistor (TFT)s are integrated.Wherein, the drain electrode of the first N-type TFT T1 connects the second data signal line
The grid of 2, the first N-type TFT T1 connect the grid of the first P-type TFT T2 and connect the 1st grade of GOA electricity
Road output signal S1, the source electrode of the first N-type TFT T1 connect the drain electrode of the first P-type TFT T2 and connection
It is brilliant that the source electrode of the 1st grade of gate output signal line G1, the first P-type TFT T2 connect the second N-type film
The drain electrode of body pipe T3 simultaneously connects first data signal line 1, the grid of the second N-type TFT T3 connection described the
The grid of two P-type TFT T4 simultaneously connects the 1st grade of GOA circuit output signal S1, second N-type TFT
The source electrode of T3 connects the drain electrode of the second P-type TFT T4 and connects the 3rd level gate output signal line G3, described
The source electrode of second P-type TFT T4 connects second data signal line 2.
By the processing of selection circuit unit 3, every level-one GOA circuit realizes the output of two groups of grid signals.Such as Fig. 3
Shown, Fig. 3 is the working timing figure of selection circuit unit in the present invention.Specifically, in first order GOA circuit, the grid of output
Pole signal S1, S1 are direct current signal, and when signal S1 is low level, the first P-type TFT T2 is opened, the first film crystal
Pipe T1 is then closed, at this point, the grid signal G1 exported in first order GOA circuit is the signal of the first data signal line 1；Work as signal
When S1 is high level, the first N-type TFT T1 is opened, and the first P-type TFT T2 is then closed, at this point, first order GOA
The grid signal G1 exported in circuit is the signal of the second data signal line 2.In this way, circuit just completes the defeated of grid signal G1
Artificial situation.
Similarly, in first order GOA circuit, when signal S1 is low level, the second P-type TFT T4 is opened, the 2nd N
Type thin film transistor (TFT) T3 is closed, at this point, the grid signal G3 exported in circuit is the signal of the second data signal line 2；Work as signal
When S1 is high level, the second N-type TFT T3 is opened, and the second P-type TFT T4 is then closed, at this point, defeated in circuit
Grid signal G3 out is the signal of the first data signal line 1.In this way, circuit just completes the output situation of grid signal G3.
In the present invention, it is contemplated that signal and low frequency reversion letter when the threshold voltage and clock of each thin film transistor (TFT)
Number equal influence factor, the voltage of high potential are set as 33V, and the high-potential voltage of grid output is 28V, the first data signal line
It is the direct current signal of -6V on 1, is the direct current signal of 28V on the second data signal line 2, meanwhile, GOA circuit of the invention can be with
Using on the display products such as various high definitions, ultra high-definition, 8K.
By the effect of selection circuit unit 3, S1 outputs two-stage grid signal, that is, realizes the GOA circuit of single grade
The function of exporting two-stage grid signal compares existing 768 grades of GOA circuits in display product, the GOA electricity in the present invention
Number mesh reduces half, it is only necessary to which 384 grades of GOA circuit can be realized as.It further illustrates, if in the GOA of existing panel
In circuit, occupied width be 1000um -2000um, GOA circuit of the invention, due to saving the GOA circuit of half,
Therefore circuit layout width is reduced to 500um -1000um.Therefore, the circuit design of this periphery, for ultra-narrow edge frame product, meeting
It is more advantageous.
From above-described embodiment as can be seen that the design invention a kind of GOA circuit, by cascade multiple GOA circuits
The middle thin film transistor (TFT) for increasing multiple N-types and p-type reduces line to realize in the case where grid signal output series is constant
Arrangement, reduce the number of GOA circuit, to save layout design width, realize the design of ultra-narrow frame panel, and reduce
The production cost of product.
A kind of GOA circuit is provided for the embodiments of the invention above to be described in detail, it is used herein specifically
Principle and implementation of the present invention are described for a example, the present invention that the above embodiments are only used to help understand
Technical solution and its core concept；Those skilled in the art should understand that: it still can be to foregoing embodiments
Documented technical solution is modified or equivalent replacement of some of the technical features；And these are modified or replace
It changes, the range of the technical solution for various embodiments of the present invention that it does not separate the essence of the corresponding technical solution.
Claims (8)
1. a kind of GOA circuit, which is characterized in that including,
Cascade multiple GOA circuit units, GOA circuit output signal line, selection circuit unit, gate output signal line,
N is positive integer, and N grades of GOA circuit units are connect with N grades of GOA circuit output signal line Sn, the N grades of GOA circuits
Output signal line Sn is connect with N grades of selection circuit units, the N grades of selection circuit units and N grades of gate output signals
Line Gn and N+2 grades of gate output signal line Gn+2 connections,
Wherein, in selection circuit unit further include: the first data signal line, the second data signal line, multiple groups N-type are connect with p-type
Thin film transistor (TFT).
2. GOA circuit according to claim 1, which is characterized in that in the selection circuit unit further include: the first N-type
Thin film transistor (TFT), the first P-type TFT, the second N-type TFT, the second P-type TFT, first N-type
The drain electrode of thin film transistor (TFT) connects second data signal line, the grid connection of first N-type TFT described the
The grid of one P-type TFT simultaneously connects the N grades of GOA circuit output signal Sn, first N-type TFT
Source electrode connects the drain electrode of first P-type TFT and connects the N grades of gate output signals line Gn, the first P
The source electrode of type thin film transistor (TFT) connects the drain electrode of second N-type TFT and connects first data signal line, institute
The grid for stating the second N-type TFT connects the grid of second P-type TFT and connects the N grades of GOA electricity
Road output signal Sn, the source electrode of second N-type TFT connect the drain electrode of second P-type TFT and connection
The source electrode of the N+2 grades of gate output signals line Gn+2, second P-type TFT connect second data-signal
Line.
3. GOA circuit according to claim 1, which is characterized in that the GOA circuit further includes clock control signal
Line, the clock control signal line include the first clock signal CK1, second clock signal CK2, wherein described cascade multiple
GOA circuit unit is alternately connected with the first clock signal CK1 and second clock signal CK2.
4. GOA circuit according to claim 1, which is characterized in that each described GOA circuit unit realizes two grids
The output of signal.
5. GOA circuit according to claim 4, which is characterized in that there are two direct current signals in the GOA circuit unit.
6. GOA circuit according to claim 1, which is characterized in that first data signal line is the direct current of voltage -6V
Signal.
7. GOA circuit according to claim 1, which is characterized in that second data signal line is the direct current of voltage 28V
Signal.
8. GOA circuit according to claim 1, which is characterized in that the width that the domain of the GOA circuit occupies is
500um—1000um。
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811605197.6A CN109559698B (en) | 2018-12-26 | 2018-12-26 | GOA circuit |
| PCT/CN2019/083591 WO2020133832A1 (en) | 2018-12-26 | 2019-04-22 | Goa circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811605197.6A CN109559698B (en) | 2018-12-26 | 2018-12-26 | GOA circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109559698A true CN109559698A (en) | 2019-04-02 |
| CN109559698B CN109559698B (en) | 2020-09-01 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201811605197.6A Active CN109559698B (en) | 2018-12-26 | 2018-12-26 | GOA circuit |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN109559698B (en) |
| WO (1) | WO2020133832A1 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109961746A (en) * | 2019-05-06 | 2019-07-02 | 深圳市华星光电半导体显示技术有限公司 | Driving circuit for display screen |
| WO2020133832A1 (en) * | 2018-12-26 | 2020-07-02 | 深圳市华星光电半导体显示技术有限公司 | Goa circuit |
| TWI715159B (en) * | 2019-08-22 | 2021-01-01 | 友達光電股份有限公司 | Display device and wire component |
| US10891902B2 (en) | 2019-05-06 | 2021-01-12 | Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd. | Driving circuit of display device |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103021359A (en) * | 2012-12-10 | 2013-04-03 | 京东方科技集团股份有限公司 | Array substrate and driving control method and display device thereof |
| US20130187837A1 (en) * | 2012-01-19 | 2013-07-25 | Canon Kabushiki Kaisha | Matrix substrate, detecting device, and detecting system |
| CN103943090A (en) * | 2014-04-15 | 2014-07-23 | 深圳市华星光电技术有限公司 | Grid drive circuit and grid drive method |
| CN106297629A (en) * | 2016-08-22 | 2017-01-04 | 武汉华星光电技术有限公司 | Scan drive circuit and there is the flat display apparatus of this circuit |
| CN109003588A (en) * | 2018-08-06 | 2018-12-14 | 深圳市华星光电半导体显示技术有限公司 | Liquid crystal display device |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102881248B (en) * | 2012-09-29 | 2015-12-09 | 京东方科技集团股份有限公司 | Gate driver circuit and driving method thereof and display device |
| CN104700799B (en) * | 2015-03-17 | 2017-09-12 | 深圳市华星光电技术有限公司 | Gate driving circuit and display device |
| KR102461694B1 (en) * | 2015-09-09 | 2022-11-02 | 엘지디스플레이 주식회사 | Finger sensor integrated type display device, method and apparatus of driving the same |
| CN107016971B (en) * | 2017-04-18 | 2020-03-27 | 京东方科技集团股份有限公司 | Scanning circuit unit, grid drive circuit and scanning signal control method |
| CN109559698B (en) * | 2018-12-26 | 2020-09-01 | 深圳市华星光电半导体显示技术有限公司 | GOA circuit |
-
2018
- 2018-12-26 CN CN201811605197.6A patent/CN109559698B/en active Active
-
2019
- 2019-04-22 WO PCT/CN2019/083591 patent/WO2020133832A1/en active Application Filing
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20130187837A1 (en) * | 2012-01-19 | 2013-07-25 | Canon Kabushiki Kaisha | Matrix substrate, detecting device, and detecting system |
| CN103021359A (en) * | 2012-12-10 | 2013-04-03 | 京东方科技集团股份有限公司 | Array substrate and driving control method and display device thereof |
| CN103943090A (en) * | 2014-04-15 | 2014-07-23 | 深圳市华星光电技术有限公司 | Grid drive circuit and grid drive method |
| CN106297629A (en) * | 2016-08-22 | 2017-01-04 | 武汉华星光电技术有限公司 | Scan drive circuit and there is the flat display apparatus of this circuit |
| CN109003588A (en) * | 2018-08-06 | 2018-12-14 | 深圳市华星光电半导体显示技术有限公司 | Liquid crystal display device |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2020133832A1 (en) * | 2018-12-26 | 2020-07-02 | 深圳市华星光电半导体显示技术有限公司 | Goa circuit |
| CN109961746A (en) * | 2019-05-06 | 2019-07-02 | 深圳市华星光电半导体显示技术有限公司 | Driving circuit for display screen |
| CN109961746B (en) * | 2019-05-06 | 2020-09-08 | 深圳市华星光电半导体显示技术有限公司 | Driving circuit for display screen |
| US10891902B2 (en) | 2019-05-06 | 2021-01-12 | Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd. | Driving circuit of display device |
| TWI715159B (en) * | 2019-08-22 | 2021-01-01 | 友達光電股份有限公司 | Display device and wire component |
Also Published As
| Publication number | Publication date |
|---|---|
| CN109559698B (en) | 2020-09-01 |
| WO2020133832A1 (en) | 2020-07-02 |
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