CN108494500B - 1+1 protection type PCM integrated multiplexer circuit based on E1 interface - Google Patents
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- H04B14/02—Transmission systems not characterised by the medium used for transmission characterised by the use of pulse modulation
- H04B14/04—Transmission systems not characterised by the medium used for transmission characterised by the use of pulse modulation using pulse code modulation
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- H—ELECTRICITY
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Abstract
The invention discloses a 1+1 protection type PCM comprehensive multiplexer circuit based on an E1 interface. The invention has the advantages that: the power module supplies power to the transceiver and the SEP optical module, the SEP optical module receives optical signals and converts the optical signals into electric signals to be output to the stabilizing circuit, the stabilizing circuit filters and denoises the electric signals and then outputs the electric signals to the transceiver, the stability of the electric signals received by the transceiver is improved, the transceiver works more stably, the working efficiency of the transceiver is improved, and the service life of the transceiver is prolonged.
Description
Technical Field
The invention relates to the field of signal transmission, in particular to a 1+1 protection type PCM comprehensive multiplexer circuit based on an E1 interface.
Background
European 30-way PCM E1, rate 2.048 Mbit/s. The E1 standard in Europe is adopted in China. One time division multiplexing frame of E1 has a length T of 125us, i.e. a sampling period of 125 μ s is divided into 32 equal time slots, which are numbered CH-CH 31. Wherein the time slot CH0 is used for frame synchronization, the time slot CH16 is used for signaling, and 30 time slots of the rest of CH1-CH15 and CH17-CH31 are used for 30 speech channels. Each slot carries 8 bits and therefore 256 bits are common. 8000 frames per second are transmitted, so that the data rate of the PCM successive group E1 is 2.048 Mbit/s.
The light receiving circuit of the existing PCM comprehensive multiplexer circuit has the defects of low stability and weak interference resistance.
Disclosure of Invention
In view of the defects of the prior art, the invention aims to provide a 1+1 protection type PCM integrated multiplexer circuit based on an E1 interface, which has a high-stability light receiving circuit.
In order to achieve the purpose, the invention provides the following technical scheme: a1 +1 protection type PCM comprehensive multiplexer circuit based on an E1 interface comprises: the power supply module is respectively connected with the transceiver and the SFP optical module and supplies power to the transceiver and the SFP optical module, the stabilizing circuit is connected between the transceiver and the SFP optical module in series and used for converting optical signals into electric signals and outputting the electric signals, and the stabilizing circuit is used for filtering and denoising the electric signals output by the SFP optical module and outputting the electric signals to the transceiver.
As a further improvement of the invention, the transceiver comprises a transceiver chip 2U2 and peripheral circuits thereof, the SFP optical module comprises a receiver chip U1 and peripheral circuits thereof, the stabilizing circuit comprises a resistor 2R5, a resistor 2R6, an inductor 2L6, a capacitor 2C TX 6, an electrolytic capacitor 2EC 6, and the receiver chip U6 comprises pins MOD _ DEF, MOD _ TX _ DEF, MODE _ DEF _ DTD _ 6, GND _ DTX _ DEF _ pins, and ABD _ DEF _ STD _ BEL _ DEF _ SEL _ BEL _ DEF _ PSE _ BEL _ PSE _ PSL, A LOS pin, an RD + pin, an RD-pin and a VCCR pin, wherein the GND pin is grounded, the MOD _ DEF0 pin, the MOD _ DEF1 pin, the MOD _ DEF2 pin and the TX _ FAULT pin are respectively connected with a resistor 2R13, a resistor 2R12, a resistor 2R11 and a resistor 2R10 and then connected with VCC3.3, the TX _ DISABLE pin is grounded, the TD + pin is connected with a resistor 2R5 and then connected with a transceiver chip 2U2, the TD-pin is connected with a resistor 2R6 and then connected with a transceiver chip 2U2, the TD + pin is connected with a capacitor 2C15 and then connected with a resistor 2R23 and then connected with a transceiver chip 2U2, the TD-pin is connected with a capacitor 2C 16C 24 and then connected with a transceiver chip 2U2, the TD + pin and the TD-pin are connected with a resistor 2R22, a connecting point 8742C 15 and a resistor 22 of the capacitor 16 and a resistor 16 is connected with a resistor 16 and a resistor 16, the connection point of the capacitor 2C15 and the resistor 2R7 is connected with a resistor 2R20, the connection point of the capacitor 2C16 and the resistor 2R8 is connected with a resistor 2R21 and then is grounded after being short-circuited with the resistor 2R20, the connection point of the capacitor 2C15 and the resistor 2R23 is connected with the resistor 2R26 and then is connected with the connection point of the capacitor 2C16 and the resistor 2R24, the VCCT pin is connected with an inductor 2L5 and then is connected with VCC3.3, the VCCT pin is connected with an electrolytic capacitor 2EC2 and a capacitor 2C6 which are mutually connected in parallel and then is grounded, the connection point of the inductor 2L5 and VCC3.3 is connected with a capacitor 2C5 and then grounded, the RATE _ SEL pin is connected with a resistor 2R37 and then is connected with VCC3.3, the LOS pin is connected with a resistor 2R14 and then connected with VCC3.3, the RD + pin and the RD-pin are both connected with a chip 2U2, the VCCR pin is connected with an inductor 2L6 and then is connected with VCC3.3, the VCCR pin is connected with an electrolytic capacitor 2EC4 and a capacitor 2C20 which are connected in parallel and then is grounded, and a capacitor 2C19 is connected between the inductor 2L6 and the VCC3.3 and then is grounded.
As a further improvement of the present invention, the power module includes a voltage stabilizing chip 6U1 and a voltage stabilizing chip 6U2, the voltage stabilizing chip 6U1 has a Vin pin, a Vout pin and an ADJ pin, the voltage stabilizing chip 6U2 has a Vin pin, a GND pin, an EN pin, a BYP pin and a Vout pin, the Vin pin of the voltage stabilizing chip 6U1 is connected to ground after being connected with a capacitor 6C2 and an electrolytic capacitor 6EC2 which are connected in parallel with each other, the Vin pin of the voltage stabilizing chip 6U1 is connected to VCC5V, the ADJ pin of the voltage stabilizing chip 6U1 is connected to ground, the Vout pin of the voltage stabilizing chip 6U1 is connected to ground after being connected with an electrolytic capacitor 6EC5 and a capacitor 6C1 which are connected in parallel with each other, the Vin pin of the voltage stabilizing chip 6U1 outputs VCC3.3, the pin of the Vin 84 and the EN pin of the voltage stabilizing chip 6U 373.3, the VCC pin of the voltage stabilizing chip 6U2 is connected to ground after being connected with a capacitor 6C 466C 9 and a capacitor 466C 24 which are connected in parallel with each other, the electrolytic capacitor 6C 466 and the pin of the stabilizing chip 5736 is connected in, the pin Vout of the voltage stabilization chip 6U2 outputs 2.5V, and the pin BYP of the voltage stabilization chip 6U2 is connected with a capacitor 6C10 and then grounded.
As a further improvement of the invention, the VCC5V is connected with a diode 6DV1 and then grounded.
As a further improvement of the present invention, the electrostatic protection module further comprises an electrostatic protection module and an ethernet switching chip 4U2, the electrostatic protection module comprises an electrostatic protection chip 4U3, and the electrostatic protection chip 4U3 is connected between the ethernet switching chip 4U2 and the power supply module.
As a further improvement of the invention, the LED lamp also comprises an indicator light module, wherein the indicator light module comprises three groups of arranged light-emitting diodes, the anodes of the arranged light-emitting diodes are respectively connected with a voltage-dividing resistor and then are connected with VCC3.3 after short circuit, and the cathodes of the arranged light-emitting diodes are connected with a driving chip 3U4 and a driving chip 3U5 and then are connected with a main control chip.
As a further improvement of the invention, the main control chip is connected with a drive chip 9U1 and then connected with a dial switch.
The power supply module supplies power to the transceiver and the SFP optical module, the SFP optical module receives optical signals and converts the optical signals into electric signals to be output to the stabilizing circuit, the stabilizing circuit filters and denoises the electric signals and then outputs the electric signals to the transceiver, the stability of the electric signals received by the transceiver is improved, the transceiver works more stably, the working efficiency of the transceiver is improved, and the service life of the transceiver is prolonged.
Drawings
FIG. 1 is a block flow diagram of the present invention;
fig. 2 is a circuit diagram of the transceiver chip 2U 2;
FIG. 3 is a circuit diagram of the light receiving circuit of FIG. 1;
FIG. 4 is a circuit diagram of the voltage regulator circuit of FIG. 1;
FIG. 5 is a circuit diagram of an electrostatic protection circuit;
fig. 6 is a circuit diagram of the ethernet switch chip 4U 2;
FIG. 7 is a circuit diagram of three banks of LEDs;
FIG. 8 is a circuit diagram of the driver chip 3U4 and the driver chip 3U 5;
fig. 9 is a circuit diagram of the driver chip 9U1 and the dial switch;
fig. 10 is a circuit diagram of the main control chip.
Detailed Description
The invention will be further described in detail with reference to the following examples, which are given in the accompanying drawings.
Referring to fig. 1, fig. 2, fig. 3, fig. 4, fig. 5, fig. 6, fig. 7, fig. 8, and fig. 9, the PCM integrated multiplexer circuit based on the E1 interface 1+1 protection type according to the present embodiment includes: the power supply module 1 is respectively connected with the transceiver 2 and the SFP optical module 4 and supplies power to the transceiver 2 and the SFP optical module 4, the stabilizing circuit 3 is connected between the transceiver 2 and the SFP optical module 4 in series, the SFP optical module 4 is used for converting optical signals into electric signals and outputting the electric signals, and the stabilizing circuit 3 is used for filtering and denoising the electric signals output by the SFP optical module 4 and outputting the electric signals to the transceiver 2.
Through the technical scheme, the power module 1 supplies power to the transceiver 2 and the SFP optical module 4, the SFP optical module 4 receives optical signals and converts the optical signals into electric signals to be output to the stabilizing circuit 3, the stabilizing circuit 3 filters and denoises the electric signals and then outputs the electric signals to the transceiver 2, the stability of the electric signals received by the transceiver 2 is improved, the transceiver 2 works more stably, the working efficiency of the transceiver 2 is improved, and the service life of the transceiver 2 is prolonged.
As a specific embodiment of improvement, the transceiver 2 includes a transceiver chip 2U2 and its peripheral circuit, the SFP optical module 4 includes a receiver chip U1 and its peripheral circuit, the stabilizing circuit 3 includes a resistor 2R5, a resistor 2R6, an inductor 2L6, a capacitor 2C6, an electrolytic capacitor 2EC 6, and the receiver chip U6 includes a pin MOD, a pin MOD _ pin, a pin d _ TX _ 6, a pin d _ TX _ tfd _ tff _ 6, a pin, a RATE _ SEL pin, a LOS pin, an RD + pin, an RD-pin and a VCCR pin, wherein the GND pin is grounded, the MOD _ DEF0 pin, the MOD _ DEF1 pin, the MOD _ DEF2 pin and the TX _ FAULT pin are respectively connected with a resistor 2R13, a resistor 2R12, a resistor 2R11 and a resistor 2R10 and then connected with VCC3.3, the TX _ DISABLE pin is grounded, the TD + pin is connected with a resistor 2R5 and then connected with a transceiver chip 2U2, the TD-pin is connected with a resistor 2R6 and then connected with a transceiver chip 2U2, the TD + pin is connected with a capacitor 2C15 and then connected with a resistor 2R23 and then connected with a transceiver chip 2U 639, the TD-pin is connected with a capacitor 2C16 and then connected with a resistor 2R24 and then connected with a transceiver chip 2U2, a resistor 16 and a resistor 16 are connected with a resistor 16 and a resistor 16 after short-16, the connection point of the capacitor 2C15 and the resistor 2R7 is connected with a resistor 2R20, the connection point of the capacitor 2C16 and the resistor 2R8 is connected with a resistor 2R21 and then is grounded after being short-circuited with the resistor 2R20, the connection point of the capacitor 2C15 and the resistor 2R23 is connected with the resistor 2R26 and then is connected with the connection point of the capacitor 2C16 and the resistor 2R24, the VCCT pin is connected with an inductor 2L5 and then is connected with VCC3.3, the VCCT pin is connected with an electrolytic capacitor 2EC2 and a capacitor 2C6 which are mutually connected in parallel and then is grounded, the connection point of the inductor 2L5 and VCC3.3 is connected with a capacitor 2C5 and then grounded, the RATE _ SEL pin is connected with a resistor 2R37 and then is connected with VCC3.3, the LOS pin is connected with a resistor 2R14 and then connected with VCC3.3, the RD + pin and the RD-pin are both connected with a chip 2U2, the VCCR pin is connected with an inductor 2L6 and then is connected with VCC3.3, the VCCR pin is connected with an electrolytic capacitor 2EC4 and a capacitor 2C20 which are connected in parallel and then is grounded, and a capacitor 2C19 is connected between the inductor 2L6 and the VCC3.3 and then is grounded.
Through the technical scheme, the resistor 2R11 and the distributed capacitor form an RC low-pass filter circuit, so that high-frequency harmonics in the data signal are effectively filtered; the resistor 2R12 and the distributed capacitor form an RC low-pass filter circuit, high-frequency harmonics in clock signals are effectively filtered, the resistors 2R10 and 2R13 are arranged to limit current between the transceiver chip 2U2 and the receiver chip U1, and the stability of the circuit is improved. The inductor 2L5, the capacitor 2C5, the capacitor 2C6 and the electrolytic capacitor 2EC2 are arranged for filtering, so that decoupling between a power supply VCC3.3 and a transmitting pin of a receiver chip U1 is realized, and the circuit stability is improved. The inductor 2L6, the capacitor 2C19, the capacitor 2C20 and the electrolytic capacitor 2EC4 are arranged for filtering, so that decoupling between a power supply VCC3.3 and a receiving pin of a receiver chip U1 is realized, and the circuit stability is improved. The resistors 2R5, 2R6, 2R37 and 2R14 are arranged for current limiting, so that the receiver chip U1 is prevented from being damaged by impulse circuit impact, and the service life of the receiver chip U1 is prolonged. TD + and TD-are signal transmission pins, a capacitor 2C15, a capacitor 2C16, a resistor 2R23 and a resistor 2R24 are arranged for current limiting and filtering, the stability of electric signals transmitted to the transceiver chip 2U2 by the receiver chip U1 is further improved, and a resistor 2R26, a resistor 2R22, a resistor 2R7, a resistor 2R8, a resistor 2R20 and a resistor 2R21 are arranged for current limiting, so that the stability and the anti-interference capability of the circuit are improved.
As an improved specific embodiment, the power module 1 includes a voltage stabilizing chip 6U1 and a voltage stabilizing chip 6U2, the voltage stabilizing chip 6U1 has a Vin pin, a Vout pin and an ADJ pin, the voltage stabilizing chip 6U2 has a Vin pin, a GND pin, an EN pin, a BYP pin and a Vout pin, the Vin pin of the voltage stabilizing chip 6U1 is connected with a capacitor 6C2 and an electrolytic capacitor 6EC2 which are connected in parallel to each other and then grounded, the Vin pin of the voltage stabilizing chip 6U1 is connected with a VCC5V, the ADJ pin of the voltage stabilizing chip 6U1 is grounded, the Vout pin of the voltage stabilizing chip 6U1 is connected with an electrolytic capacitor 6EC5 and a capacitor 6C1 which are connected in parallel to each other and then grounded, the Vout pin of the voltage stabilizing chip 6U1 outputs a VCC3.3, the pin of the voltage stabilizing chip Vin 6U2 is connected with an EN pin 3.3, the Vin pin of the voltage stabilizing chip 6U2 is connected with an electrolytic capacitor 6C 3 and the electrolytic capacitor 6C2 which are connected in parallel to ground, the pin Vout of the voltage stabilizing chip 6U2 is connected with a capacitor 6C11 and an electrolytic capacitor 6EC4 which are connected in parallel with each other and then grounded, the pin Vout of the voltage stabilizing chip 6U2 outputs 2.5V, and the pin BYP of the voltage stabilizing chip 6U2 is connected with a capacitor 6C10 and then grounded.
Through the technical scheme, 5V voltage is input into the voltage stabilizing chip 6U1 and then 3.3V is output, 3.3V voltage is input into the voltage stabilizing chip 6U2 and then 2.5V is output, the electrolytic capacitor 6EC2 and the capacitor 6C2 which are mutually connected in parallel are arranged between VCC5V and the Vin pin of the voltage stabilizing chip 6U1, then the stability of the input voltage is improved by grounding, the service life of the voltage stabilizing chip 6U1 is prolonged, the Vout pin of the voltage stabilizing chip 6U1 is connected with the electrolytic capacitor 6EC5 and the capacitor 6C1 which are mutually connected in parallel and then grounded, the output voltage is filtered, the stability of the output voltage is improved, a rear-stage circuit is protected, the Vin pin of the voltage stabilizing chip 6U2 is connected with the electrolytic capacitor 6EC3 and the capacitor 6C9 which are mutually connected in parallel and then grounded, the voltage input into the voltage stabilizing chip 6U2 is filtered, the stability of the input is improved, the service life of the voltage stabilizing chip 6U2 is prolonged, the service life of the voltage stabilizing chip 6U2 is connected with the electrolytic capacitor EC 6C, and burrs in the output voltage are filtered, the output stability is further improved, and a rear-stage circuit is protected.
In a modified specific embodiment, the VCC5V is connected with a diode 6DV1 and then grounded.
Through the technical scheme, the diode 6DV1 is a transient suppression diode, which can be SMBJ6.5A, when two poles of the diode 6DV1 receive reverse transient high-energy impact, the diode changes the high impedance between the two poles into low impedance at the speed of 10 minus 12 times of a second, absorbs the surge power of tens of millions, enables the voltage clamp between the two poles to be at a preset value, and protects precise components in a subsequent electronic circuit from being damaged by various surge pulses.
As an improved specific implementation manner, the power module further comprises an electrostatic protection module 5 and an ethernet switching chip 4U2, wherein the electrostatic protection module 5 comprises an electrostatic protection chip 4U3, and the electrostatic protection chip 4U3 is connected between the ethernet switching chip 4U2 and the power module 1.
Through the technical scheme, when the instantaneous voltage pulse appears in the power supply module 1, the instantaneous voltage pulse firstly passes through the electrostatic protection chip 4U3 and then reaches the Ethernet switch chip 4U2, so that the Ethernet switch chip 4U2 is prevented from being damaged by the instantaneous voltage pulse, the stability of the Ethernet switch chip 4U2 is further improved, the service life of the Ethernet switch chip 4U2 is prolonged, and the user experience is improved.
As a modified embodiment, still including pilot lamp module 8, pilot lamp module 8 is including three group's row type emitting diode, connect VCC3.3 behind the short circuit behind the row type emitting diode positive pole connection divider resistance respectively, connect main control chip 1 behind row type emitting diode negative pole connection driver chip 3U4 and the driver chip 3U 5.
Through above-mentioned technical scheme, set up three group's formation of arranging emitting diode to three groups of formation of arranging emitting diode have red and green, instruct the operating condition of whole circuit, and the user of being convenient for observes and overhauls, and formation of arranging emitting diode compares in that a plurality of diodes of installation are more convenient, and more succinct, and is higher with the shell matching degree, changes the installation shell. Through adding driver chip 3U4 and driver chip 3U5 as being connected between three group's row type emitting diode and main control chip 1, reduce main control chip 1's pin use quantity, change the new function of extension.
As a modified specific embodiment, the main control chip 1 is connected with a driving chip 9U1 and then connected with a dial switch 9.
Through above-mentioned technical scheme, set up dial switch 9, input signal is to main control chip 1 during stirring, and dial switch is 8 bits, can input 256 kinds of different instructions and control and adjust to main control chip 1, satisfies the demand of most instruction quantity, and dial switch 9 is small, and stability is strong, long service life. And dial switch 9 simple to operate, the installation effectiveness is high. Through adding driver chip 9U1 as being connected between dial switch 9 and main control chip 1, reduce main control chip 1's pin use quantity, change the new function of extension.
The above description is only a preferred embodiment of the present invention, and the protection scope of the present invention is not limited to the above embodiments, and all technical solutions belonging to the idea of the present invention belong to the protection scope of the present invention. It should be noted that modifications and embellishments within the scope of the invention may occur to those skilled in the art without departing from the principle of the invention, and are considered to be within the scope of the invention.
Claims (6)
1. A1 +1 protection type PCM comprehensive multiplexer circuit based on an E1 interface is characterized by comprising: the optical transceiver comprises a power module (1), a transceiver (2), a stabilizing circuit (3) and an SFP optical module (4), wherein the power module (4) is respectively connected with the transceiver (2) and the SFP optical module (4) and supplies power to the transceiver (2) and the SFP optical module (4), the stabilizing circuit (3) is connected between the transceiver (2) and the SFP optical module (4) in series, the SFP optical module (4) is used for converting optical signals into electric signals and outputting the electric signals, the stabilizing circuit (3) is used for filtering and denoising the electric signals output by the SFP optical module (4) and outputting the electric signals to the transceiver (2), the transceiver (2) comprises a transceiver chip 2U2 and peripheral circuits thereof, the SFP optical module (4) comprises a receiver chip U1 and peripheral circuits thereof, and the stabilizing circuit (3) comprises a resistor 2R5, a resistor 2R6, a resistor 2R7, a resistor 2R8, a resistor 2R10 and an SFP optical module (4), A resistor 2R, an inductor 2L, a capacitor 2C, an electrolytic capacitor 2EC, the receiver chip U comprises a chip having a GND pin, a MOD DEF pin, a TX FAULT pin, a TX DISABLE pin, a TD + pin, a TD-pin, a VCCT pin, a RATE SEL pin, a LOS pin, an RD + pin, an RD-pin and a VCCR pin, the GND DEF pin, the MOD DEF pin, the TX _ DEF pin and the TX _ FAULT pin are connected to the resistors 2R, the transceiver 2R, the VCC3, the TD + ABU is connected to the ground, the rear end of the TD-pin connecting resistor 2R6 is connected to a transceiver chip 2U2, the rear end of the TD + pin connecting capacitor 2C15 is connected to a transceiver chip 2U2, the rear end of the TD + pin connecting capacitor 2C16 is connected to a transceiver chip 2U2, a resistor 2R22 is connected between the TD + pin and the TD-pin, a resistor 2R7 is coupled to a connection point of the capacitor 2C15 and the resistor 2R22, a resistor 2R 16 is coupled to a connection point of the capacitor 2C16 and the resistor 2R 16 and then is shorted with the resistor 2R 16 and then is connected with a 3.3VAT 16, a resistor 2R 16 is connected to a connection point of the capacitor 2C16 and the resistor 2R 16 and then is shorted with the capacitor 2R 16 and then is grounded, and a connection point of the capacitor 2C16 and the resistor 2R 16 is connected with the rear end of the resistor 16 and the capacitor 2R 16, the VCCT pin is connected with and connects VCC3.3 behind inductance 2L5, the VCCT pin is connected with ground connection behind parallelly connected electrolytic capacitor 2EC2 and electric capacity 2C6 each other, inductance 2L5 is connected with electric capacity 2C5 back ground connection with VCC 3.3's tie point, RATE _ SEL foot connecting resistance 2R37 back ground connection VCC3.3, LOS foot connecting resistance 2R14 back ground connection VCC3.3, RD + foot and RD-foot all are connected to chip 2U2, the VCCR pin is connected with and connects VCC3.3 behind inductance 2L6, the VCCR pin is connected with ground connection behind parallelly connected electrolytic capacitor 2EC4 and electric capacity 2C20 each other, be connected with electric capacity 2C19 back ground connection between inductance 2L6 and VCC 3.3.
2. The protected PCM integrated multiplexer circuit based on E1 interface 1+1 as claimed in claim 1, wherein: the power supply module (4) comprises a voltage stabilizing chip 6U1 and a voltage stabilizing chip 6U2, the voltage stabilizing chip 6U1 is provided with a Vin pin, a Vout pin and an ADJ pin, the voltage stabilizing chip 6U2 is provided with a Vin pin, a GND pin, an EN pin, a BYP pin and a Vout pin, the Vin pin of the voltage stabilizing chip 6U1 is connected with a capacitor 6C2 and an electrolytic capacitor 6EC2 which are connected in parallel with each other and then grounded, the Vin pin of the voltage stabilizing chip 6U1 is connected with a V, the ADJ pin of the voltage stabilizing chip 6U1 is grounded, the Vout pin of the voltage stabilizing chip 6U1 is connected with an electrolytic capacitor 6EC5 and a capacitor 6C1 which are connected in parallel with each other and then grounded, the Vout pin of the voltage stabilizing chip 6U1 outputs VCC3.3, the pin Vin and the EN pin of the voltage stabilizing chip 6U2 are connected with a VCC3.3, the pin of the voltage stabilizing chip 6U2 is connected with a capacitor 6C9 and an electrolytic capacitor 6C 466C 3 which are connected in parallel with each other and then grounded, the electrolytic capacitor 6C 466C 24 and the electrolytic capacitor 6C 5736C, the pin Vout of the voltage stabilization chip 6U2 outputs 2.5V, and the pin BYP of the voltage stabilization chip 6U2 is connected with a capacitor 6C10 and then grounded.
3. The protected PCM integrated multiplexer circuit based on E1 interface 1+1 as claimed in claim 2, wherein: the VCC5V is connected with a diode 6DV1 and then grounded.
4. The protected PCM integrated multiplexer circuit based on E1 interface 1+1 as claimed in claim 3, wherein: the power module further comprises an electrostatic protection module (5) and an Ethernet switch chip 4U2, wherein the electrostatic protection module (5) comprises an electrostatic protection chip 4U3, and the electrostatic protection chip 4U3 is connected between the Ethernet switch chip 4U2 and the power module (1).
5. The protected PCM integrated multiplexer circuit based on E1 interface 1+1 as claimed in claim 4, wherein: still including pilot lamp module (8), pilot lamp module (8) are including three group's row type emitting diode, connect VCC3.3 behind the short circuit behind the row type emitting diode positive pole connection divider resistance respectively, connect main control chip (1) behind row type emitting diode negative pole connection driver chip 3U4 and the driver chip 3U 5.
6. The protected PCM integrated multiplexer circuit based on E1 interface 1+1 as claimed in claim 5, wherein: the main control chip (1) is connected with a drive chip 9U1 and then is connected with a dial switch (9).
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| CN201810166754.2A CN108494500B (en) | 2018-02-28 | 2018-02-28 | 1+1 protection type PCM integrated multiplexer circuit based on E1 interface |
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| CN108494500B true CN108494500B (en) | 2021-01-08 |
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| US7079775B2 (en) * | 2001-02-05 | 2006-07-18 | Finisar Corporation | Integrated memory mapped controller circuit for fiber optics transceiver |
| US7463674B2 (en) * | 2003-04-09 | 2008-12-09 | Avago Technologies Fiber Ip (Singapore) Pte. Ltd. | Tables for determining the signal strength of a received signal in a fibre optics transceiver |
| CN1219261C (en) * | 2003-06-30 | 2005-09-14 | 港湾网络有限公司 | Method and apparatus for plugging optical transcreceiving module internal E2 PROM for read broadband network device |
| KR100558309B1 (en) * | 2003-10-09 | 2006-03-10 | 한국전자통신연구원 | Optical module interfacing device and Ethernet system |
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2018
- 2018-02-28 CN CN201810166754.2A patent/CN108494500B/en active Active
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