CN219512363U

CN219512363U - USB switch chip function test circuit

Info

Publication number: CN219512363U
Application number: CN202320594689.XU
Authority: CN
Inventors: 王玮琳; 屠国权
Original assignee: B&P AUTOMATION DYNAMICS Ltd
Current assignee: B&P AUTOMATION DYNAMICS Ltd
Priority date: 2023-03-17
Filing date: 2023-03-17
Publication date: 2023-08-11
Anticipated expiration: 2033-03-17

Abstract

The embodiment of the utility model provides a USB switch chip function test circuit, which relates to the field of USB switch chips; the test chip comprises a USB switch chip unit, a test chip unit module, a singlechip and a communication terminal with a first USB interface, wherein the communication terminal is connected with the singlechip through a serial interface; the input channel is electrically connected to the first USB interface, the first control interface is connected with the second control interface provided by the singlechip, the test chip unit module provides at least one second USB interface, the test chip in the test chip unit is provided with independent IDs, and the output channel and the test chip unit are in one-to-one correspondence through the independent IDs. The serial port communication of the terminal is used for sending an instruction to the singlechip, and the USB switch chip unit is controlled according to the instruction requirement, so that the switch can manage and monitor the condition of the USB port, and when a bad port appears, the port which is the chip has a problem can be accurately judged, so that accurate problem analysis is convenient.

Description

USB switch chip function test circuit

Technical Field

The utility model relates to the field of USB switch chips, in particular to a USB switch chip function test circuit.

Background

The USB is a layered star-shaped bus topological structure taking a host as a center, the software is complex, and the power requirement is high, so that the USB is widely applied to a PC-based system in a period after being pushed out, and is not much applied to an embedded system. However, the USB 2.0 specification published in 2000 increased the speed of the USB interface from 12Mbps to 480Mbps; in 2001, a USB OTG supplementary specification is published, so that an external device can get rid of a PC, and direct communication between any two devices is realized. With these two upgrades, as more and more inexpensive peripherals with USB interfaces are available, more and more embedded system engineers want to apply USB interface technology to the design of embedded systems.

However, upgrading the USB protocol brings problems to the test work of the USB chip: the existing chip is basically integrated with a plurality of modules, and when the whole chip is tested, the chip is provided with a plurality of ports, different test voltages are required to be supplied, and excessive tester resources are occupied; the power supply end on the testing machine is limited, so that the scheme of simultaneous testing of multiple chips is greatly plagued, the current testing machine can only use single-chip testing, the testing time is too long, and the testing cost of the chips is extremely high.

In addition, the prior art can hardly distinguish which port has a problem, and the test circuit can accurately judge which port of the chip has a problem so as to be convenient for accurate problem analysis.

Disclosure of Invention

In view of the foregoing, embodiments of the present utility model have been developed to provide a USB switch chip functional test circuit that overcomes, or at least partially solves, the foregoing problems.

A USB switch chip function test circuit comprises a USB switch chip unit, a test chip unit module, a singlechip and a communication terminal with a first USB interface; the USB switch chip function test circuit provides serial communication connection between the communication terminal and the singlechip;

the USB switch chip unit comprises at least one output channel, one input channel and one first control interface, wherein the input channel is electrically connected to the first USB interface;

the first control interface is connected with a second control interface provided by the singlechip; the test chip unit module provides at least one second USB interface connected with the output channel, and at least comprises a group of test chip units electrically connected with the second USB interface, and each group of test chips in the test chip units have independent IDs;

the output channels and the test chip units are in one-to-one correspondence through the independent IDs.

Preferably, the input channel is provided with ase:Sub>A USB female connector, and the communication terminal is provided with ase:Sub>A USB-A and/or USB-B and/or USB-C connector as ase:Sub>A first USB interface; the USB female connector is electrically connected with the first USB interface through a USB direct connection line or an adapter line.

Preferably, the communication terminal is connected with the singlechip through a UART data line.

Preferably, the communication terminal is a computer device; the computer equipment comprises at least one of a PC, a tablet personal computer, an industrial personal computer and a small computer.

Preferably, the USB female connector is a USB-B type connector; the USB-B type connector is electrically connected with the USB port of the communication terminal through a connecting wire with one end being a USB-B male connector.

Preferably, the input channel includes a first interface circuit;

the first interface circuit includes: a first indication unit connected between a power supply end and a ground end of the first USB interface, and a first inductor connected between the equipment shell ground and the ground end; the first indication unit comprises a first light-emitting diode and a first current-limiting resistor which are sequentially connected, wherein the positive electrode of the first light-emitting diode is connected with the power supply end of the first USB interface, and the negative electrode of the first light-emitting diode is connected with the grounding end;

the data end of the first USB interface is electrically connected with the USB switch chip unit through the positive end and the negative end of USB data of the input channel;

and the second diode and the third diode for voltage stabilization are respectively connected between the positive end and the negative end of the USB data and the grounding end.

Preferably, the inductor further comprises a first common mode inductor;

the positive end and the negative end of the USB data are electrically connected to the USB switch chip unit through the first common mode inductor.

Preferably, the second diode and the third diode are transient suppression diodes.

Preferably, the test chip unit module further comprises a first conversion unit, a maintenance unit and a logic unit;

the output end of the first conversion unit is electrically connected with the input end of the maintenance unit, and the output end of the maintenance unit is electrically connected with the power supply end of the logic unit and is used for supplying power to the logic unit;

the data end of the test chip unit is connected with the output end of the logic unit;

the data end of the logic unit is connected to the data end of the second USB interface.

Preferably, the number of output channels of the USB switch chip units is three, and the number of corresponding test chip units is three, where each output channel is connected to one group of test chip units respectively.

The utility model has the following advantages:

in the embodiment of the utility model, a USB switch chip unit, a test chip unit module, a singlechip and a communication terminal with a first USB interface are used; providing serial communication connection between the communication terminal and the singlechip; the USB switch chip unit comprises at least one output channel, one input channel and one first control interface, wherein the input channel is electrically connected to the first USB interface; the first control interface is connected with a second control interface provided by the singlechip; the test chip unit module provides at least one second USB interface for connecting the output channel, and at least comprises a group of test chip units electrically connected with the second USB interface, and each group of test chips in the test chip units have independent IDs; the output channels and the test chip units are in one-to-one correspondence through the independent IDs. And when the single chip microcomputer receives the instruction, the USB switch chip unit is controlled according to the instruction requirement, so that the switch can manage and monitor the condition of the USB port, and when a bad port appears, the problem of which port of the chip appears can be accurately judged, thereby being convenient for carrying out accurate problem analysis.

Drawings

In order to more clearly illustrate the technical solutions of the present utility model, the drawings that are needed in the description of the present utility model will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present utility model, and that other drawings may be obtained according to these drawings without inventive effort to a person skilled in the art.

FIG. 1 is a schematic diagram of the overall structure of a USB switch chip function test circuit according to an embodiment of the present utility model;

FIG. 2 is a schematic circuit diagram of a first interface unit according to an embodiment of the present utility model;

FIG. 3 is a schematic circuit diagram of a USB switch chip unit according to an embodiment of the present utility model;

FIG. 4 is a schematic circuit diagram of a serial interface in a singlechip according to an embodiment of the utility model;

FIG. 5 is a schematic diagram of a circuit structure for converting internal signals and power of a singlechip according to an embodiment of the utility model;

fig. 6 is a schematic circuit diagram of a test chip unit module according to an embodiment of the utility model.

Reference numerals: 1. a USB switch chip unit; 2. a test chip unit module 3 and a communication terminal; 4. a single chip microcomputer; 11. an input channel; 12. an output channel; 13. a first control interface; 21. a second USB interface; 22. a first conversion unit; 23. a maintenance unit; 24. testing the chip unit; 25. a logic unit; 31. a first USB interface; 32. a first serial communication port; 41. a second serial communication port; 42. and a second control interface.

Detailed Description

In order that the manner in which the above recited objects, features and advantages of the present utility model are obtained will become more readily apparent, a more particular description of the utility model briefly described above will be rendered by reference to the appended drawings. It will be apparent that the described embodiments are some, but not all, embodiments of the utility model. All other embodiments, which can be made by those skilled in the art based on the embodiments of the utility model without making any inventive effort, are intended to be within the scope of the utility model.

It should be noted that, in any embodiment of the present utility model, the USB (Universal Serial Bus ) interface has a power supply terminal and a ground terminal therein for being used as a power supply loop of the USB interface, wherein data+ (d+) and Data- (D-) are Data terminals thereof, and are contacts or contacts for transmitting Data, wherein data+ or d+ is a positive Data terminal, and Data-or D-is a negative Data terminal. USB-C TYPE interfaces, i.e., TYPE-C interfaces.

Referring to fig. 1, a schematic structural diagram of a USB switch chip functional test circuit according to the present utility model is shown, which may specifically include: a USB switch chip unit 1, a test chip unit module 2, a singlechip 4 and a communication terminal 3 with a first USB interface 31; providing serial communication connection between the communication terminal 3 and the singlechip 4; the USB switch chip unit 1 includes at least one output channel 12, one input channel 11 and one first control interface 13, the input channel 11 being electrically connected to the first USB interface 31; the first control interface 13 is connected with a second control interface 42 provided by the singlechip 4; the test chip unit module 2 provides at least one second USB interface 21 for connecting with the output channel 12, and the test chip unit module 2 includes at least one group of test chip units 24 electrically connected with the second USB interface 21, where test chips in each group of test chip units 24 have independent IDs; the output channels 12 and the test chip units 24 are in one-to-one correspondence by the independent IDs.

When the single chip microcomputer receives the instruction, the USB switch chip unit 1 is controlled according to the instruction requirement, so that the switch can manage and monitor the condition of the USB port, especially when the USB port is managed in a multi-channel mode, as the test chip in the unit has an independent ID, the problems of data switching and monitoring in the multi-channel USB when the USB port is provided with the multi-channel USB in the prior art are solved, and the accurate judgment and control of the port can be realized when the bad port is generated. The test circuit of the utility model can accurately judge which port of the chip has the problem so as to be convenient for accurate problem analysis.

Next, the USB switch chip function test circuit in the present exemplary embodiment will be further described.

In the embodiment of the present utility model, the input channel 11 is provided with ase:Sub>A USB female connector, and the communication terminal 3 is provided with ase:Sub>A USB-ase:Sub>A and/or USB-B and/or USB-C connection port; the USB female connector is electrically connected with the connection port through a USB direct connection line or an adapter line.

In ase:Sub>A specific example, when the USB-B female connector provided in the input channel 11 is connected to the above terminal, the USB-B male connector is connected to the communication terminal 3 through ase:Sub>A datase:Sub>A line of ase:Sub>A USB-ase:Sub>A revolution. The USB female connector is a USB-B connector; the USB-B type connector is electrically connected with the USB port of the communication terminal 3 through a connecting wire with one end being a USB-B male connector.

The datase:Sub>A line of the USB-ase:Sub>A revolution USB-B male is ase:Sub>A common USB datase:Sub>A line or USB-B type interface, the USB-B interface is shaped as shown in fig. 2, which can support larger devices such as printers, upstream ports on hubs, or other larger peripherals. And allows connection of peripheral devices without the risk of connecting two hosts to each other.

In the embodiment of the present utility model, the communication terminal 3 is connected with the singlechip 4 through a UART data line.

In one example, as shown in fig. 1, the communication terminal 3 is provided with a first serial communication port 32, and is connected to a second serial communication port 41 provided on the single chip microcomputer 4 through a UART data line. UART (Universal Asynchronous Receiver/Transmitter ) is a universal serial data bus for asynchronous communications. The bus communicates bi-directionally, enabling full duplex transmission and reception. The UART first converts received parallel data into serial data for transmission. The message frame starts with a low start bit followed by 5-8 data bits, an available parity bit and one or more high stop bits. When the receiver discovers the start bit it knows that the data is ready to be transmitted and attempts to synchronize to the transmitter clock frequency. If parity is selected, the UART may append a parity bit to the data bit. Parity bits may be used to aid in error checking. During reception, the UART removes the start and end bits from the message frame, parity the incoming bytes, and converts the data bytes from serial to parallel. The UART also generates additional signals to indicate the status of the transmission and reception. For example, if a parity error is generated, the UART is set to the parity flag.

In the embodiment of the present utility model, the communication terminal 3 is a computer device; the computer equipment comprises a PC, a tablet personal computer, an industrial personal computer and a small computer.

The UART port of the control computer sends an instruction to the singlechip 4, and then the singlechip 4 controls the control pins of the chips in the USB switch chip unit 1 according to the instruction requirement, so that the USB input port of the control pin is communicated with different USB output ports. The USB communication is to test the data path of the USB switch chip, and the UART communication between the single chip 4 and the communication terminal 3 is used to control the working state of the USB switch chip.

The singlechip 4 is connected to the communication terminal 3 (such as a PC) through a UART for communication, and the control interface of the switch chip in the switch chip unit 1 needs to be operated by the singlechip 4 to realize switching of different channels of the USB switch chip. The circuit occupies small space and is not only suitable for expanding a USB interface, but also can be applied to the aspect of testing a USB switch chip.

It should be noted that, when the communication terminal 3 is an intelligent device such as a mobile phone or a tablet computer, the communication terminal can support USB and serial communication through interface conversion and interface multiplexing, for example, the TYPE-C expansion interface device or the VL160 multiplexer, which are both USB TYPE-C TYPE interface multiplexing conversion tools can realize the above USB interface and serial communication.

In the embodiment of the present utility model, as shown in fig. 2, the input channel 11 includes a first interface circuit; the first interface circuit includes: a first indication unit connected between a power supply terminal VBUS and a ground terminal GND of the first USB interface 31, and a first inductance L1 connected between a device case ground QGND and the ground terminal GND; the first indication unit includes a first light emitting diode D1 and a first current limiting resistor R1 that are sequentially connected, wherein an anode of the first light emitting diode D1 is connected to a power supply end VBUS of the first USB interface 31, and a cathode of the first light emitting diode D1 is connected to a ground end GND; wherein, the data terminals (d+ and D-) of the first USB interface 31 are electrically connected with the USB switch chip unit 1 through the positive and negative USB data terminals (d+ and D-) of the input channel 11; and a second diode D2 and a third diode D3 for voltage stabilization are respectively connected between the positive terminal (D+ and D-) of the USB data and the ground terminal GND.

The first filter inductor L1 is connected between the equipment shell ground QGND and the ground end GND, so that circuit ripple can be effectively restrained, and the anti-interference capability is improved. Through D1 as the instruction LED lamp, R1 is the current limiting resistor for instruct this interface whether to switch on the USB, when USB switch on, USB's power supply end VBUS to first diode D1 to current limiting R1 to ground connection GND forms the return circuit.

It should be noted that L1 may be a filter inductor or a magnetic bead, where the magnetic bead has very high resistivity and permeability, and is equivalent to series connection of a resistor and an inductor, but the resistance value and the inductance value all change with frequency. Compared with the common inductor, the high-frequency filter has better high-frequency filter characteristic and is resistive at high frequency, so that higher impedance can be kept in a quite wide frequency range, and the frequency modulation filter effect is improved.

As an example, the second diode D2 and the third diode D3 are transient suppression diodes. D2 and D3 are bi-directional zener diodes, and are called transient voltage suppression diodes (Transient Voltage Suppressor) abbreviated as TVS), characterized in that: when the two poles of the TVS diode are impacted by reverse transient high energy, the high resistance between the two poles can be changed into low resistance at the speed of the magnitude of minus 12 seconds of 10, and the surge power of thousands of watts is absorbed, so that the voltage clamp between the two poles is positioned at a preset value, thereby effectively protecting precise components in an electronic circuit from being damaged by various surge pulses.

Referring to fig. 2, the first common mode inductor U2 is further included; the positive terminal and the negative terminal of the USB data are electrically connected to the USB switch chip unit 1 through the first common mode inductor U2. The common mode inductance (Common mode Choke), also called common mode choke. The common-mode inductance coil is provided with a common-mode inductance coil, two coils are wound on the same iron core, the number of turns and the phase are the same, and the winding is reverse. Thus, when normal current in the circuit flows through the common-mode inductor, the currents generate reverse magnetic fields in the inductance coils wound in the same phase to cancel each other, and at the moment, the normal signal current is mainly influenced by the coil resistance and is slightly damped due to leakage inductance; when common mode current flows through the coil, due to the isotropy of the common mode current, a magnetic field in the same direction is generated in the coil to increase the inductance of the coil, so that the coil presents high impedance, a stronger damping effect is generated, and the common mode current is attenuated, thereby achieving the purpose of filtering.

In a specific example, as shown in fig. 4, in the circuit provided in the single-chip microcomputer 4, a second interface circuit having functions and structures similar to those of the first interface circuit is provided, and the details are not repeated herein with reference to the above embodiment.

In an embodiment of the present utility model, the test chip unit module further includes a first conversion unit 22, a maintenance unit 23, and a logic unit 25; wherein, the output end of the first conversion unit 22 is electrically connected to the input end of the maintaining unit 23, and the output end of the maintaining unit 23 is electrically connected to the power supply end of the logic unit 25, for providing power to the logic unit 25; the data end of the test chip unit 24 is connected with the output end of the logic unit 25; the data terminal of the logic unit 25 is connected to the data terminal of the second USB interface 21.

In an example, the first conversion unit 22 is mainly composed of a first power chip for converting DC5V into dc3.3v and supplying power to the test chip unit 24; the first power supply chip is preferably an LP5907MFX chip, the input end of the first power supply chip is provided with capacitors C24 and C25 for filtering and energy storage, the output end of the first power supply chip is provided with a current-limiting resistor R26 and an energy storage capacitor C23, and the output end of the first power supply chip is also provided with an RC filter between the current-limiting resistor R26 and the energy storage capacitor C23; the EN pin of the single chip microcomputer is connected with an EN signal provided by the single chip microcomputer 4; the voltage outputted from the first power chip is supplied to the maintaining unit 23, and the voltage is processed by the maintaining unit to supply power to the logic unit 25. The maintaining unit 23 includes a resistor R21 and a resistor R23 connected in series, one end of the resistor R21 is connected to the output end of the first power chip, the resistor R21 is further connected in parallel with the capacitor C21 and the emitter and collector of the triode Q2, one end of the resistor R23 is grounded to GND, a resistor R22 is connected between the base and the emitter of the triode Q2 as a pull-up resistor and a current limiting resistor of the MOS transistor Q1, and the gate of the MOS transistor is connected between the resistor R21 and the resistor R23. The circuit is an automatic regulation voltage stabilizing circuit, R3 and C4 filters, and meanwhile, R3 and R4 divide voltage to provide control voltage for Q1 (MOS tube); c4 also has energy storage function, and is Q2 (NPN triode). Working principle and time sequence: 3.3V is non-conductive from the E pole (emitter) to the B pole (base) of the Q2 (the E pole is non-conductive from the C pole when the NPN triode is at the B-pole high level), and at the moment, the G pole control voltage of the Q1 is obtained by dividing the R3 and R4 voltages; when the input voltage (3.3V decreases), the conduction degree of the transistor E to the C pole increases, which is equivalent to the increase of the G pole control voltage of Q1, and increases the conduction degree of Q1, thereby ensuring the voltage stability of the power supply terminal (VCC terminal) of the logic unit 25.

The EN signal is an enable signal, and the EN signal can control the chip to operate or stop operating. In practical situations, when the NPN triode works in the amplifying state, the magnitude of the current of the B pole in the non-conducting state between the E pole and the C pole is inversely proportional, and for convenience of understanding, the above description is given by the saturated state thereof;

in a specific example, the USB switch chip functional test circuit includes a USB switch chip unit 1, a test chip unit module 2, a single chip microcomputer 4, and a communication terminal 3 having a first USB interface 31; providing serial communication connection between the communication terminal 3 and the singlechip 4; the USB switch chip unit 1 includes at least one output channel 12, one input channel 11 and one first control interface 13, the input channel 11 being electrically connected to the first USB interface 31; the first control interface 13 is connected with a second control interface 42 provided by the singlechip 4; the test chip unit module 2 provides at least one second USB interface 21 for connecting with the output channel 12, and the test chip unit module 2 includes at least one group of test chip units 24 electrically connected with the second USB interface 21, where test chips in each group of test chip units 24 have independent IDs; the output channels 12 and the test chip units 24 are in one-to-one correspondence by the independent IDs. Referring to fig. 3, U1 is a USB switch chip in the USB switch chip unit 1, and the purpose of switching control is achieved by receiving EN signal, SEL0 signal and SEL1 signal of the single chip microcomputer 4, and data terminals (d+ and D-) thereof are connected to the first USB interface 31 of the communication terminal 3, which has a plurality of output channels respectively electrically connected to the logic unit 25 and the test chip unit 24 provided in the test chip unit module 2. The EN signal, the SEL0 signal and the SEL1 signal control the switching of the USB channel, where the EN signal is an enable signal, and is connected to the EN pin of the chip, and as shown in fig. 6, the logic unit 25 of the test chip unit module 2 is connected to the USB1 through the level switching channels of the SEL0 signal and the SEL1 signal, specifically, when the SEL0 and the SEL1 are both at low level, the data terminals (d+ and D-); when SEL0 is high and SEL1 is low, the data terminals (D+ and D-) are communicated with USB 2; when SEL0 is low and SEL1 is high, the data terminals (D+ and D-) are communicated with MHL; when SEL0 and SEL1 are both high, the data terminals (d+ and D-) are in a high impedance state with MHL.

In an embodiment of the present utility model, as shown in fig. 5, the single chip microcomputer 4 further has a second indication circuit, which includes a 3.3V power supply current limiting resistor R17 and a light emitting diode D7 connected to the connection port to the ground GND, and forms a loop when connected. It further includes a second conversion unit, and since it is similar to the first conversion unit 22 in function and structure, reference is made to the first conversion unit 22, and thus, a description thereof will not be repeated.

In a specific embodiment, the number of output channels 12 of the USB switch chip unit 1 is three, and the number of corresponding test chip units 24 is three, where each output channel 12 is respectively connected to one group of test chip units 24. The USB ID chips externally connected with the three channels have different ID information, so that whether the functions of each channel of the chip are normal can be accurately judged, and the USB interfaces of the chip are respectively connected to the three output channels of the USB switch chip through the USB interfaces on the test chip so as to realize whether the functions of the three different channels of the USB switch chip are normal. The USB input channel of the USB switch chip is designed as a device connected with the female port of the USB-B, and is connected to the computer end through a male data line of the USB-B so as to realize the communication function with the computer. In addition, the control interface of the USB switch chip needs to be operated by a singlechip to realize the switching of different channels of the USB switch chip. The singlechip is connected to the computer end through a UART for communication.

While preferred embodiments of the present utility model have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiment and all such alterations and modifications as fall within the scope of the embodiments of the utility model.

Finally, it is further noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or terminal that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or terminal. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article or terminal device comprising the element.

The above describes the USB switch chip functional test circuit provided by the present utility model in detail, and specific examples are applied to illustrate the principles and embodiments of the present utility model, and the above description of the examples is only used to help understand the method and core idea of the present utility model; meanwhile, as those skilled in the art will have variations in the specific embodiments and application scope in accordance with the ideas of the present utility model, the present description should not be construed as limiting the present utility model in view of the above.

Claims

1. The USB switch chip function test circuit is characterized by comprising a USB switch chip unit, a test chip unit module, a singlechip and a communication terminal with a first USB interface; the USB switch chip function test circuit provides serial communication connection between the communication terminal and the singlechip;

2. The USB switch chip functional test circuit of claim 1, wherein the input channel is provided with ase:Sub>A USB female connector, and the communication terminal is provided with ase:Sub>A USB-ase:Sub>A and/or USB-B and/or USB-C connector as ase:Sub>A first USB interface; the USB female connector is electrically connected with the first USB interface through a USB direct connection line or an adapter line.

3. The USB switch chip functional test circuit of claim 1, wherein the communication terminal is connected to the single chip microcomputer through a UART data line.

4. A USB switch chip functional test circuit according to any one of claims 1 to 3, wherein the communications terminal is a computer device; the computer equipment comprises at least one of a PC, a tablet personal computer, an industrial personal computer and a small computer.

5. The USB switch chip functional test circuit of claim 2, wherein the USB female connector is a USB-B type connector; the USB-B type connector is electrically connected with the USB port of the communication terminal through a connecting wire with one end being a USB-B male connector.

6. The USB switch chip functional test circuit of claim 1, wherein the input channel includes a first interface circuit;

7. The USB switch chip functional test circuit of claim 6, further comprising a first common mode inductance;

8. The USB switch chip functional test circuit of claim 6, wherein the second diode and the third diode are transient suppression diodes.

9. The USB switch chip functional test circuit of claim 1, wherein the test chip unit module further includes a first conversion unit, a maintenance unit, and a logic unit;

10. The USB switch chip functional test circuit of claim 1, wherein the number of output channels of the USB switch chip units is three, and the number of corresponding test chip units is three, wherein each output channel is respectively connected to one group of test chip units.