CN113452445B

CN113452445B - Centralized gigabit Ethernet optical transceiver

Info

Publication number: CN113452445B
Application number: CN202110675260.9A
Authority: CN
Inventors: 余清华; 李统孝; 凌秋立; 吴益伟; 陈宣林; 郑晓
Original assignee: Zhejiang Hengjie Communication Technology Co ltd
Current assignee: Zhejiang Hengjie Communication Technology Co ltd
Priority date: 2021-06-17
Filing date: 2021-06-17
Publication date: 2022-05-03
Anticipated expiration: 2041-06-17
Also published as: CN113452445A

Abstract

The invention relates to a centralized gigabit Ethernet optical transceiver, which comprises a main control unit, an E1 unit, an Ethernet unit, a telephone unit and an optical module interface device. The main control unit comprises a main control chip, a clock signal jitter attenuation chip, a power-on reset device, a clock attenuation signal configuration module and a dial switch module. The main control chip is respectively connected to the E1 unit, the Ethernet unit, the telephone unit, the optical module interface device, the clock signal jitter attenuation chip and the dial switch module. The clock signal jitter attenuation chip is respectively connected to the clock attenuation signal configuration module and the power-on reset device. The clock attenuation signal configuration module comprises a plurality of anode resistors and cathode resistors, and each signal pin of the clock signal jitter attenuation chip is connected to a VCC power supply end through one anode resistor and is grounded through one cathode resistor. The integrated gigabit Ethernet optical transceiver has high integration level, and achieves the effect of easy expansion and easy upgrading by adopting a modular design.

Description

Centralized gigabit Ethernet optical transmitter and receiver

Technical Field

The present invention relates to an optical transceiver, and more particularly, to a centralized gigabit ethernet optical transceiver.

Background

The optical transceiver is a physical isolation type Ethernet optical fiber transmission device developed for high-definition network cameras, network access control systems and other systems. The 1.5G/2.5G/3.125G transmission rate and CWDM (Coarse Wavelength Division Multiplexer) technology are applied to realize the mixed multiplexing and transmission of gigabit/hundred megaline speed Ethernet data channels, videos and asynchronous data RS 485/422/232. The method can meet the requirements of operators, large customers and private network users on different levels of bandwidth and multi-service access. The existing optical transceiver has the problems of unreasonable circuit design, low integration level, large occupied space and the like.

Disclosure of Invention

In view of the defects in the prior art, on the one hand, a centralized gigabit ethernet optical transceiver is provided, which has a high integration level and adopts a modular design.

In order to achieve the above object, on one hand, the following technical solutions are provided:

a centralized gigabit Ethernet optical transceiver comprises a main control unit, an F1 unit, an Ethernet unit, a telephone unit and an optical module interface device.

The main control unit comprises a main control chip, a clock signal jitter attenuation chip, a power-on reset device, a clock attenuation signal configuration module and a dial switch module.

The main control chip is respectively connected to the E1 unit, the Ethernet unit, the telephone unit, the optical module interface device, the clock signal jitter attenuation chip and the dial switch module.

The clock signal jitter attenuation chip is respectively connected to the clock attenuation signal configuration module and the power-on reset device.

The clock attenuation signal configuration module comprises a plurality of anode resistors and cathode resistors, and each signal pin of the clock signal jitter attenuation chip is connected to a VCC power supply end through one anode resistor and is grounded through one cathode resistor.

To sum up, the following beneficial effects are achieved in the technical scheme: the integrated gigabit Ethernet optical transceiver has high integration level, adopts a modular design to achieve the effect of easy expansion and easy upgrading, and can be configured with service modules with various functions at will according to requirements. And a centralized structural design is adopted, so that the expansion and maintenance are convenient. The conduction and the closing of each port can be controlled at will through the dial switch module.

Drawings

Fig. 1 is a schematic block diagram of a centralized gigabit ethernet optical transceiver;

fig. 2 is a schematic circuit diagram of a dial-up switch module of a centralized gigabit ethernet optical transceiver;

fig. 3 is a schematic circuit diagram of a buck chip of a centralized gigabit ethernet optical transceiver;

fig. 4 is a schematic circuit diagram of an optical module interface device of a centralized gigabit ethernet optical transceiver.

Reference numerals: 10. a main control unit; 11. a main control chip; 12. a clock signal jitter attenuation chip; 13. a power-on restorer; 14. a clock attenuation signal configuration module; 15. a dial switch module; 20. an E1 element; 21. an E1 interface signal receiver; 22. an E1 interface signaling driver; 23. an E1 interface transformer; 30. an Ethernet unit; 31. an Ethernet switch chip; 32. gigabit ethernet transformers; 33. a hundred mega Ethernet interface chip; 34. an Ethernet RJ45 interface chip; 40. a telephone unit; 41. a telephone module connector; 42. a logic signal driving chip; 50. an optical module interface device.

Detailed Description

The present invention will be described in further detail with reference to the accompanying drawings and examples. In which like parts are designated by like reference numerals. It should be noted that the terms "front," "back," "left," "right," "upper" and "lower" used in the following description refer to directions in the drawings, and the terms "bottom" and "top," "inner" and "outer" refer to directions toward and away from, respectively, the geometric center of a particular component.

As shown in fig. 1, a centralized gigabit ethernet optical transceiver includes a main control unit 10, an E1 unit 20, an ethernet unit 30, a telephone unit 40, and an optical module interface device 50; the main control unit 10 comprises a main control chip 11, a clock signal jitter attenuation chip 12, a power-on reset 13, a clock attenuation signal configuration module 14 and a dial switch module 15; the main control chip 11 is respectively connected to the E1 unit 20, the ethernet unit 30, the telephone unit 40, the optical module interface device 50, the clock signal jitter attenuation chip 12 and the dial switch module 15; the clock signal jitter attenuation chip 12 is respectively connected to the clock attenuation signal configuration module 14 and the power-on reset 13; the clock attenuation signal configuration module 14 includes a plurality of positive resistors and negative resistors, and each signal pin of the clock signal jitter attenuation chip 12 is connected to the VCC power supply terminal through one positive resistor and is grounded through one negative resistor. The integrated gigabit Ethernet optical transceiver has high integration level, adopts a modular design to achieve the effect of easy expansion and easy upgrading, and can be configured with service modules with various functions at will according to requirements. And a centralized structural design is adopted, so that the expansion and maintenance are convenient. The conduction and the closing of each port can be controlled arbitrarily by the dial switch module 15. The clock signal jitter attenuation chip 12, the power-on reset 13 and the clock attenuation signal configuration module 14 ensure the stability and reliability of the main control chip 11. The E1 unit 20, the ethernet unit 30, the telephone unit 40, and the optical module interface device 50 are respectively used for providing an E1 interface, an ethernet interface, a telephone interface, and an optical fiber interface, and the units are independent from each other and do not interfere with each other, so that the failure unit can be maintained individually according to different problems when maintenance is needed, and a modification space is provided for individual upgrade of each component in the future.

As shown in fig. 2, the dial switch module 15 includes a register 8U2 and a switch group 8SW 1; the +33V pin of the register is connected to a VCC power supply terminal, the GND pin is connected to ground, the Q8 pin is connected to the main control chip 11, the DS pin is connected to the VCC power supply terminal through a resistor 8R22, the P1 pin, the P2 pin, the P3 pin, the P4 pin, the P5 pin, the P6 pin, the P7 pin and the P8 pin are respectively connected to the first pin, the second pin, the third pin, the fourth pin, the fifth pin, the sixth pin, the seventh pin and the eighth pin of the switch group 8SW1, the ninth pin, the tenth pin, the eleventh pin, the twelfth pin, the thirteenth pin, the fourteenth pin, the fifteenth pin and the sixteenth pin of the switch group 8SW1 are commonly grounded, the P1 pin, the P2 pin, the P3 pin and the P869 pin of the register are respectively connected to the pin 6864A, the pin 3A, the pin 6862A and the pin 1A pin of the RN 8RN3, the pin 5, the pin P53, the pin, the P7 pin, the pin 8 pin and the pin 867 pin of the RN 867 are respectively connected to the pin 1A pin of the RN 867 row of the RN 8, The pin 3A, the pin 2A and the pin 1A, the pin 1B, the pin 2B, the pin 3B and the pin 4B of the resistor bank 8RN3 and the pin 1B, the pin 2B, the pin 3B and the pin 4B of the resistor bank 8RN1 are commonly connected to a VCC power supply terminal. The P/S pin and CLK pin of the register 8U2 are also connected to the light module to indicate the ON or OFF status of the switch set 8SW 1.

The plurality of the registers 8U2 are arranged and connected in series in sequence, the switch group 8SW1 is arranged and corresponds to the registers 8U2 one by one, and each register 8U2 is connected to the DS pin of the register 8U2 connected in series through the Q8 pin. More switch sets 8SW1 can be connected by connecting a plurality of registers 8U2 in series without increasing the number of pins required for the main control chip 11.

The E1 unit 20 comprises an E1 interface signal receiver 21, an E1 interface signal transmission driver 22 and an E1 interface transformer 23; the E1 interface signal receiver 21 is connected to the main control chip 11, and the E1 interface signal transmission driver 22 and the E1 interface transformer 23 are respectively connected to the E1 interface signal receiver 21. The number of the E1 interface signal receivers 21 is 2, the number of the E1 interface signal transmitting drivers 22 is 2 times that of the E1 interface signal receivers 21, and each E1 interface signal receiver 21 is connected with 2E 1 interface signal transmitting drivers 22.

As shown in fig. 3, the ethernet unit 30 includes an ethernet switch chip 31, a gigabit ethernet transformer 32, a gigabit ethernet interface chip 33, and an ethernet RJ45 interface chip 34; the ethernet switch chip 31 is connected to the main control chip 11, and the gigabit ethernet transformer 32, the gigabit ethernet interface chip 33, and the ethernet RJ45 interface chip 34 are respectively connected to the ethernet switch chip 31. The gigabit ethernet transformer 32 can enhance the signal to make the transmission distance longer, and isolate the ethernet switching chip 31 from the outside, so that the anti-interference capability is greatly enhanced, and the chip is greatly protected. The ethernet unit 30 further includes a voltage-reducing chip 4U2 connected to the ethernet switch chip 31, the RUN pins of the voltage-reducing chip 4U2 are connected to the VCC power supply terminal, the positive electrode of the electrolytic capacitor 4EC1 and the VIN pin, the GND pin is connected to the negative electrode of the electrolytic capacitor 4EC1 and the ground, the SW pin is connected to the first end of the inductor 4L1, the VFB pin is connected to the first end of the resistor 4R7, the first end of the resistor 4R8 and the first end of the capacitor 4C40, the second end of the inductor 4L1, the second end of the resistor 4R8 and the second end of the capacitor 4C40 are commonly connected to the ethernet switch chip 31 for providing a 1V power supply thereto, the second end of the resistor 4R7 is grounded, the second end of the inductor 4L1 is also connected to the positive electrode of the electrolytic capacitor 4EC2 and the positive electrode of the electrolytic capacitor 4EC3, and the negative electrode of the electrolytic capacitor 4EC2 and the negative electrode of the electrolytic capacitor 4EC3 are commonly grounded.

The ethernet switch chips 31 are provided in plurality and are all connected to the main control chip 11, and the gigabit ethernet transformers 32 are provided in plurality and are connected to the ethernet switch chips 31 in a one-to-one correspondence. The ethernet switching chips 31 may provide pins for connecting the hundreds of mega ethernet interface chips 33 and the ethernet RJ45 interface chips 34, thereby providing more ethernet interfaces and RJ45 interfaces.

The telephone unit 40 includes a logic signal driving chip 42 and a plurality of telephone module connectors 41, the telephone module connectors 41 are all connected to the main control chip 11, and the logic signal driving chip 42 is connected to the main control chip 11 and each telephone module connector 41. The telephone module connector 41 is used for receiving telephone signals and transmitting the telephone signals to the main control chip 11 through the logic signal driving chip 42.

As shown in fig. 4, the MOD _ DEF0 pin, the MOD _ DEF1 pin, the MOD _ DEF1 pin, and the TX _ FAULT pin of the optical module interface device 50 are connected to the VCC power supply through a resistor 2R44, a resistor 2R43, a resistor 2R42, and a resistor 2R41, respectively, the VEET pin, the TX _ DISABLE pin, and the VEER pin are grounded, respectively, the TD + pin and the TD-pin are connected to the main control chip 11 through a resistor 2R45 and a resistor 2R46, respectively, the VCCT pin is connected to the first terminal of the inductor 2L7, the second terminal of the inductor 2L7 is connected to the VCC power supply, the first terminal of the inductor 2L7 is further connected to the positive terminal of the polar capacitor 2EC5 and the one terminal of the capacitor 2C22, the second terminal of the inductor 2L7 is connected to one terminal of the capacitor 2C21, the negative terminal of the polar capacitor 2EC5, the other terminal of the capacitor 2C22, and the other terminal of the capacitor 2C21 are connected to the VCC pin and the resistor 2R 82 47R 48, the RD + pin and the RD-pin are connected to the main control chip 11 through a resistor 2R49 and a resistor 2R50, respectively, the VCCR pin is connected to a first end of an inductor 2L8, a second end of the inductor 2L8 is connected to a VCC power supply, a first end of the inductor 2L8 is further connected to a positive electrode of a polar capacitor 2EC4 and one end of a capacitor 2C24, a second end of the inductor 2L8 is connected to one end of the capacitor 2C23, and a negative electrode of the polar capacitor 2EC4, the other end of the capacitor 2C24 and the other end of the capacitor 2C23 are grounded together.

The optical module interface device 50 is provided in plurality and is connected to the main control chip 11.

The technical parameters of the interfaces all accord with international or domestic related standards, and the optical fiber interface has 5G optical fiber capacity, high integration level, modular design, easy capacity expansion and easy upgrading, can be randomly configured with the functions of service modules with various functions according to requirements, and simultaneously supports multiple paths of 1000M Ethernet, multiple paths of 100M Ethernet, multiple paths of video, multiple paths of voice, multiple paths of E1, multiple paths of RS485/RS422/RS232 and the like. All ethernet ports are completely physically isolated. Each interface has surge and tertiary lightning protection. Through ITU-TK.20 about lightning impulse, power induction test and power contact test, after circuit impact is released, the circuit can be automatically recovered, and the capacity expansion and maintenance are convenient by adopting a centralized structural design. And user customization and OEM modes are supported. Perfect network management function, real-time detection equipment various states in operation.

The above is only a preferred embodiment of the present invention, and the protection scope of the present invention is not limited to the above-mentioned embodiments, and all technical solutions belonging to the idea of the present invention belong to the protection scope of the present invention. It should be noted that modifications and embellishments within the scope of the invention may occur to those skilled in the art without departing from the principle of the invention, and are considered to be within the scope of the invention.

Claims

1. A centralized gigabit Ethernet optical transceiver is characterized by comprising a main control unit (10), an E1 unit (20), an Ethernet unit (30), a telephone unit (40) and an optical module interface device (50);

the master control unit (10) comprises a master control chip (11), a clock signal jitter attenuation chip (12), a power-on reset device (13), a clock attenuation signal configuration module (14) and a dial switch module (15);

the main control chip (11) is respectively connected to the E1 unit (20), the Ethernet unit (30), the telephone unit (40), the optical module interface device (50), the clock signal jitter attenuation chip (12) and the dial switch module (15);

the clock signal jitter attenuation chip (12) is respectively connected to a clock attenuation signal configuration module (14) and a power-on reset (13);

the clock attenuation signal configuration module (14) comprises a plurality of positive pole resistors and negative pole resistors, and each signal pin of the clock signal jitter attenuation chip (12) is connected to a VCC power supply end through one positive pole resistor and is grounded through one negative pole resistor;

the dial switch module (15) comprises a temporary storage 8U2 and a switch group 8SW 1;

a pin +33V of the register is connected to a VCC power supply end, a GND pin is grounded, a pin Q8 is connected to a main control chip (11), a pin DS is connected to the VCC power supply end through a resistor 8R22, a pin P1, a pin P2, a pin P3, a pin P4, a pin P5, a pin P6, a pin P7 and a pin P8 are respectively connected to a first pin, a second pin, a third pin, a fourth pin, a fifth pin, a sixth pin, a seventh pin and an eighth pin of a switch group 8SW1, a ninth pin, a tenth pin, an eleventh pin, a twelfth pin, a thirteenth pin, a fourteenth pin, a fifteenth pin and a sixteenth pin of the switch group 8SW1 are commonly grounded, a pin P1, a pin P2, a pin P3 and a pin P4 of the register are respectively connected to a pin 4A, a pin 3A, a pin 2A and a pin of a bar 8RN3, and a pin P5 of the register are connected to the pin P5, The pin P6, the pin P7 and the pin P8 are also respectively connected to the pin 4A, the pin 3A, the pin 2A and the pin 1A of the bank 8RN1, and the pin 1B, the pin 2B, the pin 3B and the pin 4B of the bank 8RN3 and the pin 1B, the pin 2B, the pin 3B and the pin 4B of the bank 8RN1 are commonly connected to a VCC power supply terminal.

2. The centralized gigabit ethernet optical transceiver of claim 1, wherein the plurality of registers 8U2 are arranged in series, the plurality of switch sets 8SW1 are arranged in one-to-one correspondence with the plurality of registers 8U2, and each register 8U2 is connected to the DS pin of the register 8U2 connected in series through the Q8 pin.

3. The centralized gigabit ethernet optical transceiver according to claim 1, wherein the E1 unit (20) comprises an E1 interface signal receiver (21), an E1 interface signal transmitter driver (22), and an E1 interface transformer (23);

the E1 interface signal receiver (21) is connected to the main control chip (11), and the E1 interface signal transmission driver (22) and the E1 interface transformer (23) are respectively connected to the E1 interface signal receiver (21).

4. The centralized gigabit Ethernet optical transceiver according to claim 3, wherein there are a plurality of E1 interface signal sinks (21), the number of E1 interface signal transmission drivers (22) is 2 times that of the E1 interface signal sinks (21), and each E1 interface signal sink (21) is connected to 2E 1 interface signal transmission drivers (22).

5. The centralized gigabit ethernet optical transceiver according to claim 1, wherein the ethernet unit (30) comprises an ethernet switch chip (31), a gigabit ethernet transformer (32), a gigabit ethernet interface chip (33), and an ethernet RJ45 interface chip (34);

the Ethernet switching chip (31) is connected to the main control chip (11), and the gigabit Ethernet transformer (32), the gigabit Ethernet interface chip (33) and the Ethernet RJ45 interface chip (34) are respectively connected to the Ethernet switching chip (31).

6. The centralized gigabit ethernet optical transceiver according to claim 5, wherein said ethernet switch chip (31) is provided in plurality and connected to the main control chip (11), and said gigabit ethernet transformer (32) is provided in plurality and connected to the ethernet switch chip (31) in a one-to-one correspondence.

7. The centralized gigabit ethernet optical transceiver according to claim 1, wherein the phone unit (40) comprises a logic signal driving chip (42) and a plurality of phone module connectors (41), the phone module connectors (41) are connected to the main control chip (11), and the logic signal driving chip (42) is connected to the main control chip (11) and each phone module connector (41).

8. The centralized gigabit ethernet optical transceiver according to claim 1, wherein the MOD _ DEF0 pin, the MOD _ DEF1 pin, the MOD _ DEF1 pin, and the TX _ FAULT pin of the optical module interface device (50) are respectively connected to the VCC power supply through a resistor 2R44, a resistor 2R43, a resistor 2R42, and a resistor 2R41, the VEET pin, the TX _ DISABLE pin, and the VEER pin are respectively connected to ground, the TD + pin and the TD-pin are respectively connected to the main control chip (11) through a resistor 2R45 and a resistor 2R46, the VCCT pin is connected to the first terminal of an inductor 2L7, the second terminal of the inductor 2L7 is connected to the VCC power supply, the first terminal of the inductor 2L7 is further respectively connected to the positive terminal of the polar capacitor 2EC5 and one terminal of the capacitor 2C22, the second terminal of the inductor 2L7 is connected to one terminal of the capacitor 2C21, the negative terminal of the capacitor EC5, the other terminal of the capacitor 2C22, the common terminal of the capacitor 21, the RATE _ SEL pin and the LOS pin are respectively connected to a VCC power supply through a resistor 2R47 and a resistor 2R48, the RD + pin and the RD-pin are respectively connected to a main control chip (11) through a resistor 2R49 and a resistor 2R50, the VCCR pin is connected to a first end of an inductor 2L8, a second end of the inductor 2L8 is connected to the VCC power supply, the first end of the inductor 2L8 is also respectively connected to a positive electrode of a polar capacitor 2EC4 and one end of a capacitor 2C24, a second end of the inductor 2L8 is connected to one end of a capacitor 2C23, and a negative electrode of the polar capacitor 2EC4, the other end of the capacitor 2C24 and the other end of the capacitor 2C23 are commonly grounded.