CN108493238B - Thin film transistor, manufacturing method, array substrate and display device - Google Patents
Thin film transistor, manufacturing method, array substrate and display device Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
- H01L29/513—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being perpendicular to the channel plane
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/518—Insulating materials associated therewith the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
Abstract
The invention discloses a thin film transistor, a manufacturing method of the thin film transistor, an array substrate and a display device. The thin film transistor includes: a gate electrode; and an internal insulating layer provided on the gate electrode, the internal insulating layer including an N element, an O element, and an Si element, in the internal insulating layer, in a direction from a side close to the gate electrode to a side far from the gate electrode, a content of the N element decreases, and a content of the O element increases. Therefore, the internal insulating layer is a single film layer, and the internal part of the insulating layer has no interface defects formed by different crystal lattices and is resistant to water vapor and free Na + 、K + 、H + The plasma has stronger blocking capability, thereby improving the performance of the thin film transistor.
Description
Technical Field
The invention relates to the field of display, in particular to a thin film transistor, a manufacturing method thereof, an array substrate and a display device.
Background
The display panel includes a display element and a control element, where the control element (e.g., a thin film transistor) is used to control input of a signal in the display element (e.g., a pixel electrode or an organic electroluminescent layer) so that the display panel realizes a display function. The thin film transistor comprises a grid electrode, a source electrode, a drain electrode, an active layer and an insulating layer, wherein the insulating layer is used for isolating the metal element or preventing the metal element from being in contact with the active layer, so that the thin film transistor achieves the function of switching.
However, improvements in the thin film transistor, the manufacturing method thereof, the array substrate and the display device are still needed.
Disclosure of Invention
The present invention is based on the discovery and recognition by the inventors of the following facts and problems:
at present, the thin film transistor still has the problem of poor performance, and further the display effect of the display device is influenced. The inventors have made extensive studies and have found, through a large number of experiments, that this is mainly caused by poor performance of an internal insulating layer in a thin film transistor. Specifically, currently, siN is commonly used in thin film transistors x Layer and SiO 2 Composite structure of layers or SiO of single composition x N y (x and y are constant values) as an internal insulating layer. Wherein SiN is used x Layer and SiO 2 SiN when the composite structure of the layers is used as an internal insulating layer x The layer serving as an insulating layer, siO 2 The layer serves as a protective layer against H + Penetrating the inner insulating layer. Although SiN x The layer has good insulating property, compact film layer, excellent water vapor barrier and free Na + 、K + Plasma capability, but SiN x H in free state in the layer + Much of it is easily diffused to the channel of the thin film transistor and also diffused to SiN x -SiO 2 Forming a new interface layer on the interface. Due to SiN x And SiO 2 The crystal structure types of the (A) are different, the cell constants are different, lattice distortion (stress) can be caused on an interface, a plurality of structural defects are formed, and the structural defects are represented as parasitic thin film transistors or parasitic capacitors on devices, so that the performance of the devices is reduced. And SiO of a single component x N y The film has loose quality and is resistant to water vapor and free Na + 、K + The plasma has weak barrier ability to water vapor and Na + 、K + Plasma is very likely to enter, and thus characteristics of a pixel electrode, a thin film transistor, and the like are affected, and display defects are formed. And SiO x N y To H + The barrier capability of the material is much lower than that of SiO 2 Thus SiO x N y It is not suitable for insulating layer of low temperature polysilicon. In summary, the current inter-layer insulation (also called interlayer insulation)Insulating layer) remains to be improved.
The present invention aims to alleviate or solve at least to some extent at least one of the above mentioned problems.
In one aspect of the present invention, a thin film transistor is provided. The thin film transistor includes: a gate electrode; and an internal insulating layer provided on the gate electrode, the internal insulating layer including an N element, an O element, and an Si element, in the internal insulating layer, along a direction from a side close to the gate electrode to a side far from the gate electrode, a content of the N element decreases, and a content of the O element increases. Therefore, the internal insulating layer is a single film layer, and the internal part of the insulating layer has no interface defects formed by different crystal lattices and is resistant to water vapor and free Na + 、K + 、H + The plasma has stronger blocking capability, thereby improving the performance of the thin film transistor.
According to an embodiment of the present invention, the inner insulation layer further includes: an N-rich phase on one side of the internal insulating layer close to the gate; a balanced phase on a side of the N-rich phase away from the gate; and the O-enriched phase is positioned on one side of the equilibrium phase far away from the N-enriched phase, wherein the content of O element in the equilibrium phase close to one side of the N-enriched phase is greater than the maximum value of the content of O element in the N-enriched phase and increases by no more than 30% of the maximum value of the content of O element in the N-enriched phase, the content of O element in the O-enriched phase close to one side of the equilibrium phase is greater than the maximum value of the content of O element in the equilibrium phase and increases by no more than 30% of the maximum value of the content of O element in the equilibrium phase, the content of N element in the equilibrium phase close to one side of the N-enriched phase is less than the minimum value of the content of N element in the N-enriched phase and increases by no more than 30% of the minimum value of the content of N element in the N-enriched phase, and the content of N element in the O-enriched phase close to one side of the equilibrium phase is less than the minimum value of the content of N element in the equilibrium phase and decreases by no more than 30% of the minimum value of the content of N element in the equilibrium phase. Thus, the internal insulating layer has good insulating property against Na in a free state + 、K + 、H + The plasma has strong blocking capability, the internal insulating layer is a single film layer, and interface defects formed by different crystal lattices do not exist in the insulating layer.
According to the embodiment of the present invention, in the internal insulating layer, the content of the N element is uniformly decreased and the content of the O element is uniformly increased along the direction from the N-rich phase to the O-rich phase. Therefore, the gradual transition from the N enrichment phase to the O enrichment phase can be realized, so that the internal insulating layer has good insulating property and can not only have good insulating property to free Na + 、K + 、H + The plasma has strong blocking capability, and can prevent an interface layer formed between different crystal lattices from appearing in the internal insulating layer, thereby improving the performance of the thin film transistor.
According to an embodiment of the present invention, in the inner insulating layer, the content of the N element decreases in a gradient manner and the content of the O element increases in a gradient manner in a direction from the N-rich phase to the O-rich phase. Therefore, the gradual transition from the N enrichment phase to the O enrichment phase can be realized, so that the internal insulating layer has good insulating property and can not only have good insulating property to free Na + 、K + 、H + The plasma has strong blocking capability, and can prevent an interface layer formed among different crystal lattices from appearing in the internal insulating layer, thereby improving the performance of the thin film transistor.
In another aspect of the invention, a method of fabricating a thin film transistor is provided. According to an embodiment of the invention, the method comprises: arranging a grid; and providing an internal insulating layer on the gate electrode, the internal insulating layer including an N element, an O element, and an Si element, in the internal insulating layer, the content of the N element decreases and the content of the O element increases in a direction from a side close to the gate electrode to a side far from the gate electrode. Therefore, the internal insulating layer with a single film layer and without interface defects formed by different crystal lattices in the internal insulating layer can be obtained by a simple method, and the thin film transistor with good performance is further obtained.
In accordance with an embodiment of the present invention,the internal insulation layer is formed by chemical vapor deposition, and the step of arranging the internal insulation layer is realized by the following steps: introducing SiH into the sealed space 4 、N 2 O、NH 3 And N 2 So as to provide an N-rich phase on the gate electrode; introducing SiH into the sealed space 4 、N 2 O、NH 3 And N 2 So as to provide an equilibrium phase on the side of the N-rich phase remote from the grid; and introducing SiH into the sealed space 4 、N 2 O、NH 3 And N 2 The content of the O element in the equilibrium phase at a side close to the N-enriched phase is made to be greater than the maximum value of the content of the O element in the N-enriched phase by an amount not exceeding 30% of the maximum value of the content of the O element in the N-enriched phase, the content of the O element in the O-enriched phase at a side close to the equilibrium phase is made to be greater than the maximum value of the content of the O element in the equilibrium phase by an amount not exceeding 30% of the maximum value of the content of the O element in the N-enriched phase, the content of the N element in the equilibrium phase at a side close to the N-enriched phase is made to be less than the minimum value of the content of the N element in the N-enriched phase by an amount not exceeding 30% of the minimum value of the content of the N element in the N-enriched phase, and the content of the N element in the O-enriched phase at a side close to the equilibrium phase is made to be less than the minimum value of the content of the N element in the equilibrium phase by an amount not exceeding 30% of the minimum value of the N element in the equilibrium phase. Therefore, na with good insulating property and free state can be obtained by adjusting the content of each element in the mixed gas + 、K + 、H + The plasma has an internal insulating layer with strong blocking capability, the internal insulating layer is a single film layer, and interface defects formed by different lattices do not exist in the insulating layer.
According to the embodiment of the invention, when the N-enriched phase is formed, the content of the N element in the first mixed gas is adjusted to be uniformReduction; when the equilibrium phase is formed, adjusting the content of the O element in the second mixed gas to be uniformly increased, wherein the maximum value of the content of the N element in the second mixed gas is less than or equal to the minimum value of the content of the N element in the first mixed gas; and when the O enriched phase is formed, adjusting the content of O element in the third mixed gas to be uniformly increased and the content of N element to be uniformly reduced, wherein the maximum value of the content of N element in the third mixed gas is less than or equal to the minimum value of the content of N element in the second mixed gas, and the minimum value of the content of O element in the third mixed gas is greater than or equal to the maximum value of the content of O element in the second mixed gas. Therefore, the gradual transition from the N enrichment phase to the O enrichment phase can be realized, so that the internal insulating layer has good insulating property and can not only have good insulating property to free Na + 、K + 、H + The plasma has strong blocking capability, and can prevent an interface layer formed among different crystal lattices from appearing in the internal insulating layer, thereby improving the performance of the thin film transistor.
According to the embodiment of the invention, when the N-enriched phase is formed, the content of the N element in the first mixed gas is adjusted to be reduced in a gradient manner; when the equilibrium phase is formed, adjusting the content of the O element in the second mixed gas to increase in a gradient manner, wherein the maximum value of the content of the N element in the second mixed gas is less than or equal to the minimum value of the content of the N element in the first mixed gas; and when the O-enriched phase is formed, adjusting the content of the O element in the third mixed gas to increase in a gradient manner and the content of the N element to decrease in a gradient manner, wherein the maximum value of the content of the N element in the third mixed gas is less than or equal to the minimum value of the content of the N element in the second mixed gas, and the minimum value of the content of the O element in the third mixed gas is greater than or equal to the maximum value of the content of the O element in the second mixed gas. Therefore, the gradual transition from the N enrichment phase to the O enrichment phase can be realized, so that the internal insulating layer has good insulating property and can not only have good insulating property to free Na + 、K + 、H + The plasma has strong blocking capability, and can prevent interface layers formed between different crystal lattices from appearing in the internal insulating layer, thereby improving the performance of the thin film transistorCan be used.
In another aspect of the present invention, an array substrate is provided. According to an embodiment of the present invention, the array substrate includes the foregoing thin film transistor, and thus, the array substrate has all the features and advantages of the foregoing thin film transistor, which are not described herein again. In general, the array substrate has good use performance.
In another aspect of the present invention, a display device is provided. According to an embodiment of the present invention, the display device includes the array substrate, and thus, the display device has all the features and advantages of the array substrate, which are not described herein again. In general, the display device has good display effect.
Drawings
The above and/or additional aspects and advantages of the present invention will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:
fig. 1 shows a schematic structural diagram of a thin film transistor according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a prior art TFT;
FIG. 3 shows a schematic structural diagram of a thin film transistor according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of a TFT structure according to another embodiment of the present invention;
FIG. 5 is a schematic diagram of a TFT structure according to another embodiment of the present invention; and
fig. 6 shows a flow chart of a method for fabricating a thin film transistor according to an embodiment of the invention.
Description of the reference numerals:
100: a gate electrode; 200: an inner insulating layer; 210: n-enriched phase; 220: an equilibrium phase; 230: an O-enriched phase; 240: siN x A layer; 250: siO 2 2 A layer; 300: an active layer; 400: a gate insulating layer; 500: a source electrode; 600: a drain electrode; 700: a substrate; 800: a buffer layer; 10: an interfacial layer.
Detailed Description
Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the accompanying drawings are illustrative only for the purpose of explaining the present invention, and are not to be construed as limiting the present invention.
In one aspect of the present invention, a thin film transistor is provided. According to an embodiment of the present invention, referring to fig. 1, the thin film transistor includes: a gate electrode 100, and an internal insulating layer 200. Wherein the internal insulating layer 200 is disposed on the gate electrode 100, the internal insulating layer 200 includes an N element, an O element, and an Si element, and in the internal insulating layer 200, the content of the N element decreases and the content of the O element increases along a direction from a side close to the gate electrode 100 to a side far from the gate electrode 100. Therefore, the internal insulating layer is a single film layer, has good insulating property and can be used for the water vapor and the free Na + 、K + 、H + The plasma has stronger blocking capability, and the inside of the insulating layer has no interface defects formed by different crystal lattices, thereby improving the performance of the thin film transistor.
For ease of understanding, the following first briefly describes a thin film transistor according to an embodiment of the present invention:
as mentioned above, siN is commonly used in current thin film transistors x Layer and SiO 2 Composite structure of layers or SiO of single composition x N y (x and y are constant values) as an internal insulating layer. For SiN x Layer and SiO 2 Composite Structure of layers, referring to FIG. 2, the internal insulation layer 200 comprises SiN x Layer 240 and SiO 2 Layer 250, albeit of SiN x Layer 240 has good insulating properties, a dense film layer, excellent barrier to moisture and free Na + 、K + Plasma capability, but SiN x H in free state in layer 240 + Much of it is easily diffused to the channel of the thin film transistor and also diffused to SiN x -SiO 2 A new interface layer 10 is formed on the interface. Due to SiN x And SiO 2 The crystal structure types of the (A) are different, the cell constants are different, lattice distortion (stress) can be caused on an interface, a plurality of structural defects are formed, and the structural defects are represented as parasitic thin film transistors or parasitic capacitors on devices, so that the performance of the devices is reduced. For single component SiO x N y As an internal insulating layer, due to SiO x N y The film has loose quality and is resistant to water vapor and free Na + 、K + The plasma has weak barrier ability to water vapor and Na + 、K + Plasma is very likely to enter, and thus characteristics of a pixel electrode, a thin film transistor, and the like are affected, and display defects are formed. And SiO x N y To H + The barrier capability of the material is much lower than that of SiO 2 Thus SiO x N y It is not suitable for insulating layer of low temperature polysilicon.
According to the embodiments of the present invention, the effects of the composite structure, such as good insulation and strong Na resistance, can be achieved by forming the internal insulating layer in which the N content and the O content gradually change in a direction perpendicular to the gate electrode + 、K + 、H + The ability of plasma entry and the absence of interfacial layers of compounds of different crystal lattices between the multiple sublayers in the inner insulating layer may improve the performance of the thin film transistor.
The following describes the respective structures of the thin film transistor in detail according to the embodiments of the present invention:
according to an embodiment of the present invention, referring to fig. 3, the internal insulation layer 200 includes: an N-rich phase 210, an equilibrium phase 220, and an O-rich phase 230. The N-rich phase 210 is located on a side of the internal insulation layer 200 close to the gate 100, the equilibrium phase 220 is located on a side of the N-rich phase 210 away from the gate 100, and the O-rich phase 230 is located on a side of the equilibrium phase 220 away from the N-rich phase 210. According to the embodiment of the present invention, the N-rich phase 210, the equilibrium phase 220, and the O-rich phase 230 all include N, O, and Si elements, wherein the content of N element in the N-rich phase 210 is much greater than the content of O element, and the content of Si element is proportional to the content of N element and O element; the content of O element in the equilibrium phase 220 is equivalent to the content of N element to reach the equilibrium stateThe content of Si element is in proportion to the content of N element and O element; the content of the O element in the O-rich phase 230 is much greater than the content of the N element, and the content of the Si element is proportional to the content of the N element and the O element. Thus, the N-rich phase 210 is primarily SiN x Has good insulating property, and the O-enriched phase 230 is mainly SiO 2 Has strong H prevention + The ability to enter, the equilibrium phase 220 acts as a transition phase from the N-rich phase 210 to the O-rich phase 230, so that the occurrence of an interface layer formed between different crystal lattices in the internal insulating layer can be prevented, thereby improving the performance of the thin film transistor. It should be particularly noted that the multilayer structure of the inner insulating layer 200 shown in the drawings is only for illustrating the relative positions of the N-rich phase 210, the equilibrium phase 220, and the O-rich phase 230, and the inner insulating layer 200 should not be construed as including a multiple sublayer structure. In fact, there is no specific interface between the N-rich phase 210, the equilibrium phase 220, and the O-rich phase 230, and the three phases gradually change depending on the chemical composition (N, O, and Si content) to realize natural transition, and there is no specific interface between any two adjacent phases.
According to the embodiment of the invention, in the process of forming the N-rich phase 210, the equilibrium phase 220 and the O-rich phase 230, the gas containing N element and O element is simultaneously introduced, and the N-rich phase 210, the equilibrium phase 220 and the O-rich phase 230 are respectively formed by adjusting the content relationship of N element and O element. In addition, the N-rich phase 210, the equilibrium phase 220, and the O-rich phase 230 all contain O elements and N elements, and along the direction from the N-rich phase 210 to the O-rich phase 230, the content of O elements gradually increases, and the content of N elements gradually decreases, thereby realizing a gradual transition from the N-rich phase 210 to the O-rich phase 230. According to the embodiment of the invention, the gas containing N element and O element is introduced at the same time, so that the N atom and the O atom form a good matching relation, thereby eliminating the problems of lattice mismatch and the like and further eliminating the interface layer formed between different lattices.
According to the embodiment of the present invention, the content of the O element is gradually increased and the content of the N element is gradually decreased along the direction from the N-rich phase 210 to the O-rich phase 230. Specifically, the equilibrium phase 220 is adjacent to the N-rich phase 210The content of the O element at the side is greater than the maximum value of the content of the O element in the N-enriched phase 210, the increase is not more than 30% of the maximum value of the content of the O element in the N-enriched phase 210, the content of the O element at the side, close to the equilibrium phase 220, in the O-enriched phase 230 is greater than the maximum value of the content of the O element in the equilibrium phase 220, and the increase is not more than 30% of the maximum value of the content of the O element in the equilibrium phase 220; the content of the N element in the equilibrium phase 220 on the side near the N-rich phase 210 is less than the minimum value of the N element content in the N-rich phase 210, and the reduction is not more than 30% of the minimum value of the N element content in the N-rich phase 210, and the content of the N element in the O-rich phase 230 on the side near the equilibrium phase 220 is less than the minimum value of the N element content in the equilibrium phase 220, and the reduction is not more than 30% of the minimum value of the N element content in the equilibrium phase 220. Therefore, the gradual transition from the N enrichment phase to the O enrichment phase can be realized, the generation of an interface layer formed between different crystal lattices is prevented, and the internal insulating layer is a single film layer, has good insulating property and can be used for free Na + 、K + 、H + The plasma has a strong blocking capability.
The manner of decreasing or increasing the N element and the O element is not particularly limited as long as the above decrease and increase ratio is satisfied, and those skilled in the art can design the element according to the specific situation. For example, according to the embodiment of the present invention, in the internal insulating layer, the content of the N element is uniformly decreased and the content of the O element is uniformly increased in the direction from the N-rich phase to the O-rich phase. It should be noted that the term "uniform" means that along the direction perpendicular to the gate electrode, the content of the N element decreases at a constant rate at different positions in the internal insulating layer 200, the content of the O element increases at a constant rate, and a straight line can be obtained by plotting the height or depth of the internal insulating layer 200 and the content of the N element at the positions, and similarly, a straight line can be obtained by plotting the height or depth of the internal insulating layer 200 and the content of the O element at the positions. Therefore, gradual transition from the N enrichment phase to the O enrichment phase can be realized, so that the inner insulating layer has good insulating property and can not only be used for the free Na + 、K + 、H + The plasma has strong blocking capability and can alsoTo prevent an interface layer formed between different crystal lattices from occurring in the internal insulating layer.
According to other embodiments of the present invention, in the inner insulating layer, the content of the N element decreases in a gradient manner and the content of the O element increases in a gradient manner in a direction from the N-rich phase to the O-rich phase. The term "gradient" means that the content of N element is balanced at a constant amount in each of the N-rich phase, the equilibrium phase, and the O-rich phase, and decreases linearly by a decreasing amount of not more than 30% during transition of the N-rich phase to the equilibrium phase and during transition of the equilibrium phase to the O-rich phase. Similarly, the content of the element O is kept in equilibrium in a constant amount in each of the N-rich phase, the equilibrium phase, and the O-rich phase, and increases linearly with an increase of not more than 30% in each of the transition of the N-rich phase to the equilibrium phase and the transition of the equilibrium phase to the O-rich phase. Therefore, the gradual transition from the N enrichment phase to the O enrichment phase can be realized, so that the internal insulating layer has good insulating property and can not only have good insulating property to free Na + 、K + 、H + The plasma has strong blocking capability, and can also prevent an interface layer formed between different crystal lattices from appearing in the internal insulating layer, thereby improving the performance of the thin film transistor.
According to an embodiment of the present invention, the inner insulating layer including the N-rich phase, the equilibrium phase, and the O-rich phase is made of SiO x N y Wherein x and y are independently selected from 2 to 6. For example, the inner insulating layer may be made of SiO 4 N 3 Formed of, or consisting of, siO 2 N 4 And (3) forming. Therefore, the internal insulating layer is a single film layer, has good insulating property and is H-proof + And interface defects formed by different crystal lattices do not exist in the insulating layer, so that the performance of the thin film transistor is improved. Specifically, the SiO is x N y Is a statistical result of the chemical composition at different locations in the inner insulating layer 200. Compared with the traditional method of using single SiO x N y The chemical composition of the inner insulating layer according to the embodiment of the present invention is different at different positions as compared with the inner insulating layer composed of the compositionNamely: the inner insulating layers at different depths or different locations have different chemical compositions.
The type of the thin film transistor is not particularly limited, and those skilled in the art can select the type according to the circumstances. For example, according to an embodiment of the present invention, the thin film transistor may have a top gate structure, and in particular, referring to fig. 4, the thin film transistor includes a gate electrode 100, a gate insulating layer 400, an active layer 300, an internal insulating layer 200, a source electrode 500, a drain electrode (not shown), a buffer layer 800, and a substrate 700. The buffer layer 800 is disposed on one side of the substrate 700, the active layer 300 is disposed on one side of the buffer layer 800 away from the substrate 700, the gate insulating layer 400 is disposed on one side of the active layer 300 away from the buffer layer 800, the gate electrode 100 is disposed in the gate insulating layer 400 and located on one side of the active layer 300 away from the buffer layer 800, the internal insulating layer 200 is disposed on one side of the gate insulating layer 400 away from the active layer 300, the internal insulating layer 200 and the gate insulating layer 400 have through holes, and the source electrode 500 is connected to the active layer 300 through the through holes. Therefore, the internal insulating layer is applied to the thin film transistor with the top gate structure, and the performance of the thin film transistor can be improved.
According to other embodiments of the present invention, the thin film transistor may have a bottom gate structure, and in particular, referring to fig. 5, the thin film transistor includes a gate electrode 100, a gate insulating layer 400, an active layer 300, an internal insulating layer 200, a source electrode 500, a drain electrode 600, a buffer layer 800, and a substrate 700. The buffer layer 800 is disposed on one side of the substrate 700, the gate 100 is disposed on one side of the buffer layer 800 away from the substrate 700, the gate insulating layer 400 is disposed on one side of the gate 100 away from the buffer layer 800, the internal insulating layer 200 is disposed on one side of the gate insulating layer 400 away from the gate 100, the active layer 300 is disposed on one side of the internal insulating layer 200 away from the gate insulating layer 400, and the source 500 and the drain 600 are disposed on one side of the internal insulating layer 200 away from the gate insulating layer 400 and connected to the active layer 300. Therefore, the internal insulating layer is applied to the thin film transistor with the bottom gate structure, and the performance of the thin film transistor can be improved.
In another aspect of the invention, a method of fabricating a thin film transistor is provided. According to an embodiment of the present invention, the thin film transistor manufactured by the method may be the thin film transistor described above, and thus, the thin film transistor manufactured by the method may have the same features and advantages as those of the thin film transistor described above, and will not be described herein again. According to an embodiment of the invention, referring to fig. 6, the method comprises:
s100: setting a grid
According to an embodiment of the invention, in this step, a gate is provided. The specific manner of disposing the gate electrode is not particularly limited, and those skilled in the art can design the gate electrode according to the specific circumstances.
S200: providing an internal insulating layer on the gate
According to an embodiment of the present invention, in this step, an internal insulating layer is provided on the gate electrode. According to the embodiment of the invention, the internal insulation layer is a single layer and comprises N element, O element and Si element, and in the internal insulation layer, along the direction from the side close to the grid electrode to the side far away from the grid electrode, the content of the N element is reduced, and the content of the O element is increased. Therefore, the internal insulating layer with a single film layer and without interface defects formed by different crystal lattices in the internal insulating layer can be obtained by a simple method, and the thin film transistor with good performance is further obtained.
According to an embodiment of the present invention, the inner insulating layer may be formed by chemical vapor deposition, and the providing of the inner insulating layer may be performed by: firstly, siH is introduced into a closed space at the same time 4 、N 2 O、NH 3 And N 2 So as to form an N-rich phase on the gate electrode, and subsequently, in the closed space, simultaneously introducing SiH 4 、N 2 O、NH 3 And N 2 So as to form a balanced phase on the side of the N-enriched phase away from the gate, and finally, simultaneously introducing SiH into the closed space 4 、N 2 O、NH 3 And N 2 So as to form an O-rich phase on the side of the equilibrium phase remote from the N-rich phase. According to the embodiment of the present invention, the flow rate of each gas in the mixed gas can be adjusted to adjust the N element, the O element, and the Si element in the mixed gasThe content of the element, thereby forming an N-rich phase, an equilibrium phase and an O-rich phase.
According to an embodiment of the present invention, NH in the first mixed gas 3 And N 2 Is far more than N 2 The content of O, whereby the content of the element N is much larger than the content of the element O, so that an N-enriched phase is formed. NH in the second mixed gas 3 And N 2 Content of (A) and N 2 The content of O is equivalent, and thus, the content of N element is equivalent to the content of O element to reach an equilibrium state so as to form an equilibrium phase. N in the third mixed gas 2 The content of O is far greater than that of NH 3 And N 2 Whereby the content of the O element is much larger than that of the N element to form an O enriched phase.
According to the embodiment of the invention, the content of each gas in the mixed gas is adjusted to realize the gradual transition from the N-enriched phase to the O-enriched phase. According to an embodiment of the present invention, the gradual transition from the N-rich phase to the O-rich phase may be achieved by: the content of O element at one side of the equilibrium phase close to the N enrichment phase is larger than the maximum value of the content of O element in the N enrichment phase and the amplification is not more than 30% of the maximum value of the content of O element in the N enrichment phase, the content of O element at one side of the O enrichment phase close to the equilibrium phase is larger than the maximum value of the content of O element in the equilibrium phase and the amplification is not more than 30% of the maximum value of the content of O element in the equilibrium phase, and the content of N element at one side of the equilibrium phase close to the N enrichment phase is smaller than the minimum value of the content of N element in the N enrichment phase and the amplification is not more than 30% of the minimum value of the content of N element in the N enrichment phase, and the content of N element at one side of the O enrichment phase close to the equilibrium phase is smaller than the minimum value of the content of N element in the equilibrium phase and the amplification is not more than 30% of the minimum value of the content of N element in the equilibrium phase. Therefore, the gradual transition from the N enrichment phase to the O enrichment phase can be realized, the interface layer formed among different crystal lattices in the internal insulating layer is prevented, and meanwhile, the internal insulating layer has good insulating property and strong H resistance + Of the cell.
The specific implementation process for realizing the gradual transition from the N-rich phase to the O-rich phase is not particularly limited as long as the above-mentioned reduction and increase are satisfiedHowever, the design can be designed by those skilled in the art according to specific situations. For example, according to an embodiment of the present invention, the N element may be uniformly decreased and the O element may be uniformly increased in a direction from the N-rich phase to the O-rich phase. According to the embodiment of the invention, when the N-rich phase is formed, the content of the N element in the first mixed gas can be adjusted to be uniformly reduced, that is, the flow rate of the N-containing gas in the first mixed gas can be continuously reduced in the process of forming the N-rich phase, so that the content of the N element in the first mixed gas is continuously and uniformly reduced along with the increase of the deposition time; similarly, when the equilibrium phase is formed, the content of the O element in the second mixed gas is adjusted to be uniformly increased, and the maximum value of the content of the N element in the second mixed gas is less than or equal to the minimum value of the content of the N element in the first mixed gas; and when an O enrichment phase is formed, adjusting the content of the O element in the third mixed gas to be uniformly increased and the content of the N element to be uniformly reduced, wherein the maximum value of the content of the N element in the third mixed gas is less than or equal to the minimum value of the content of the N element in the second mixed gas, and the minimum value of the content of the O element in the third mixed gas is greater than or equal to the maximum value of the content of the O element in the second mixed gas. Therefore, gradual transition from the N enrichment phase to the O enrichment phase can be realized, so that the inner insulating layer has good insulating property and can not only be used for the free Na + 、K + 、H + The plasma has strong blocking capability, and can prevent an interface layer formed between different crystal lattices from appearing in the internal insulating layer, thereby improving the performance of the thin film transistor.
According to other embodiments of the present invention, the N element may decrease in a gradient and the O element may increase in a gradient from the N-rich phase to the O-rich phase. According to the embodiment of the invention, when the N-enriched phase is formed, the content of the N element in the first mixed gas can be adjusted to be reduced in a gradient manner, namely, the flow of the N-containing gas in the first mixed gas is reduced by a certain value at intervals, and the flow of the N-containing gas can be reduced for multiple times in the process of forming the N-enriched phase; similarly, when forming equilibrium phase, adjusting the content of O element in the second mixed gas to increase in gradient, and the maximum value of the content of N element in the second mixed gas is less than or equal to N element in the first mixed gasMinimum of elemental content; and when the O enrichment phase is formed, adjusting the content of the O element in the third mixed gas to increase in a gradient manner and the content of the N element to decrease in a gradient manner, wherein the maximum value of the content of the N element in the third mixed gas is less than or equal to the minimum value of the content of the N element in the second mixed gas, and the minimum value of the content of the O element in the third mixed gas is greater than or equal to the maximum value of the content of the O element in the second mixed gas. Therefore, gradual transition from the N enrichment phase to the O enrichment phase can be realized, so that the inner insulating layer has good insulating property and can not only be used for the free Na + 、K + 、H + The plasma has strong blocking capability, and can prevent an interface layer formed between different crystal lattices from appearing in the internal insulating layer, thereby improving the performance of the thin film transistor.
According to the embodiment of the invention, the internal insulation layer is a single film layer and can be formed through single film forming, and the N enrichment phase, the equilibrium phase and the O enrichment phase can be formed only by adjusting the content of each gas in the introduced mixed gas, so that the internal insulation layer is formed + The performance is improved, and interface defects formed by different crystal lattices do not exist in the thin film transistor, so that the performance of the thin film transistor can be improved.
According to an embodiment of the present invention, the inner insulating layer including the N-rich phase, the equilibrium phase, and the O-rich phase is made of SiO x N y Wherein x and y are independently selected from 2 to 6. For example, the inner insulating layer may be made of SiO 4 N 3 Formed of, or consisting of, siO 2 N 4 And (3) forming. Therefore, the internal insulating layer is a single film layer, has good insulating property and is H-proof + And interface defects formed by different crystal lattices do not exist in the thin film transistor, so that the performance of the thin film transistor is improved.
According to the embodiment of the invention, the thin film transistor can be of a bottom gate structure and can also be of a top gate structure, so that the application of various conditions can be met. It will be understood by those skilled in the art that the thin film transistor may further include structures such as an active layer, a gate insulating layer, a source electrode, a drain electrode, a buffer layer, and a substrate in order to realize a functional use of the thin film transistor.
According to the embodiment of the invention, after the internal insulation layer is manufactured, the film quality of the internal insulation layer can be detected, for example, the uniformity, the distribution condition, the refractive index, the dielectric constant, the breakdown voltage, the hydrogen content and the like are detected, so as to ensure the reliability of the film layer.
In another aspect of the present invention, an array substrate is provided. According to an embodiment of the present invention, the array substrate includes the thin film transistor described above, and thus, the array substrate has all the features and advantages of the thin film transistor described above, which are not described herein again. In general, the array substrate has good use performance.
In another aspect of the present invention, a display device is provided. According to an embodiment of the present invention, the display device includes the array substrate described above, and thus, the display device has all the features and advantages of the array substrate described above, which are not described herein again. In general, the display device has good display effect.
In the description of the present invention, the terms "upper", "lower", and the like indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience of describing the present invention but do not require that the present invention must be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present invention.
Reference throughout this specification to the description of "one embodiment," "another embodiment," or the like means that a particular feature, structure, material, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Moreover, various embodiments or examples and features of various embodiments or examples described in this specification can be combined and combined by one skilled in the art without being mutually inconsistent. In addition, it should be noted that the terms "first" and "second" in this specification are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or to imply that the number of indicated technical features is high.
Although embodiments of the present invention have been shown and described above, it will be understood that the above embodiments are exemplary and not to be construed as limiting the present invention, and that changes, modifications, substitutions and alterations can be made to the above embodiments by those of ordinary skill in the art within the scope of the present invention.
Claims (8)
1. A thin film transistor, comprising:
a gate electrode; and
a gate insulating layer disposed on the gate electrode;
an internal insulating layer provided on a side of the gate insulating layer away from the gate electrode, the internal insulating layer including an N element, an O element, and an Si element, in the internal insulating layer, a content of the N element decreases and a content of the O element increases in a direction from a side close to the gate electrode to a side away from the gate electrode; the inner insulating layer is a single film layer;
the internal insulation layer further includes:
an N-rich phase on one side of the inner insulating layer near the gate;
a balanced phase on a side of the N-rich phase away from the gate; and
an O-rich phase on a side of the equilibrium phase away from the N-rich phase,
wherein the content of O element at one side of the equilibrium phase close to the N-rich phase is greater than the maximum content of O element in the N-rich phase and increases by no more than 30% of the maximum content of O element in the N-rich phase, the content of O element at one side of the O-rich phase close to the equilibrium phase is greater than the maximum content of O element in the equilibrium phase and increases by no more than 30% of the maximum content of O element in the equilibrium phase,
the content of the N element at one side of the equilibrium phase close to the N-enriched phase is less than the minimum value of the N element content in the N-enriched phase and the reduction is not more than 30% of the minimum value of the N element content in the N-enriched phase, and the content of the N element at one side of the O-enriched phase close to the equilibrium phase is less than the minimum value of the N element content in the equilibrium phase and the reduction is not more than 30% of the minimum value of the N element content in the equilibrium phase.
2. The thin film transistor according to claim 1, wherein a content of the N element is uniformly decreased and a content of the O element is uniformly increased in the internal insulating layer in a direction from the N-rich phase to the O-rich phase.
3. The thin film transistor according to claim 1, wherein a content of the N element is decreased in a gradient manner and a content of the O element is increased in a gradient manner in a direction from the N-rich phase to the O-rich phase in the internal insulating layer.
4. A method of fabricating a thin film transistor, comprising:
arranging a grid; and
arranging a grid insulating layer on the grid electrode;
arranging an internal insulating layer on one side of the gate insulating layer far away from the gate, wherein the internal insulating layer comprises an N element, an O element and a Si element, and the content of the N element is reduced and the content of the O element is increased in the internal insulating layer along the direction from the side close to the gate to the side far away from the gate; the inner insulating layer is a single film layer;
the internal insulation layer is formed by chemical vapor deposition, and the step of arranging the internal insulation layer is realized by the following steps:
in a closed space, siH is introduced 4 、N 2 O、NH 3 And N 2 So as to provide a first mixed gas on the grid electrodePlacing the N enrichment phase;
introducing SiH into the sealed space 4 、N 2 O、NH 3 And N 2 So as to provide an equilibrium phase on the side of the N-rich phase remote from the grid; and
introducing SiH into the sealed space 4 、N 2 O、NH 3 And N 2 So as to provide an O-enriched phase on the side of the equilibrium phase remote from the N-enriched phase,
by respectively and independently adjusting the content of N element, O element and Si element in the first mixed gas, the second mixed gas and the third mixed gas, the content of O element at one side of the equilibrium phase close to the N-enriched phase is larger than the maximum value of the content of O element in the N-enriched phase and increases by no more than 30% of the maximum value of the content of O element in the N-enriched phase, the content of O element at one side of the O-enriched phase close to the equilibrium phase is larger than the maximum value of the content of O element in the equilibrium phase and increases by no more than 30% of the maximum value of the content of O element in the equilibrium phase,
the content of the N element at one side of the equilibrium phase close to the N-enriched phase is less than the minimum value of the N element content in the N-enriched phase and the reduction is not more than 30% of the minimum value of the N element content in the N-enriched phase, and the content of the N element at one side of the O-enriched phase close to the equilibrium phase is less than the minimum value of the N element content in the equilibrium phase and the reduction is not more than 30% of the minimum value of the N element content in the equilibrium phase.
5. The method according to claim 4, wherein the content of N element in the first mixed gas is adjusted to be uniformly reduced when the N-rich phase is formed;
when the equilibrium phase is formed, adjusting the content of the O element in the second mixed gas to be uniformly increased, wherein the maximum value of the content of the N element in the second mixed gas is less than or equal to the minimum value of the content of the N element in the first mixed gas;
and when the O enriched phase is formed, adjusting the content of O element in the third mixed gas to be uniformly increased and the content of N element to be uniformly decreased, wherein the maximum value of the content of N element in the third mixed gas is less than or equal to the minimum value of the content of N element in the second mixed gas, and the minimum value of the content of O element in the third mixed gas is greater than or equal to the maximum value of the content of O element in the second mixed gas.
6. The method according to claim 4, wherein the content of N element in the first mixed gas is adjusted to be reduced in a gradient manner when the N-enriched phase is formed;
when the equilibrium phase is formed, adjusting the content of the O element in the second mixed gas to increase in a gradient manner, wherein the maximum value of the content of the N element in the second mixed gas is less than or equal to the minimum value of the content of the N element in the first mixed gas;
and when the O-enriched phase is formed, adjusting the content of the O element in the third mixed gas to increase in a gradient manner and the content of the N element to decrease in a gradient manner, wherein the maximum value of the content of the N element in the third mixed gas is less than or equal to the minimum value of the content of the N element in the second mixed gas, and the minimum value of the content of the O element in the third mixed gas is greater than or equal to the maximum value of the content of the O element in the second mixed gas.
7. An array substrate comprising the thin film transistor according to any one of claims 1 to 3.
8. A display device comprising the array substrate according to claim 7.
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