CN108493122B - Semiconductor devices and its packaging method - Google Patents
Semiconductor devices and its packaging method Download PDFInfo
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- CN108493122B CN108493122B CN201810276019.7A CN201810276019A CN108493122B CN 108493122 B CN108493122 B CN 108493122B CN 201810276019 A CN201810276019 A CN 201810276019A CN 108493122 B CN108493122 B CN 108493122B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/111—Manufacture and pre-treatment of the bump connector preform
- H01L2224/1112—Applying permanent coating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/81009—Pre-treatment of the bump connector or the bonding area
- H01L2224/81048—Thermal treatments, e.g. annealing, controlled pre-heating or pre-cooling
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/818—Bonding techniques
- H01L2224/81801—Soldering or alloying
- H01L2224/81815—Reflow soldering
Abstract
The present invention provides a kind of semiconductor devices and its packaging methods.Packaging method includes: metal cladding process: providing chip and substrate, wherein plates metal layer on one side in chip, the region with chip pre-bonded plates metal layer on substrate；Pre-sintering process: utilizing low-temperature and low-pressure sintering technique, and the metal layer of the metal layer of metallic film and chip, substrate is pre-sintered together；The metal of the metal layer of metallic film, the metal layer of chip and substrate is same metal；Sintering process: whole made of utilizing high temperature and pressure sintering process, sintering to be pre-sintered as chip, metallic film and substrate；Lead packages process: chip, metallic film and substrate that sintering is completed are connected on lead frame；Molding rib cutting process: molding is carried out, and rib cutting is carried out to the lead frame after molding, to obtain package structure of semiconductor device.
Description
Technical field
The present invention relates to field of semiconductor devices, in particular to a kind of semiconductor devices and its packaging method.
Background technique
Encapsulation is necessary and vital for semiconductor devices.Encapsulation is viscous including chip cutting, chip
It connects, lead packages process and molding rib cutting process, wherein die bonding technique is that chip is fixed on to the process of substrate.Traditional
Die bonding technique is to realize that chip is bonding with substrate using elargol or silver paste.However, either in elargol or silver paste
Comprising more organic principle, during the sintering process, these organic principles are reacted with oxygen at a higher temperature and are generated a large amount of
Carbon dioxide gas, a part of carbon dioxide gas evolution make to generate cavity, another part between substrate and chip in evolution
Carbon dioxide gas is not escaped and is deposited between substrate and chip, so that there are a large amount of cavities between chip and substrate, sternly
Ghost image rings the functions such as heat transfer and electrical conduction between chip and substrate.
Summary of the invention
The purpose of the present invention is to provide a kind of semiconductor devices and its packaging methods, to solve in the prior art ask
Topic.
In order to solve the above technical problems, the present invention provides a kind of packaging method of semiconductor devices, comprising: metal cladding mistake
Journey: providing chip and substrate, wherein plate metal layer on one side in the chip, over the substrate with the chip pre-bonded
Region plate metal layer；Pre-sintering process: low-temperature and low-pressure sintering technique is utilized, by the metal of metallic film and the chip
Layer, the substrate metal layer be pre-sintered together, make the chip, the metallic film and the substrate be unified into one it is whole
The metal layer of body, the metallic film, the metal layer of the chip and the substrate is formed by same metal material；It is sintered
Journey: whole made of utilizing high temperature and pressure sintering process, sintering to be pre-sintered as the chip, the metallic film and the substrate
Body；Lead packages process: the chip, the metallic film and the substrate that sintering is completed are connected on lead frame；
Molding rib cutting process: mould is carried out to the chip, the metallic film, the substrate and the lead frame using molding technique
Envelope, and rib cutting is carried out to the lead frame after molding, to obtain package structure of semiconductor device.
Preferably, the metallic film is Ag films, and the metal layer plated on the chip and the substrate is silver layer；Or
Person, the metallic film are gold thin film, and the metal layer plated on the chip and the substrate is layer gold.
Preferably, the sintering process carries out in upper mold and lower mold, the upper mold and the lower mold to by
The chip, the metallic film and the substrate are integrally pressed and are heated made of being pre-sintered；The upper mold and institute
It states the pressure that lower mold applies and is greater than 15Mpa, the temperature of heating is 200 degree~300 degree.
Preferably, the upper mold and the lower mold include multiple units, the unit of the upper mold and it is described under
The unit of mould corresponds, and multiple is pre-sintered by the chip, the metallic film and the substrate for being sintered simultaneously
Entirety.
Preferably, the flatness of the inner surface of the upper mold and the lower mold is respectively less than 5 μm.
Preferably, the thickness of the metallic film is less than 100 μm；The metallic film with a thickness of 20 μm~80 μm.
Preferably, the pre-sintering includes: and is pre-sintered the metal layer of metallic film and the chip together, and will burn
The metallic film of knot on the chip is pre-sintered together with the metal layer of the substrate again.
Preferably, the metal layer thickness of the chip is less than 1 μm；The metal layer thickness of the substrate is less than 10 μm；It is described
Pre-sintering makes metal layer of the metallic film respectively with the metal layer of the chip, the substrate by soldering tip in chip mounter
It contacts and is pre-sintered together, the sintering temperature of the pre-sintering is 100 degree~150 degree, and sintering pressure is 3Mpa~5Mpa, is burnt
Tying the time is 1~4 second.
Preferably, the chip is SiC chip；The substrate is ceramic insulation substrate.
The present invention also provides a kind of semiconductor devices, the semiconductor devices is made using packaging method as described above.
As shown from the above technical solution, the advantages and positive effects of the present invention are:
Present invention metal cladding on chip and substrate, to be pre-sintered, merged with metallic film one in sintering process
It rises, and since the metal layer of metallic film, the metal layer of chip and substrate is formed by same metal material, fusion
Effect is good, so that the adhesive property between chip, metallic film and substrate is more preferable.By be pre-sintered process, by metallic film with
Chip, substrate are bonded together, and since metallic film is practically free of organic ingredient, greatly reduce the sky between chip and substrate
Hole rate, and since the form of metallic film is fixed, there is mobility rather than the silver paste or elargol used in the prior art, thus
It avoids the position of chip from shifting, ensure that the accuracy of chip position on substrate, reduce due to chip position not just
Rework rate caused by really, ensure that going on smoothly for subsequent encapsulation process.
After chip, metallic film and substrate pre-burning strike up partnership, then it is sintered technique, passes through the agglomerant of high temperature and pressure
Skill migrates the metal layer of metallic film and chip, the metallic particles in the metal layer of substrate, while high pressure makes metal
The gap of intergranular becomes smaller, and generates particle joint, ultimately forms cavity less and fine and close sintered chip, metallic film and lining
Bottom.Since cavity is few, the connection between chip and substrate is strengthened, keeps its bonding strength higher, and in subsequent lead packages
In the process, reduce the probability that chip is secretly split, improve the stabilization of semiconductor devices, while also improving heat transfer and conduction
Property.
Detailed description of the invention
Fig. 1 is the flow chart of semiconductor packages method of the invention；
Fig. 2 is the schematic diagram that semiconductor packages method of the invention is sintered；
Fig. 3 is the schematic diagram that semiconductor packages method of the invention is pre-sintered.
Wherein, the reference numerals are as follows: 1, chip；2, the silver layer of chip；3, Ag films；4, the silver layer of substrate；5, it serves as a contrast
Bottom；6, upper mold；7, lower mold；8, the entirety that chip, Ag films and substrate are jointly formed；9, Argent grain；11, soldering tip.
Specific embodiment
The exemplary embodiment for embodying feature of present invention and advantage will describe in detail in the following description.It should be understood that
The present invention can have various variations in different embodiments, neither depart from the scope of the present invention, and theory therein
Bright and diagram inherently is illustrated as being used, rather than to limit the present invention.
Principle and structure in order to further illustrate the present invention carry out the preferred embodiment of the present invention now in conjunction with attached drawing detailed
It describes in detail bright.
- Fig. 3 refering to fig. 1, the present invention provide a kind of packaging method of semiconductor devices, including silver plating process, are pre-sintered
Journey, sintering process, lead packages process and molding rib cutting process.
Silver coating process: step S1 provides chip 1 and substrate 5, silver layer is wherein plated on one side in chip 1, in substrate 5
Upper and 1 pre-bonded of chip region plates silver layer.
Chip 1 is SiC chip, and substrate 5 is ceramic insulation substrate.In other embodiments, chip 1 can also for GaN chip,
GaAs chip；Substrate 5 can also be SiC substrate, Si substrate, Sapphire Substrate etc..
More preferably, for 2 thickness of silver layer of chip less than 1 μm, which should ensure that it with certain compression strength；Lining
For 4 thickness of silver layer at bottom less than 10 μm, the thickness of the silver layer should ensure that it with certain compression strength.
Step S2 is pre-sintered process: low-temperature and low-pressure sintering technique is utilized, by the silver layer 2 of Ag films 3 and chip, substrate
Silver layer 4 is pre-sintered together, and chip 1, Ag films 3 and substrate 5 is made to be unified into an entirety 8.
Specifically, Ag films 3 are practically free of organic ingredient, and for the film that fine silver granules are formed, thickness is less than 100 μm.
More preferably, the thickness range of Ag films 3 is 20 μm~80 μm.The Argent grain of Ag films 3 can be micron order, or nanometer
Grade.
The silver layer 2 of Ag films 3 and chip, substrate silver layer 4 lower than material melting point at a temperature of, generate intergranular suction
It is attached, it is transmitted and is migrated by Argent grain 9, chip 1, Ag films 3 and substrate 5 are combined into an entirety 8.And Ag films 3 and chip
Silver layer 2, substrate silver layer 4 formed by same metal material, therefore, syncretizing effect is good so that chip 1, Ag films 3 and lining
Adhesive property between bottom 5 is more preferable.By being pre-sintered process, Ag films 3 and chip 1, substrate 5 are bonded together, due to silver
Film 3 is free of organic principle, greatly reduces the voidage between chip 1 and substrate 5.In addition, the thermal expansion of same metal
Coefficient is the same, so that the thermal stress between the silver layer 4 of the silver layer 2 of Ag films 3 and chip, substrate is small, therefore is applicable to various
The chip 1 of size.
For the bonding quality for guaranteeing chip 1 and substrate 5, the area of traditional elargol or silver paste covering can be than the ruler of chip
It is very little much bigger.In the present invention during pre-sintering, the size of Ag films 3 and chip 1 matches, without being greater than chip
1 size substantially increases the utilization rate of Ag films 3, so that the utilization rate of Ag films 3 is close to 100%.
In compared with the existing technology for flowable silver paste or elargol, the form of Ag films 3 of the present invention is fixed and pre-burning
Knot between substrate 5 and chip 1, avoid the position of chip 1 from shifting, ensure that the certainty of 1 position of chip, reduce by
The rework rate caused by 1 malposition of chip, ensure that going on smoothly for subsequent encapsulation process.
As shown in Fig. 2, Ag films 3 and the silver layer 2 of chip are pre-sintered by soldering tip 11 in chip mounter in the present embodiment
Together, and by Ag films 3 of the sintering on chip 1 it is pre-sintered together with the silver layer of substrate 4 again.The sintering temperature of pre-sintering
It is 100 degree~150 degree, sintering pressure is 3Mpa~5Mpa, and sintering time is 1~4 second.Soldering tip 11 can with vacuum suction chip 1,
The risk that chip 1 is scratched is reduced, while heating chip 1, combines chip 1 with Ag films 3 even closer, prevents from being pre-sintered it
Chip 1 falls off afterwards.
In other embodiments, first the silver layer 4 of Ag films 3 and substrate can also be pre-sintered together, then will be sintered upper
Ag films 3 and chip silver layer 2 be pre-sintered together.
Step S3, sintering process: utilizing high temperature and pressure sintering process, and sintering is pre-sintered by chip 1, Ag films 3 and substrate 5
Made of whole 8.
By the sintering process of high temperature and pressure, make the silver layer 2 of Ag films 3 and chip, the Argent grain 9 in the silver layer 4 of substrate
Migrate, while high pressure makes the gap between Argent grain 9 become smaller, generate particle joint, ultimately form cavity less and it is fine and close by
The entirety 8 that chip 1, Ag films 3 and substrate 5 are jointly formed.Whole 8 cavity is fewer, and whens lead packages occurs what chip 1 was secretly split
Probability is fewer, and semiconductor devices is more stable, while heat transfer and electric conductivity are more preferable.
And high temperature and pressure sintering promotes the energy of atom by high temperature, atom migrates, while applying pressure, accelerates former
The movement of son, shortens the time of sintering, sintering time is made to shorten to a few minutes from 1 hour, and it is raw to be conducive to large-scale batch
It produces.
In the present embodiment, sintering process carries out in upper mold 6 and lower mold 7, upper mold 6 and lower mold 7 to by chip,
Whole 8 are pressed and are heated made of Ag films 3 and substrate 5 are pre-sintered.Specifically, the pressure that upper mold 6 and lower mold 7 apply
Power is greater than 15Mpa, and the temperature of heating is 200 degree~300 degree.Upper mold 6 and lower mold 7 not only can provide needed for sintering process
High temperature and pressure demand can also prevent the displacement of chip, it is ensured that the position of chip 1 is more accurate, drops significantly in particle migration
The probability that low chip 1 shifts, is conducive to the progress of subsequent encapsulation process.
More preferably, upper mold 6 and lower mold 7 include multiple units, and the unit of upper mold 6 and the unit one of lower die are a pair of
It answers, it is whole made of multiple pre-sinterings as chip, Ag films 3 and substrate 5 for being sintered simultaneously.The design can once be burnt simultaneously
Entirety made of multiple pre-sinterings as chip 1, Ag films 3 and substrate 5 is tied, large-scale serial production is suitable for.
The flatness of the inner surface of upper mold 6 and lower mold 7 is respectively less than 5 μm.It can make the gradient of chip after sintering
It is lower, less than 10 μm.
Lead packages process: step S4 chip, Ag films 3 and substrate 5 that sintering is completed is connected on lead frame.
During lead packages, since cavity is few, the connection between chip and substrate is strengthened, keeps its bonding strength higher, reduced
The probability that chip is secretly split.
Molding rib cutting process: step S5 carries out mould to chip 1, Ag films 3, substrate 5 and lead frame using molding technique
Envelope, and rib cutting is carried out to the lead frame after molding, to obtain package structure of semiconductor device.
In another embodiment of the present invention, metallic film is gold thin film, and the metal layer plated on chip 1 and substrate 5 is equal
For layer gold.Layer gold is wherein plated on one side in chip 1, and the region on substrate 5 with 1 pre-bonded of chip plates layer gold, utilizes
Chip 1, substrate 5 are passed sequentially through pre-sintering process, sintering process, lead packages process and molding rib cutting process and obtained by gold thin film
Package structure of semiconductor device.
The present invention also provides a kind of using semiconductor devices made from packaging method as above.
As shown from the above technical solution, the advantages and positive effects of the present invention are:
Present invention metal cladding on chip and substrate, to be pre-sintered, merged with metallic film one in sintering process
It rises, and since the metal layer of metallic film, the metal layer of chip and substrate is formed by same metal material, fusion
Effect is good, so that the adhesive property between chip, metallic film and substrate is more preferable.By be pre-sintered process, by metallic film with
Chip, substrate are bonded together, and since metallic film is practically free of organic ingredient, greatly reduce the sky between chip and substrate
Hole rate, and since the form of metallic film is fixed, there is mobility rather than the silver paste or elargol used in the prior art, thus
It avoids the position of chip from shifting, ensure that the accuracy of chip position on substrate, reduce due to chip position not just
Rework rate caused by really, ensure that going on smoothly for subsequent encapsulation process.
After chip, metallic film and substrate pre-burning strike up partnership, then it is sintered technique, passes through the agglomerant of high temperature and pressure
Skill migrates the metal layer of metallic film and chip, the metallic particles in the metal layer of substrate, while high pressure makes metal
The gap of intergranular becomes smaller, and generates particle joint, ultimately forms cavity less and fine and close sintered chip, metallic film and lining
Bottom.Since cavity is few, the connection between chip and substrate is strengthened, keeps its bonding strength higher, and in subsequent lead packages
In the process, reduce the probability that chip is secretly split, improve the stabilization of semiconductor devices, while also improving heat transfer and conduction
Property.
The above is only preferable possible embodiments of the invention, not limit the scope of the invention, all with the present invention
The variation of equivalent structure made by specification and accompanying drawing content, is included within the scope of protection of the present invention.
Claims (10)
1. a kind of packaging method of semiconductor devices characterized by comprising
Metal cladding process: providing chip and substrate, wherein plate metal layer on one side in the chip, over the substrate with
The region of the chip pre-bonded plates metal layer；
Pre-sintering process: utilizing low-temperature and low-pressure sintering technique, by the metal layer of metallic film and the chip, the gold of the substrate
Belong to layer to be pre-sintered together, the chip, the metallic film and the substrate is made to be unified into an entirety, the metal foil
The metal layer of film, the metal layer of the chip and the substrate is formed by same metal material；The sintering temperature of the pre-sintering
Degree is 100 degree~150 degree, and sintering pressure is 3Mpa~5Mpa；
Sintering process: utilizing high temperature and pressure sintering process, and sintering is pre-sintered by the chip, the metallic film and the substrate
Made of it is whole；The sintering process carries out in upper mold and lower mold, and the upper mold and the lower mold are to by described
Chip, the metallic film and the substrate are integrally pressed and are heated made of being pre-sintered；The upper mold and it is described under
The pressure that mold applies is greater than 15Mpa, and the temperature of heating is 200 degree~300 degree；
Lead packages process: the chip, the metallic film and the substrate that sintering is completed are connected on lead frame；
Molding rib cutting process: using molding technique to the chip, the metallic film, the substrate and the lead frame into
Row molding, and rib cutting is carried out to the lead frame after molding, to obtain package structure of semiconductor device.
2. packaging method according to claim 1, which is characterized in that the metallic film be Ag films, the chip and
The metal layer plated on the substrate is silver layer；Alternatively, the metallic film is gold thin film, plated on the chip and the substrate
Metal layer be layer gold.
3. packaging method according to claim 1, which is characterized in that the upper mold and the lower mold include multiple
The unit of unit, the unit of the upper mold and the lower die corresponds, for be sintered simultaneously it is multiple by the chip, it is described
Metallic film and the substrate are whole made of being pre-sintered.
4. packaging method according to claim 1, which is characterized in that the inner surface of the upper mold and the lower mold
Flatness is respectively less than 5 μm.
5. packaging method according to claim 1, which is characterized in that the thickness of the metallic film is less than 100 μm.
6. packaging method according to claim 5, which is characterized in that the metallic film with a thickness of 20 μm~80 μm.
7. packaging method according to claim 1, which is characterized in that the pre-sintering includes:
The metal layer of metallic film and the chip is pre-sintered together, and again by the metallic film of sintering on the chip
It is pre-sintered together with the metal layer of the substrate.
8. packaging method according to claim 7, which is characterized in that the metal layer thickness of the chip is less than 1 μm；It is described
The metal layer thickness of substrate is less than 10 μm；
It is described pre-sintering in chip mounter by soldering tip make the metallic film respectively with the metal layer of the chip, the substrate
Metal layer contact and be pre-sintered together, the sintering time of the pre-sintering is 1~4 second.
9. packaging method according to claim 1, which is characterized in that the chip is SiC chip；The substrate is ceramics
Insulating substrate.
10. a kind of semiconductor devices, which is characterized in that the semiconductor devices is used as described in claim 1~9 any one
Packaging method be made.
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| CN201810276019.7A CN108493122B (en) | 2018-03-30 | 2018-03-30 | Semiconductor devices and its packaging method |
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| CN201810276019.7A CN108493122B (en) | 2018-03-30 | 2018-03-30 | Semiconductor devices and its packaging method |
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| CN108493122B true CN108493122B (en) | 2019-11-29 |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103077912A (en) * | 2013-01-15 | 2013-05-01 | 宜兴市环洲微电子有限公司 | Graphite die for sintering multichip |
| CN103681525A (en) * | 2012-08-29 | 2014-03-26 | 英飞凌科技股份有限公司 | Pre-sintered semiconductor die structure |
| CN107004653A (en) * | 2015-01-26 | 2017-08-01 | 三菱电机株式会社 | The manufacture method of semiconductor device and semiconductor device |
-
2018
- 2018-03-30 CN CN201810276019.7A patent/CN108493122B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103681525A (en) * | 2012-08-29 | 2014-03-26 | 英飞凌科技股份有限公司 | Pre-sintered semiconductor die structure |
| CN103077912A (en) * | 2013-01-15 | 2013-05-01 | 宜兴市环洲微电子有限公司 | Graphite die for sintering multichip |
| CN107004653A (en) * | 2015-01-26 | 2017-08-01 | 三菱电机株式会社 | The manufacture method of semiconductor device and semiconductor device |
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