CN108492846A - A kind of PROM evaluation methods and system based on aerospace applications - Google Patents
A kind of PROM evaluation methods and system based on aerospace applications Download PDFInfo
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/50—Marginal testing, e.g. race, voltage or current testing
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C2029/0407—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals on power on
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/50—Marginal testing, e.g. race, voltage or current testing
- G11C2029/5004—Voltage
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Abstract
The PROM evaluation methods based on aerospace applications that the invention discloses a kind of, described method includes following steps：Step 1：Component grade is evaluated；Wherein, the evaluation of component grade includes storage unit evaluation, storage unit storage associate feature evaluation and the analysis of component grade functional performance；Step 2：Plate grade is evaluated；Wherein, plate grade evaluation include basic function verification, port timing verification, electric power pulling bias testing, upper and lower electrical testing and with CPU matching tests；Step 3：Programmable device is evaluated；Wherein, programmable device evaluation includes resistance uniformity analysis after the analysis of programmable device output stability and programming.The present invention can comprehensively evaluate PROM devices, be of great significance for the evaluation of PROM.
Description
Technical field
The invention belongs to aviation electronics circuit test field more particularly to a kind of PROM evaluation methods based on aerospace applications
And system.
Background technology
Prom memory as a kind of important storage medium, be widely applied to computer, mobile electronic device,
The fields such as aircraft industry are often used as astrionic system Program code and the storage of other key messages.Due to aerospace
The special working environment of device, such as：The conditions such as non-dismountable replacement and space radiation in device operation.This aspect
It is required that PROM has higher reliability, on the other hand require PROM that there is space environment adaptability.Therefore, it is formally answered in PROM
Before using space flight model task, need to carry out a series of reliability evaluation to PROM.
Before this, the evaluation method of PROM is to stress content in a certain respect for different occupation modes, evaluation
Index is not comprehensive.Therefore, a set of effectively evaluating method comprehensively is proposed by the appraisal organization of profession, it is unified to carry out to PROM
Appraisal, and instruct the application of PROM very necessary with this.
Invention content
Present invention solves the technical problem that being：It has overcome the deficiencies of the prior art and provide a kind of based on aerospace applications
PROM evaluation methods and system can comprehensively evaluate PROM devices, be of great significance for the evaluation of PROM.
The object of the invention is achieved by the following technical programs：A kind of PROM evaluation methods based on aerospace applications, institute
The method of stating includes the following steps：Step 1：Component grade is evaluated；Wherein, component grade evaluation includes that storage unit is commented
Valence, storage unit-storage associate feature evaluation and the analysis of component grade functional performance；Step 2：Plate grade is evaluated；Its
In, the evaluation of plate grade includes basic function verification, port timing verification, electric power pulling bias testing, upper and lower electrical testing and matches survey with CPU
Examination；Step 3：Programmable device is evaluated；Wherein, programmable device evaluation includes electricity after the analysis of programmable device output stability and programming
Hinder consistency analysis.
In the above-mentioned PROM evaluation methods based on aerospace applications, in step 1, storage unit evaluation includes the following steps：
Step S110：PROM devices are divided into four quadrant positions, choose several from four quadrant positions and center respectively
Storage unit；Step S120：Using certain voltage as stepping, several storage units chosen in step 1 are scanned, are surveyed
The leakage current for trying each storage unit obtains the breakdown voltage of each storage unit by leakage current；Step S130：According to each
The breakdown voltage of storage unit obtains the average value and standard deviation of breakdown voltage, if standard deviation divided by average value are less than 2%,
Storage unit breakdown voltage is consistent.
In the above-mentioned PROM evaluation methods based on aerospace applications, in step 1, storage unit-storage associate feature evaluation
Include the following steps：Step S210：PROM devices are chosen into several storage units；Step S220：At a certain temperature will
PROM devices work different specified times, obtain the resistance for several storage units chosen in step S210；Step S230：
The drift curve of resistance at any time is obtained according to the resistance of each storage unit and different specified times in step S220, if
Resistance drift amount is less than preset value and influences to be less than preset value to the power consumption of PROM devices, then the storage unit of PROM-storage is closed
Join stability of characteristics.
In the above-mentioned PROM evaluation methods based on aerospace applications, in step 1, the analysis of component grade functional performance includes
Following steps：Step S310：Population parameter test is carried out under the conditions of -55 DEG C, 25 DEG C and 125 DEG C to several PROM devices；
To the maximum value of parameter, minimum value, average value and standard deviation；If the distribution in ± 1 standard deviation is more than 60%, PROM devices
Electrical parameter is consistent；Step S320：With the positively and negatively stepping respectively of certain voltage, tested by supply voltage limit capacity
To PROM supply voltage limiting values；Step S330：Negative sense stepping at a time interval, test PROM devices are in different operation frequency
Function under rate obtains the limiting value of access cycle；Step S340：Temperature shock marginal test is carried out to PROM devices, is obtained
The resistance to temperature limiting range of stress value of PROM devices；Step S350：Keep PROM devices not powered storage 1000h under 150 DEG C of high temperature laggard
Row electric parameters testing, if electrical parameter, in predetermined threshold value, PROM devices pass through 150 DEG C, 1000h high-temperature storage life tests.
In the above-mentioned PROM evaluation methods based on aerospace applications, in step 2, basic function verification includes the following steps：
Step S410：PROM devices are written into data template with specified programmable device；Step S420：Build FPGA control systems, wherein
FPGA control systems include host computer and control panel, and host computer is connected with control panel, and control panel includes that fpga logic control is single
Member, MCU control unit and PROM devices, MCU control unit are connected with fpga logic control unit, fpga logic control unit
It is connected with PROM devices, MCU control unit is connected with fpga logic control unit；Step S430：Pass through PC control
Fpga logic control unit is read out the data that PROM devices are written；Step S440：FPGA returns to the data of reading
Position machine and compared with data template, if the data read are consistent with data template, the basic function of PROM devices is correct.
In the above-mentioned PROM evaluation methods based on aerospace applications, in step 2, port timing verification includes the following steps：
Step S510：PROM devices are written into data template with specified programmable device；Step S520：Build FPGA control systems, wherein
FPGA control systems include host computer and control panel, and host computer is connected with control panel, and control panel includes that fpga logic control is single
Member, MCU control unit and PROM devices, MCU control unit are connected with fpga logic control unit, fpga logic control unit
It is connected with PROM devices, MCU control unit is connected with fpga logic control unit；Step S530：It is given by host computer
Fpga logic control unit sends the instruction of different reading manners；Step S540：Fpga logic control unit executes step S520
In instruction when, by oscillograph acquire the enabled pins of PROM devices, address pin and data pin waveform, if waveform
Meet predetermined waveform, then port sequential is correct.
In the above-mentioned PROM evaluation methods based on aerospace applications, in step 2, electric power pulling bias testing includes the following steps：
Step S610：PROM devices are written into data template with specified programmable device；Step S620：Build FPGA control systems, wherein
FPGA control systems include host computer and control panel, and host computer is connected with control panel, and control panel includes that fpga logic control is single
Member, MCU control unit and PROM devices, MCU control unit are connected with fpga logic control unit, fpga logic control unit
It is connected with PROM devices, MCU control unit is connected with fpga logic control unit；Step S630：It is sent by host computer
PROM device power source voltage instructions；Step S640：MCU control unit on control panel executes the instruction in step S620, passes through
It adjusts digital regulation resistance and obtains supply voltage corresponding with instruction；Step S650：It is corresponding with instruction in step S640
Supply voltage under by PC control fpga logic control unit to be written PROM devices data be read out；Step
S660：The data of reading are returned to host computer and compared with data template by fpga logic control unit, if the data read
It is consistent with data template, then pass through electric power pulling bias testing.
In the above-mentioned PROM evaluation methods based on aerospace applications, in step 2, power-on and power-off test includes the following steps：Step
Rapid S710：PROM devices are written into data template with specified programmable device；Step S720：Build FPGA control systems, wherein
FPGA control systems include host computer and control panel, and host computer is connected with control panel, and control panel includes that fpga logic control is single
Member, MCU control unit and PROM devices, MCU control unit are connected with fpga logic control unit, fpga logic control unit
It is connected with PROM devices, MCU control unit is connected with fpga logic control unit；Step S730：Continuous several times are to control
Plate carries out upper and lower electronic work；Step S740：And pass through PC control fpga logic control unit pair after repeatedly upper and lower electricity
The data of write-in PROM devices are read out；Step S750：The data of reading are returned to host computer simultaneously by fpga logic control unit
Compared with data template, if the data read are consistent with data template, pass through upper and lower electrical testing.
Include following step with CPU matching tests in step 2 in the above-mentioned PROM evaluation methods based on aerospace applications
Suddenly：Step S810：PROM devices are written into program with specified programmable device；Step S820：Build system control cpu, wherein
System control cpu includes CPU, latch and PROM devices, and CPU, latch and PROM devices interconnect；Step S830：Make
CPU loads the program being written in PROM devices under assigned frequency；Step S840：CPU is according to loading in step S830
Program runs to obtain operation result, operation result compared with default result, if unanimously, by with CPU matching tests.
In the above-mentioned PROM evaluation methods based on aerospace applications, in step 3, the analysis of programmable device output stability includes
Following steps：Step S910：So that programmable device is operated at different temperature and voltage, PROM devices are programmed；Step
S920：Test program device output voltage and sequential at different temperature and voltage in step S910, if output voltage and
Sequential meets default result, then programmable device output is stablized；
Resistance uniformity analysis includes the following steps after programming：Step S1010：Make programmable device be operated in different temperature and
Under voltage, PROM devices are programmed；Step S1020：The storage unit of the PROM devices programmed in testing procedure S1010
Resistance, if resistance uniformity meets 6 σ distributions, resistance is consistent after programming.
According to another aspect of the present invention, a kind of PROM evaluation systems based on aerospace applications are additionally provided, including：First
Module, for evaluating component grade；Wherein, the evaluation of component grade includes storage unit evaluation, storage unit-storage pass
Join evaluating characteristics and the analysis of component grade functional performance；Second module, for evaluating plate grade；Wherein, plate grade evaluation packet
Include basic function verification, port timing verification, electric power pulling bias testing, upper and lower electrical testing and with CPU matching tests；Third module,
For evaluating programmable device；Wherein, programmable device evaluation includes that the analysis of programmable device output stability is consistent with resistance after programming
Property analysis.
The present invention has the advantages that compared with prior art：
(1) the present invention provides the evaluation methods of a set of PROM, can comprehensively evaluate PROM devices, for
The evaluation of PROM is of great significance；
(2) present invention is general for the PROM of domestic different factories same specification, can be conveniently objectively to difference
The device of factory is compared.
Description of the drawings
By reading the detailed description of hereafter preferred embodiment, various other advantages and benefit are common for this field
Technical staff will become clear.Attached drawing only for the purpose of illustrating preferred embodiments, and is not considered as to the present invention
Limitation.And throughout the drawings, the same reference numbers will be used to refer to the same parts.In the accompanying drawings：
Fig. 1 is the flow diagram of the PROM evaluation methods provided in an embodiment of the present invention based on aerospace applications.
Specific implementation mode
The exemplary embodiment of the disclosure is more fully described below with reference to accompanying drawings.Although showing the disclosure in attached drawing
Exemplary embodiment, it being understood, however, that may be realized in various forms the disclosure without should be by embodiments set forth here
It is limited.On the contrary, these embodiments are provided to facilitate a more thoroughly understanding of the present invention, and can be by the scope of the present disclosure
Completely it is communicated to those skilled in the art.It should be noted that in the absence of conflict, embodiment in the present invention and
Feature in embodiment can be combined with each other.The present invention will be described in detail below with reference to the accompanying drawings and embodiments.
Fig. 1 is the flow diagram of the PROM evaluation methods provided in an embodiment of the present invention based on aerospace applications.Such as Fig. 1 institutes
Show, is somebody's turn to do the PROM evaluation methods based on aerospace applications and includes the following steps：
Step 1：Component grade is evaluated；Wherein, the evaluation of component grade includes storage unit evaluation, storage unit-
Store associate feature evaluation and the analysis of component grade functional performance；
Step 2：Plate grade is evaluated；Wherein, plate grade evaluation includes basic function verification, port timing verification, power supply
High low bias test, upper and lower electrical testing and with CPU matching tests；
Step 3：Programmable device is evaluated；Wherein, programmable device evaluation includes the analysis of programmable device output stability and programming
Resistance uniformity is analyzed afterwards.
In step 1, storage unit evaluation includes the following steps：
Step S110：PROM is divided into four quadrant positions, if being chosen respectively from four quadrant positions and center
Dry storage unit；
Step S120：With certain voltage (0.1v-0.3v) for stepping, to several storage units for being chosen in step 1 into
Row scanning, tests the leakage current of each storage unit, the breakdown voltage of each storage unit is obtained by leakage current；
Step S130：The average value and standard deviation of breakdown voltage are obtained according to the breakdown voltage of each storage unit, if
Standard deviation divided by average value are less than 2%, then storage unit breakdown voltage is consistent.
In step 1, storage unit-storage associate feature evaluation includes the following steps：
Step S210：Device threshold resistance is determined according to the resistance value before and after PROM device breakdowns；
Step S220：PROM devices are chosen into several storage units；
Step S230：PROM devices are worked at a certain temperature different specified times, obtains choosing in step S220
Several storage units resistance；
Step S240：Resistance is obtained according to the resistance of each storage unit and different specified times in step S220 at any time
Between drift curve, if resistance drift amount is less than the 10% of threshold resistance, and influence of the resistance drift to PROM device power consumptions
Less than 1%, then the storage unit of PROM-storage associate feature is stablized.
In step 1, the analysis of component grade functional performance includes the following steps：
Step S310：Several (preferably 45) PROM devices are carried out under the conditions of -55 DEG C, 25 DEG C and 125 DEG C
Population parameter is tested；Obtain maximum value, minimum value, average value and the standard deviation of parameter；If the distribution in ± 1 standard deviation is more than
60%, then PROM device electrical parameters are consistent；
Step S320：With the positively and negatively stepping respectively of certain voltage, test to obtain by supply voltage limit capacity
PROM supply voltage limiting values；
Step S330：Negative sense stepping at a time interval, function of the test PROM devices under different operation frequency, obtains
To the limiting value of access cycle；
Step S340：Temperature shock marginal test is carried out to PROM devices, obtains the resistance to temperature limiting range of stress value of PROM devices；
Step S350：PROM devices are made to carry out electric parameters testing after not powered storage 1000h under 150 DEG C of high temperature, if electric
Parameter is in predetermined threshold value, then PROM devices pass through 150 DEG C, 1000h high-temperature storage life tests.Predetermined threshold value is device handbook
Defined.
In step 2, basic function verification includes the following steps：
Step S410：PROM devices are written into data template with specified programmable device；
Step S420：Build FPGA control systems, wherein system includes host computer and control panel, host computer and control panel
It is connected, control panel includes fpga logic control unit, MCU control unit and PROM devices, MCU control unit and fpga logic
Control unit is connected, and fpga logic control unit is connected with PROM devices, MCU control unit and fpga logic control unit
It is connected；
Step S430：The data that PROM devices are written are read out by PC control fpga logic control unit；
Step S440：The data of reading are returned to host computer and compared with data template by FPGA, if the data read
Consistent with data template, then the basic function of PROM devices is correct.
In step 2, port timing verification includes the following steps：
Step S510：PROM devices are written into data template with specified programmable device；
Step S520：Build FPGA control systems, wherein system includes host computer and control panel, host computer and control panel
It is connected, control panel includes fpga logic control unit, MCU control unit and PROM devices, MCU control unit and fpga logic
Control unit is connected, and fpga logic control unit is connected with PROM devices, MCU control unit and fpga logic control unit
It is connected
Step S530：The instruction of different reading manners is sent to fpga logic control unit by host computer；
Step S540：When fpga logic control unit executes the instruction in step S520, PROM devices are acquired by oscillograph
The enabled pin of part, the waveform of address pin and data pin, if waveform meets predetermined waveform, port sequential is correct.It should
Predetermined waveform is in device handbook regulation.
In step 2, electric power pulling bias testing includes the following steps：
Step S610：PROM devices are written into data template with specified programmable device；
Step S620：Build FPGA control systems, wherein system includes host computer and control panel, host computer and control panel
It is connected, control panel includes fpga logic control unit, MCU control unit and PROM devices, MCU control unit and fpga logic
Control unit is connected, and fpga logic control unit is connected with PROM devices, MCU control unit and fpga logic control unit
It is connected
Step S630：PROM device power source voltage instructions are sent by host computer；
Step S640：MCU control unit on control panel executes the instruction in step S620, by adjusting digital regulation resistance
Obtain supply voltage corresponding with instruction；
Step S650：Pass through PC control fpga logic under supply voltage corresponding with instruction in step S640
Control unit is read out the data that PROM devices are written；
Step S660：The data of reading are returned to host computer and compared with data template by fpga logic control unit, such as
The data that fruit is read are consistent with data template, then pass through electric power pulling bias testing.
In step 2, power-on and power-off test includes the following steps：
Step S710：PROM devices are written into data template with specified programmable device；
Step S720：Build FPGA control systems, wherein system includes host computer and control panel, host computer and control panel
It is connected, control panel includes fpga logic control unit, MCU control unit and PROM devices, MCU control unit and fpga logic
Control unit is connected, and fpga logic control unit is connected with PROM devices, MCU control unit and fpga logic control unit
It is connected；
Step S730：Continuous several times carry out upper and lower electronic work to control panel；
Step S740：And after repeatedly upper and lower electricity by PC control fpga logic control unit to PROM devices are written
The data of part are read out；
Step S750：The data of reading are returned to host computer and compared with data template by fpga logic control unit, such as
The data that fruit is read are consistent with data template, then pass through upper and lower electrical testing.
In step 2, include the following steps with CPU matching tests：
Step S810：PROM devices are written into program with specified programmable device；
Step S820：Build system control cpu, wherein system includes CPU, latch and the PROM devices of specified model,
Three is connected with each other；
Step S830：CPU is set to load the program being written in PROM devices under assigned frequency；
Step S840：CPU runs to obtain operation result, operation result and default knot according to the program loaded in step S830
Fruit compares, if unanimously, by with CPU matching tests.
In step 3, the analysis of programmable device output stability includes the following steps：
Step S910：So that programmable device is operated at different temperature and voltage, PROM devices are programmed；
Step S920：Test program device output voltage and sequential at different temperature and voltage in step S910, such as
Fruit output voltage and sequential meet default result, then programmable device output is stablized；
Resistance uniformity analysis includes the following steps after programming：
Step S1010：So that programmable device is operated at different temperature and voltage, PROM devices are programmed；
Step S1020：The resistance of the storage unit of the PROM devices programmed in testing procedure S1010, if resistance is consistent
Property meet 6 σ distribution, then program after resistance it is consistent.
The present embodiment additionally provides a kind of PROM evaluation systems based on aerospace applications, including：First module, the second module
With third module.Wherein,
First module, for evaluating component grade；Wherein, the evaluation of component grade includes storage unit evaluation, deposits
Storage unit-storage associate feature evaluation and the analysis of component grade functional performance；Second module, for evaluating plate grade；Its
In, the evaluation of plate grade includes basic function verification, port timing verification, electric power pulling bias testing, upper and lower electrical testing and matches survey with CPU
Examination；Third module, for evaluating programmable device；Wherein, programmable device evaluation includes the analysis of programmable device output stability and compiles
Resistance uniformity is analyzed after journey.
The evaluation method of a set of PROM is present embodiments provided, comprehensively PROM devices can be evaluated, for
The evaluation of PROM is of great significance.And the present embodiment is general, energy for the PROM of domestic different factories same specification
It is enough that conveniently objectively the device of different factories is compared.
Embodiment described above is the present invention more preferably specific implementation mode, and those skilled in the art is in this hair
The usual variations and alternatives carried out in bright technical proposal scope should be all included within the scope of the present invention.
Claims (11)
1. a kind of PROM evaluation methods based on aerospace applications, which is characterized in that described method includes following steps：
Step 1：Component grade is evaluated；Wherein, the evaluation of component grade includes storage unit evaluation, storage unit-storage
Associate feature is evaluated and the analysis of component grade functional performance；
Step 2：Plate grade is evaluated；Wherein, plate grade evaluation include basic function verification, port timing verification, power supply drawing partially
Test, upper and lower electrical testing and with CPU matching tests；
Step 3：Programmable device is evaluated；Wherein, programmable device evaluation includes electricity after the analysis of programmable device output stability and programming
Hinder consistency analysis.
2. the PROM evaluation methods according to claim 1 based on aerospace applications, it is characterised in that：In step 1, deposit
Storage unit evaluation includes the following steps：
Step S110：PROM devices are divided into four quadrant positions, if being chosen respectively from four quadrant positions and center
Dry storage unit；
Step S120：Using certain voltage as stepping, several storage units chosen in step 1 are scanned, test is each
The leakage current of storage unit obtains the breakdown voltage of each storage unit by leakage current；
Step S130：The average value and standard deviation of breakdown voltage are obtained according to the breakdown voltage of each storage unit, if standard
Difference divided by average value are less than 2%, then storage unit breakdown voltage is consistent.
3. the PROM evaluation methods according to claim 1 based on aerospace applications, it is characterised in that：In step 1, deposit
Storage unit-storage associate feature evaluation includes the following steps：
Step S210：PROM devices are chosen into several storage units；
Step S220：PROM devices are worked at a certain temperature different specified times, if obtain choosing in step S210
The resistance of dry storage unit；
Step S230：Resistance is obtained according to the resistance of each storage unit and different specified times in step S220 at any time
Drift about curve, if resistance drift amount is less than preset value and influences to be less than preset value to the power consumption of PROM devices, PROM's deposits
Storage unit-storage associate feature is stablized.
4. the PROM evaluation methods according to claim 1 based on aerospace applications, it is characterised in that：In step 1, member
The analysis of device level functional performance includes the following steps：
Step S310：Population parameter test is carried out under the conditions of -55 DEG C, 25 DEG C and 125 DEG C to several PROM devices；Obtain parameter
Maximum value, minimum value, average value and standard deviation；If the distribution in ± 1 standard deviation is more than 60%, PROM device electrical parameters
Unanimously；
Step S320：With the positively and negatively stepping respectively of certain voltage, test to obtain PROM by supply voltage limit capacity
Supply voltage limiting value；
Step S330：Negative sense stepping at a time interval, function of the test PROM devices under different operation frequency, must visit
Ask the limiting value in period；
Step S340：Temperature shock marginal test is carried out to PROM devices, obtains the resistance to temperature limiting range of stress value of PROM devices；
Step S350：PROM devices are made to carry out electric parameters testing after not powered storage 1000h under 150 DEG C of high temperature, if electrical parameter
In predetermined threshold value, then PROM devices pass through 150 DEG C, 1000h high-temperature storage life tests.
5. the PROM evaluation methods according to claim 1 based on aerospace applications, it is characterised in that：In step 2, base
This functional verification includes the following steps：
Step S410：PROM devices are written into data template with specified programmable device；
Step S420：Build FPGA control systems, wherein FPGA control systems include host computer and control panel, host computer and control
Making sheet is connected, and control panel includes fpga logic control unit, MCU control unit and PROM devices, MCU control unit and FPGA
Logic control element is connected, and fpga logic control unit is connected with PROM devices, MCU control unit and fpga logic control
Unit is connected；
Step S430：The data that PROM devices are written are read out by PC control fpga logic control unit；
Step S440：The data of reading are returned to host computer and compared with data template by FPGA, if the data and number that read
Consistent according to template, then the basic function of PROM devices is correct.
6. the PROM evaluation methods according to claim 1 based on aerospace applications, it is characterised in that：In step 2, end
Mouth timing verification includes the following steps：
Step S510：PROM devices are written into data template with specified programmable device；
Step S520：Build FPGA control systems, wherein FPGA control systems include host computer and control panel, host computer and control
Making sheet is connected, and control panel includes fpga logic control unit, MCU control unit and PROM devices, MCU control unit and FPGA
Logic control element is connected, and fpga logic control unit is connected with PROM devices, MCU control unit and fpga logic control
Unit is connected；
Step S530：The instruction of different reading manners is sent to fpga logic control unit by host computer；
Step S540：When fpga logic control unit executes the instruction in step S520, PROM devices are acquired by oscillograph
The waveform of enabled pin, address pin and data pin, if waveform meets predetermined waveform, port sequential is correct.
7. the PROM evaluation methods according to claim 1 based on aerospace applications, it is characterised in that：In step 2, electricity
Source high low bias test includes the following steps：
Step S610：PROM devices are written into data template with specified programmable device；
Step S620：Build FPGA control systems, wherein FPGA control systems include host computer and control panel, host computer and control
Making sheet is connected, and control panel includes fpga logic control unit, MCU control unit and PROM devices, MCU control unit and FPGA
Logic control element is connected, and fpga logic control unit is connected with PROM devices, MCU control unit and fpga logic control
Unit is connected；
Step S630：PROM device power source voltage instructions are sent by host computer；
Step S640：MCU control unit on control panel executes the instruction in step S620, is obtained by adjusting digital regulation resistance
Supply voltage corresponding with instruction；
Step S650：It is controlled by PC control fpga logic under supply voltage corresponding with instruction in step S640
Unit is read out the data that PROM devices are written；
Step S660：The data of reading are returned to host computer and compared with data template by fpga logic control unit, if read
The data taken are consistent with data template, then pass through electric power pulling bias testing.
8. the PROM evaluation methods according to claim 1 based on aerospace applications, it is characterised in that：In step 2, on
Lower electrical testing includes the following steps：
Step S710：PROM devices are written into data template with specified programmable device；
Step S720：Build FPGA control systems, wherein FPGA control systems include host computer and control panel, host computer and control
Making sheet is connected, and control panel includes fpga logic control unit, MCU control unit and PROM devices, MCU control unit and FPGA
Logic control element is connected, and fpga logic control unit is connected with PROM devices, MCU control unit and fpga logic control
Unit is connected；
Step S730：Continuous several times carry out upper and lower electronic work to control panel；
Step S740：And after repeatedly upper and lower electricity by PC control fpga logic control unit to write-in PROM devices
Data are read out；
Step S750：The data of reading are returned to host computer and compared with data template by fpga logic control unit, if read
The data taken are consistent with data template, then pass through upper and lower electrical testing.
9. the PROM evaluation methods according to claim 1 based on aerospace applications, it is characterised in that：In step 2, with
CPU matching tests include the following steps：
Step S810：PROM devices are written into program with specified programmable device；
Step S820：Build system control cpu, wherein system control cpu includes CPU, latch and PROM devices, CPU, lock
Storage and PROM devices interconnect；
Step S830：CPU is set to load the program being written in PROM devices under assigned frequency；
Step S840：CPU runs to obtain operation result, operation result and default result phase according to the program loaded in step S830
Compare, if unanimously, by with CPU matching tests.
10. the PROM evaluation methods according to claim 1 based on aerospace applications, it is characterised in that：In step 3, compile
The analysis of journey device output stability includes the following steps：
Step S910：So that programmable device is operated at different temperature and voltage, PROM devices are programmed；
Step S920：Test program device output voltage and sequential at different temperature and voltage in step S910, if defeated
Go out voltage and sequential meets default result, then programmable device output is stablized；
Resistance uniformity analysis includes the following steps after programming：
Step S1010：So that programmable device is operated at different temperature and voltage, PROM devices are programmed；
Step S1020：The resistance of the storage unit of the PROM devices programmed in testing procedure S1010, if resistance uniformity is full
Foot 6 σ distributions, then resistance is consistent after programming.
11. a kind of PROM evaluation systems based on aerospace applications, it is characterised in that including：
First module, for evaluating component grade；Wherein, the evaluation of component grade includes storage unit evaluation, storage list
Member-storage associate feature evaluation and the analysis of component grade functional performance；
Second module, for evaluating plate grade；Wherein, plate grade evaluation includes basic function verification, port timing verification, electricity
Source high low bias test, upper and lower electrical testing and with CPU matching tests；
Third module, for evaluating programmable device；Wherein, programmable device evaluation includes the analysis of programmable device output stability and compiles
Resistance uniformity is analyzed after journey.
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