CN108470743A - The forming method of imaging sensor - Google Patents
The forming method of imaging sensor Download PDFInfo
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- CN108470743A CN108470743A CN201810282396.1A CN201810282396A CN108470743A CN 108470743 A CN108470743 A CN 108470743A CN 201810282396 A CN201810282396 A CN 201810282396A CN 108470743 A CN108470743 A CN 108470743A
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- 238000000034 method Methods 0.000 title claims abstract description 196
- 238000003384 imaging method Methods 0.000 title claims abstract description 32
- 239000000758 substrate Substances 0.000 claims abstract description 107
- 239000004065 semiconductor Substances 0.000 claims abstract description 101
- 238000000137 annealing Methods 0.000 claims abstract description 87
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 74
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 73
- 239000001301 oxygen Substances 0.000 claims abstract description 73
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 73
- 230000008569 process Effects 0.000 claims abstract description 66
- 239000011248 coating agent Substances 0.000 claims abstract description 24
- 238000000576 coating method Methods 0.000 claims abstract description 24
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 15
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 15
- 238000002347 injection Methods 0.000 claims description 4
- 239000007924 injection Substances 0.000 claims description 4
- 238000005516 engineering process Methods 0.000 claims description 3
- 238000005468 ion implantation Methods 0.000 claims 1
- 238000002955 isolation Methods 0.000 description 31
- 150000002500 ions Chemical class 0.000 description 29
- 238000005286 illumination Methods 0.000 description 10
- 230000015572 biosynthetic process Effects 0.000 description 9
- 238000010586 diagram Methods 0.000 description 8
- 238000005530 etching Methods 0.000 description 8
- -1 oxonium ion Chemical class 0.000 description 7
- 238000004380 ashing Methods 0.000 description 6
- 238000010276 construction Methods 0.000 description 6
- 239000000463 material Substances 0.000 description 5
- 239000000243 solution Substances 0.000 description 5
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 230000003287 optical effect Effects 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 238000006243 chemical reaction Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000011049 filling Methods 0.000 description 3
- 239000011810 insulating material Substances 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000005622 photoelectricity Effects 0.000 description 3
- 238000004528 spin coating Methods 0.000 description 3
- 229910003978 SiClx Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 229910052738 indium Inorganic materials 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
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- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
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- 238000009792 diffusion process Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
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- 229910052733 gallium Inorganic materials 0.000 description 1
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- 150000004767 nitrides Chemical class 0.000 description 1
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- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
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- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
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- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
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Abstract
Technical solution of the present invention discloses a kind of forming method of imaging sensor, including：Semiconductor substrate is provided, the semiconductor substrate includes adjacent first area and at least one second area；First groove is formed in the semiconductor substrate；Photoresist layer is formed in the semiconductor substrate of the first area and the non-processing second area；Using the photoresist layer as mask, note oxygen technique is carried out, annealing process is carried out again after noting oxygen, oxide skin(coating) is formed in the semiconductor substrate of the first groove bottom for the second area that need to be processed；Using above-mentioned flow, the second area processed successively in different need carries out note oxygen technique and annealing process, oxide skin(coating) is formed in the semiconductor substrate of the first groove bottom of the second area, the different second areas forms the oxide skin(coating) of different-thickness.When different zones form the groove of different depth, avoids and generate difference in height between exposed film layer and shielded film layer.
Description
Technical field
The present invention relates to the manufacturing field of semiconductor devices more particularly to the forming methods of imaging sensor, especially carry on the back
The forming method of illuminated image sensor.
Background technology
Imaging sensor receives optical signal from object and converts optical signal into electric signal, and then electric signal can be transmitted
For further handling, such as digitizes, then stored in such as memory device of memory, CD or disk, or use
In display over the display, printing etc..Imaging sensor is commonly used in digital camera, video camera, scanner, facsimile machine etc.
Device.
Imaging sensor is usually two types, charge coupling device (CCD) sensor and cmos image sensor
(CIS).CCD is known as photoelectric coupled device, collects charge by photoelectric effect, often the charge of row pixel is sent to clock signal
It simulates on shift register, then serial conversion is voltage.CIS is a kind of solid state image sensor of fast development, due to
Image sensor portion and control circuit part in cmos image sensor are integrated in same chip, therefore cmos image passes
Sensor it is small, low in energy consumption, cheap, have more advantage compared to traditional CCD (Charged Couple) imaging sensor, also more
It is easily universal.
Existing cmos image sensor includes mainly preceding illuminated (Front-side Illumination, abbreviation FSI)
Cmos image sensor and back-illuminated type (Back-side Illumination, abbreviation BSI) two kinds of cmos image sensor.Its
In, in back side illumination image sensor, light from the photodiode in the back surface incident to imaging sensor of imaging sensor,
To convert light energy into electric energy；Back-illuminated cmos image sensors are because its better photoelectric conversion result (i.e. imitate by quantum conversion
Rate is high) and the wider application of acquisition.
When cmos image sensor forms groove at present, due to forming the region of photodiode and forming circuit unit
The depth of groove isolation construction required by region is different, needs first to etch to form shallower groove, then covers two pole of photoelectricity
Region where pipe further etches other regions and forms deeper groove.But the prior art uses multistep etching technics
The groove for forming different depth is caused since etch media can also remove the film layer of exposed segment thickness in etching process
Prodigious difference in height is formed between film layer and the film layer being exposed under etch media in different zones under photoresist protection, to rear
Continuous chemically mechanical polishing (CMP) technique generates prodigious burden.In addition, this multistep etching technics not only easily causes substrate
Damage influence yield, and complex process, influence efficiency.
Invention content
Technical solution of the present invention technical problems to be solved are to provide a kind of forming method of imaging sensor, using passing through
Note oxygen technique adjusts the depth of different zones groove, to meet different trench isolations requirements.
In order to solve the above technical problems, technical solution of the present invention provides a kind of forming method of imaging sensor includes：It carries
For semiconductor substrate, the semiconductor substrate includes adjacent first area and at least one second area；In the semiconductor
First groove is formed in substrate；Light is formed in the semiconductor substrate of the first area and the non-processing second area
Photoresist layer；Using the photoresist layer as mask, note oxygen technique is carried out, annealing process is carried out again after noting oxygen, described in it need to process
Oxide skin(coating) is formed in the semiconductor substrate of the first groove bottom of second area；Remove the photoresist layer；It adopts
With above-mentioned flow, the second area processed successively in different need carries out note oxygen technique and annealing process, this described the
Oxide skin(coating) is formed in the semiconductor substrate of the first groove bottom in two regions, the different second areas forms difference
The oxide skin(coating) of thickness.
Optionally, when the second area is one：First groove is formed in the semiconductor substrate；Described
The photoresist layer is formed in the semiconductor substrate in one region；Using the photoresist layer as mask, the first note oxygen work is carried out
Skill carries out the first annealing process after the first note oxygen technique, oxide is formed in the semiconductor substrate of first groove bottom again
Layer forms second groove；Remove the photoresist layer.
Optionally, first note oxygen technique is O +ion implanted technique.
Optionally, the direction of O +ion implanted and the surface composition of the semiconductor substrate in first note oxygen technique
Angle is 60 °~120 °.
Optionally, the O +ion implanted dosage is 1E14sccm~5E18sccm, and energy is 50Kev~250Kev.
Optionally, first annealing process is furnace anneal or short annealing.
Optionally, when first annealing process is furnace anneal, furnace tube temperature is 800 DEG C~1300 DEG C, when annealing
Between be 1 hour~5 hours.
Optionally, when first annealing process is short annealing, annealing temperature is 900 DEG C~1300 DEG C, when annealing
Between be 3 seconds~30 minutes.
Optionally, when the second area is two, the first second area and the second second area are located at first
Region both sides：First groove is formed in the semiconductor substrate；In the first area and the institute of first second area
It states and forms photoresist layer in semiconductor substrate；Using the photoresist layer as mask, the first note oxygen technique, the first note oxygen technique are carried out
Carry out the first annealing process again afterwards, the shape in the semiconductor substrate of the first groove bottom of second second area
At oxide skin(coating), second groove is formed；Remove the photoresist layer；In the first area and the institute of second second area
It states and forms photoresist layer in semiconductor substrate；Using the photoresist layer as mask, the second note oxygen technique, the second note oxygen technique are carried out
Carry out the second annealing process again afterwards, the shape in the semiconductor substrate of the first groove bottom of first second area
At oxide skin(coating), third groove is formed；Remove the photoresist layer.
Optionally, the first note oxygen and second note oxygen technique are O +ion implanted technique.
Optionally, the direction of O +ion implanted is partly led with described in first note oxygen technique and second note oxygen technique
The angle that the surface of body substrate is constituted is 60 °~120 °.
Optionally, in first note oxygen technique O +ion implanted dosage be 1E14~5E18sccm, energy be 50~
250Kev。
Optionally, oxonium ion dosage is 1E14~5E18sccm in second note oxygen technique, and energy is 50~250Kev.
Optionally, first annealing process and second annealing process are furnace anneal or short annealing.
Optionally, when first annealing process and second annealing process are furnace anneal, furnace tube temperature 800
DEG C~1300 DEG C, annealing time is 1~5 hour.
Optionally, when first annealing process and second annealing process are short annealing, annealing temperature is 900 DEG C
~1100 DEG C, annealing time is 3 seconds~30 minutes.
Optionally, before forming first groove, further include：Pad oxide is formed on the semiconductor substrate；Institute
It states and forms silicon nitride layer on pad oxide.
Compared with prior art, technical solution of the present invention has the advantages that：
The shallower first groove of depth is first formed in semiconductor substrate, further according to different needs in different second areas
The annealing process after note oxygen technique and note oxygen technique is carried out respectively to adjust the trench isolations depth of different second areas, by
In note oxygen technique be doping or ion implanting by way of in semiconductor substrate inject oxygen after, make the oxygen of doping or injection from
Son reacts to form the oxide skin(coating) with isolation features with semiconductor substrate, and ditch is promoted while deepening the depth of isolation structure
Slot isolation effect, and then exposed film layer can be effectively prevent not to be corroded and damage, avoid the exposure between different zones
Film layer and shielded film layer between generate difference in height.
Further, by controlling the parameters such as dosage, energy of O +ion implanted in note oxygen technique, groove can be adjusted well
The depth of isolation, effectively improves process window, and the efficiency of technique is effectively increased while improving yield of devices.
Description of the drawings
Fig. 1 is a kind of structural schematic diagram of back side illumination image sensor；
Fig. 2 to Fig. 5 is the corresponding structure of each step of back side illumination image sensor forming method in first embodiment of the invention
Schematic diagram；
Fig. 6 to Figure 11 is the corresponding structure of each step of back side illumination image sensor forming method in second embodiment of the invention
Schematic diagram.
Specific implementation mode
In the manufacturing process of existing back side illumination image sensor, need to form groove in semiconductor substrate.Such as：
The photodiode area of semiconductor substrate occurs photo-generated carrier diffusion, causes figure in order to prevent between different pixels region
The problem of image distortion, needs to form trench isolations between photodiodes.Meanwhile in semiconductor substrate further including other areas
Domain, such as logic region are also required to form trench isolations between each circuit unit of logic region.But photoelectricity
The requirement of diode area and logic region to trench isolations depth is different, needs to form the trench isolations knot of different depth
Structure.
Specifically, formation back side illumination image sensor technique shown in FIG. 1 can be referred to.
Referring to Fig.1, semiconductor substrate 10 is provided, the semiconductor substrate 10 includes first area I and second area II, institute
It states and is formed with discrete photodiode 20 in the I of first area, discrete circuit unit 30 is formed in the second area II.
Specific formation process is as follows：First the first photoresist layer (not shown) is coated on the surface of semiconductor substrate 10；It is right
First photoresist layer is patterned；Using patterned first photoresist layer as mask, to the semiconductor substrate 10 into
Row etching, forms first groove 40 between each photodiode 20 and between each circuit unit 30.Described in removal
First photoresist layer.
Then, it is coated with the second photoresist layer on 10 surface of the semiconductor substrate；Pattern is carried out to second photoresist
Change, the second photoresist layer is made to cover the first area I；Using patterned second photoresist layer as mask, along first ditch
Slot carries out intensification etching, and second groove 50, the second groove are formed between each circuit unit 30 of the second area II
50 depth is deeper than the first groove 40.Then, the full insulation of filling in the second groove 50 and the first groove 40
Substance (not shown) forms isolation structure.
The present inventor in the second area II using the above method by the study found that form second ditch
When slot, since etch media can also remove the film layer of exposed segment thickness in etching process, photoetching in different zones is caused
Prodigious difference in height is formed between film layer and the film layer being exposed under etch media under glue protection, subsequent chemical machinery is thrown
Light (CMP) technique generates prodigious burden.
To solve the technical problem, the present invention provides a kind of forming method of imaging sensor, first in semiconductor substrate
It is interior to form shallower groove, deepen the groove isolation construction of different zones by note oxygen technique and annealing process further according to demand
Depth is isolated.Since note oxygen technique is to inject oxonium ion in semiconductor substrate by way of doping or ion implanting, make to mix
Miscellaneous or injection oxonium ion reacts to form the oxide skin(coating) with isolation features with semiconductor substrate, in the depth for deepening isolation structure
Trench isolations effect is promoted while spending, and then exposed film layer can be effectively prevent not to be corroded and damage, and avoids difference
Difference in height is generated between the film layer of exposure between region and shielded film layer.
In addition, technical scheme of the present invention is also easily achieved to forming the technique that two or more trench isolations require, because
This this flexible method for adjusting trench isolations depth can expand process window.
Technical solution of the present invention is described in detail with reference to embodiment and attached drawing.
First embodiment
Fig. 2 to Fig. 5 is the corresponding structure of each step of back side illumination image sensor forming method in first embodiment of the invention
Schematic diagram.
With reference to figure 2, semiconductor substrate 100 is provided, the semiconductor substrate 100 includes first area I and second area II；
Pad oxide 110 is formed in the semiconductor substrate 100；Silicon nitride layer 111 is formed on the pad oxide 110.
In the present embodiment, the semiconductor substrate 100 can be silicon substrate or the material of the semiconductor substrate 100
Can also be germanium, SiGe, silicon carbide, GaAs or gallium indium, the semiconductor substrate 100 can also be the silicon on insulator
Germanium substrate on substrate or insulator, or growth have the substrate of epitaxial layer.
In the present embodiment, the first area I is pixel unit area, the semiconductor substrate 100 of the first area I
Extended meeting forms discrete photodiode after interior, and the photodiode is sensor devices, and the optical signal received is converted
For electric signal.In order to meet the semiconductor substrate 100 overall thickness thinning requirement, usual each photodiode is described
Position in semiconductor substrate 100 lies substantially in same depth.The second area II is logic circuit area, secondth area
Extended meeting forms discrete circuit unit after in the semiconductor substrate 100 of domain II.
In the present embodiment, the technique for forming the pad oxide 110 is thermal oxidation method or chemical vapour deposition technique；The pad
The material of oxide layer 110 can be silica.
In the present embodiment, the technique for forming the silicon nitride layer 111 is chemical vapour deposition technique；The silicon nitride layer 111
It can also be substituted by silicon oxynitride layer.
As shown in figure 3, forming photoresist layer 160 on the surface of the silicon nitride layer 111；To the photoresist layer 160 into
Row patterning, defines groove figure；It is mask with patterned photoresist layer 160, along groove figure, is sequentially etched the nitrogen
SiClx layer 111, the pad oxide 110 and the semiconductor substrate 100 form the first ditch in the semiconductor substrate 100
Slot 140.
In the present embodiment, the technique for forming first photoresist layer 160 is spin-coating method.
In the present embodiment, it can be dry etch process to etch the method for forming the first groove 140.
In the present embodiment, the depth of the first groove 140 of formation is more shallow than the photodiode subsequently needed to form, light
It is isolated by well region between electric diode, the depth of the first groove 140 is shallower than photodiode, is to reduce dark current.
As shown in figure 4, the removal photoresist layer 160 shown in Fig. 3；Then, in the nitridation of the first area I
Photoresist layer 170 is formed on silicon layer 111, and the first area I is protected.It is mask with the photoresist layer 170,
Two region II in the direction of arrows, the first note oxygen work are carried out into the semiconductor substrate 100 of 140 bottom of the first groove
Skill, will be in the semiconductor substrate 100 of O +ion implanted to 140 bottom of the first groove；After the first note oxygen technique,
The first annealing process is carried out again, forms oxide skin(coating) 190 in 140 bottom of the first groove, the second area II's is described
First groove 140 and the oxide skin(coating) 190 constitute second groove 150, i.e. the depth of the second groove 150 is more than described the
One groove 140.
In the present embodiment, the method for removing first photoresist layer 160 is ashing method.
In the present embodiment, it is subsequently formed in the isolation depth ratio for the second groove 150 that the second area II is formed
Circuit unit it is deep, the electronic interferences between circuit unit can be prevented.
In the present embodiment, the method for forming photoresist layer 170 is spin-coating method.Although diagram is only formed on silicon nitride layer surface
The photoresist layer 170, photoresist layer 170 described in actual process can also enter to first ditch of the first area I
In slot.The photoresist layer 170 can be substituted by silicon nitride layer.
In the present embodiment, first note oxygen technique is O +ion implanted or doping process.In first note oxygen technique
The angle that the surface of the direction of O +ion implanted and the semiconductor substrate 100 is constituted is 60 °~120 °, preferably 85 °~
95 °, more excellent is 90 °.The O +ion implanted dosage is 1E14sccm~5E18sccm, and energy is 50Kev~250Kev.
In the present embodiment, first annealing process is furnace anneal or short annealing.When first annealing process is
When furnace anneal, furnace tube temperature is 800 DEG C~1300 DEG C, and annealing time is 1 hour~5 hours.When first annealing process
For short annealing when, annealing temperature be 900 DEG C~1300 DEG C, annealing time be 3 seconds~30 minutes.
By controlling the O +ion implanted dosage and energy of first note oxygen technique, O +ion implanted can be effectively controlled
The depth of the semiconductor substrate 100.Then by control the first annealing process temperature and annealing time, ensure oxonium ion with
The semiconductor substrate 100 is fully reacted.
As shown in figure 5, removing the photoresist layer 170 of the first area I.
In the present embodiment, the method for removing the photoresist layer 170 is ashing method.
After the first grooves 140 and the second groove 150 for forming different isolation depth, further described the
The full insulating materials of filling, forms groove isolation construction, wherein the second groove in one groove 140 and the second groove 150
Groove isolation construction in 150 is made of insulating materials and the oxide skin(coating) 190.Then, then remove silicon nitride layer and
Pad oxide；Discrete photodiode 120 is formed in the semiconductor substrate 100 of I in first area, in second area II
The semiconductor substrate 100 in form discrete circuit unit 130；Metal grate is formed in the semiconductor substrate 100.
Completely imaging sensor further includes：Filter layer, between the metal grate；Lens jacket is located at the filter
On photosphere.
Second embodiment
Fig. 6 to Figure 11 is the corresponding structure of each step of back side illumination image sensor forming method in second embodiment of the invention
Schematic diagram.
With reference to figure 6, semiconductor substrate 200 is provided, the semiconductor substrate 200 includes first area I and second area, institute
It includes the first second area II and the second second area III, the first second area II and described the two the to state second area
Two region III are located at the first area both sides I；Pad oxide 210 is formed in the semiconductor substrate 200；In the pad
Silicon nitride layer 211 is formed in oxide layer 210.
In the present embodiment, the material of the semiconductor substrate 200, the material of the pad oxide 210 and formation process, institute
It is identical with first embodiment to state material and formation process of silicon nitride layer 211 etc., repeats no more in this embodiment.
In the present embodiment, the first area I is pixel unit area, the semiconductor substrate 200 of the first area I
It is inside subsequently formed discrete photodiode, the photodiode is sensor devices, and the optical signal received is converted
For electric signal.In order to meet the semiconductor substrate 200 overall thickness thinning requirement, usual each photodiode is described
Position in semiconductor substrate 200 lies substantially in same depth.Described two second areas are logic circuit area, and described
It is subsequently formed the first discrete circuit unit in the semiconductor substrate 200 of one second area II, the two the second area
Discrete second circuit unit is subsequently formed in the semiconductor substrate 200 of domain III.
As shown in fig. 7, forming photoresist layer 260 on the surface of the silicon nitride layer 211；To the photoresist layer 260 into
Row patterning, defines groove figure；It is mask with patterned photoresist layer 260, along groove figure, is sequentially etched the nitrogen
SiClx layer 211, the pad oxide 210 and the semiconductor substrate 200 form the first ditch in the semiconductor substrate 200
Slot 240.
In the present embodiment, the technique for forming the photoresist layer 260 is spin-coating method.
In the present embodiment, it can be etching technics to etch the method for forming the first groove 240, and the etching technics is
Dry etching.
In the present embodiment, the depth of the first groove 240 of formation is more shallow than the photodiode being subsequently formed, photoelectricity two
It is isolated by well region between pole pipe, the depth of the first groove 240 is shallower than photodiode, is to reduce dark current.
As shown in figure 8, the removal photoresist layer 260 shown in Fig. 7；Described the first of the semiconductor substrate 200
Region I and the first second area II form photoresist layer 270, to the first area I and the first non-processing second area II
It is protected.Be mask with the photoresist layer 270, the second second area III in the direction of arrows, to the first groove
The first note oxygen technique is carried out in the semiconductor substrate 200 of 240 bottoms, by O +ion implanted to 240 bottom of the first groove
In the semiconductor substrate 200 in portion；In the first note oxygen technique and then the first annealing process is carried out, in the first groove
First oxide skin(coating) 280 is formed on 240 bottoms, and the first groove 240 of the second second area III is aoxidized with described first
Nitride layer 280 constitutes second groove 250, i.e. the depth of the second groove 250 is more than the first groove 240.
In the present embodiment, the method for removing the photoresist layer 260 is ashing method.Form photoresist layer 270 and removal light
The method of photoresist layer 270 is consistent with formation and removal photoresist layer 260.Although diagram is only formed on 211 surface of silicon nitride layer
The photoresist layer 270, photoresist layer 270 described in actual process can also enter to first ditch of the first area I
In the first groove of slot and the first second area II.
In the present embodiment, first note oxygen technique is O +ion implanted or doping process.In first note oxygen technique
The angle that the surface of the direction of O +ion implanted and the semiconductor substrate 200 is constituted is 60 °~120 °, preferably 85 °~
95 °, more excellent is 90 °.The O +ion implanted dosage is 1E14sccm~5E18sccm, and energy is 50Kev~250Kev.
In the present embodiment, first annealing process is furnace anneal or short annealing.When first annealing process is
When furnace anneal, furnace tube temperature is 800 DEG C~1300 DEG C, and annealing time is 1 hour~5 hours.When first annealing process
For short annealing when, annealing temperature be 900 DEG C~1300 DEG C, annealing time be 3 seconds~30 minutes.
By controlling the O +ion implanted dosage and energy of first note oxygen technique, O +ion implanted can be effectively controlled
The depth of the semiconductor substrate 200 of second second area III.Then the temperature by the first annealing process of control and annealing
Time ensures that the semiconductor substrate 200 of oxonium ion and the first groove bottom of the second second area III is fully anti-
It answers.
In the present embodiment, the second groove 250 that the second second area III is formed isolation depth than subsequent the
Two circuit units are deep, can prevent the electronic interferences between second circuit unit.
As shown in figure 9, removing the photoresist layer 270 of the first area I and the first second area II.
In the present embodiment, the method for removing the photoresist layer 270 is ashing method.
Then, as shown in Figure 10, in the first area I of the semiconductor substrate 200 and the second second area III shapes
At photoresist layer 271, the first area I and non-processing second second area III are protected.With the photoresist layer
271 be mask, the first second area II in the direction of arrows, to the semiconductor substrate 200 of 240 bottom of the first groove
The second note oxygen technique of interior progress, will be in the semiconductor substrate 200 of O +ion implanted to 240 bottom of the first groove；
The second annealing process of second note oxygen technique and then progress forms the second oxide skin(coating) 290 in 240 bottom of the first groove,
The first groove 240 of the first second area II constitutes third groove 251, i.e. institute with second oxide skin(coating) 290
The depth for stating third groove 251 is more than the first groove 240.
In the present embodiment, the method for removing the photoresist layer 260 is ashing method.Form photoresist layer 270 and removal light
The method of photoresist layer 270 is consistent with formation and removal photoresist layer 260.Although diagram is only formed on 211 surface of silicon nitride layer
The photoresist layer 270, photoresist layer 270 described in actual process can also enter to first ditch of the first area I
In the first groove of slot and the first second area II.
In the present embodiment, second note oxygen technique is O +ion implanted or doping process.In second note oxygen technique
The angle that the surface of the direction of O +ion implanted and the semiconductor substrate 200 is constituted is 60 °~120 °, preferably 85 °~
95 °, more excellent is 90 °.The O +ion implanted dosage is 1E14sccm~5E18sccm, and energy is 50Kev~250Kev.Second
O +ion implanted dosage and the first note oxygen technique of energy ratio are big in note oxygen technique, therefore second oxide skin(coating) 290 formed
Thickness be more than the thickness of first oxide skin(coating) 280, i.e. the isolation depth of the third groove 251 is more than second ditch
The isolation depth of slot 250.
In the present embodiment, second annealing process is furnace anneal or short annealing.When second annealing process is
When furnace anneal, furnace tube temperature is 800 DEG C~1300 DEG C, and annealing time is 1 hour~5 hours.When second annealing process
For short annealing when, annealing temperature be 900 DEG C~1300 DEG C, annealing time be 3 seconds~30 minutes.
By controlling the O +ion implanted dosage and energy of second note oxygen technique, O +ion implanted can be effectively controlled
The depth of semiconductor substrate 200 described in first second area II.When then by temperature and the annealing of the second annealing process of control
Between, ensure that oxonium ion is fully reacted with the semiconductor substrate 200 of the first groove bottom of the first second area II.
In the present embodiment, the first second area II formed 251 depth of third groove than be subsequently formed first
Circuit unit is deep, can prevent the electronic interferences between the first circuit unit.
As shown in figure 11, the photoresist layer 271 of the first area I and the second second area III are removed.
In the present embodiment, the method for removing the photoresist layer 271 is ashing method.
In the first groove 240, the second groove 250 and the third groove 251 for forming different isolation depth
Afterwards, the further full insulating materials of filling, formation in the first groove 240, the second groove 250 and third groove 251
Groove isolation construction.Then, silicon nitride layer and pad oxide are removed then；The shape in the semiconductor substrate 200 of first area I
At discrete photodiode 220, the first discrete circuit is formed in the semiconductor substrate 200 of the first second area II
Unit 230, the semiconductor substrate 200 of the second second area III is interior to form discrete second circuit unit 231；
Metal grate is formed in semiconductor substrate.
Completely imaging sensor further includes：Filter layer, between the metal grate；Lens jacket is located at the filter
On photosphere.
In the present embodiment, controlled half described in O +ion implanted by controlling dosage and the energy of the oxonium ion of note oxygen technique
The depth of conductor substrate 200, the i.e. depth of trench isolations.Although dosage used by the first note oxygen technique and the second note oxygen technique
It is consistent with energy range, but if the depth of the third groove 251 is more than the depth of the second groove 250, same
It is in range that the dosage of the second note oxygen technique and the first note oxygen technique of ratio of energy adjustment is big.
In addition to above-mentioned two embodiment, note oxygen technique and annealing process can also be used to be formed according to process requirements
The groove isolation construction of three kinds or more trench isolations depth, this flexible method for adjusting trench isolations depth can expand work
Skill window.
Although the present invention discloses as above in a preferred embodiment thereof, it is not for limiting the present invention, any ability
Field technique personnel without departing from the spirit and scope of the present invention, may be by the methods and technical content of the disclosure above to this
Inventive technique scheme makes possible variation and modification, therefore, every content without departing from technical solution of the present invention, according to this hair
Bright technical spirit belongs to the technology of the present invention to any simple modifications, equivalents, and modifications made by embodiment of above
The protection domain of scheme.
Claims (17)
1. a kind of forming method of imaging sensor, which is characterized in that including：
Semiconductor substrate is provided, the semiconductor substrate includes adjacent first area and at least one second area；
First groove is formed in the semiconductor substrate；
Photoresist layer is formed in the semiconductor substrate of the first area and the non-processing second area；
Using the photoresist layer as mask, note oxygen technique is carried out, annealing process is carried out again after noting oxygen, in need to process described second
Oxide skin(coating) is formed in the semiconductor substrate of the first groove bottom in region；
Remove the photoresist layer；
Using above-mentioned flow, the second area processed successively in different need carries out note oxygen technique and annealing process, at this
Oxide skin(coating), the different second area shapes are formed in the semiconductor substrate of the first groove bottom of the second area
At the oxide skin(coating) of different-thickness.
2. the forming method of imaging sensor as described in claim 1, which is characterized in that when the second area is one
When：
First groove is formed in the semiconductor substrate；
The photoresist layer is formed in the semiconductor substrate of the first area；
Using the photoresist layer as mask, the first note oxygen technique is carried out, the first annealing process is carried out again after the first note oxygen technique, the
Oxide skin(coating) is formed in the semiconductor substrate of one channel bottom, forms second groove；
Remove the photoresist layer.
3. the forming method of imaging sensor as claimed in claim 2, which is characterized in that first note oxygen technique be oxygen from
Sub- injection technology.
4. the forming method of imaging sensor as claimed in claim 3, which is characterized in that in first note oxygen technique oxygen from
The angle that the direction of son injection is constituted with the surface of the semiconductor substrate is 60 °~120 °.
5. the forming method of imaging sensor as claimed in claim 4, which is characterized in that the O +ion implanted dosage is
1E14sccm~5E18sccm, energy are 50Kev~250Kev.
6. the forming method of imaging sensor as claimed in claim 2, which is characterized in that first annealing process is boiler tube
Annealing or short annealing.
7. the forming method of imaging sensor as claimed in claim 6, which is characterized in that when first annealing process is stove
When pipe is annealed, furnace tube temperature is 800 DEG C~1300 DEG C, and annealing time is 1 hour~5 hours.
8. the forming method of imaging sensor as claimed in claim 6, which is characterized in that when first annealing process is fast
When fast annealing, annealing temperature is 900 DEG C~1300 DEG C, and annealing time is 3 seconds~30 minutes.
9. the forming method of imaging sensor as described in claim 1, which is characterized in that when the second area is two
When, the first second area and the second second area are located at first area both sides：
First groove is formed in the semiconductor substrate；
Photoresist layer is formed in the semiconductor substrate of the first area and first second area；
Using the photoresist layer as mask, the first note oxygen technique is carried out, the first annealing process is carried out again after the first note oxygen technique,
Oxide skin(coating) is formed in the semiconductor substrate of the first groove bottom of second second area, forms the second ditch
Slot；
Remove the photoresist layer；
Photoresist layer is formed in the semiconductor substrate of the first area and second second area；
Using the photoresist layer as mask, the second note oxygen technique is carried out, the second annealing process is carried out again after the second note oxygen technique,
Oxide skin(coating) is formed in the semiconductor substrate of the first groove bottom of first second area, forms third ditch
Slot；
Remove the photoresist layer.
10. the forming method of imaging sensor as claimed in claim 9, which is characterized in that the first note oxygen and described
Two note oxygen techniques are O +ion implanted technique.
11. the forming method of imaging sensor as claimed in claim 10, which is characterized in that first note oxygen technique and institute
It is 60 °~120 ° to state the angle that the direction of O +ion implanted and the surface of the semiconductor substrate are constituted in the second note oxygen technique.
12. the forming method of imaging sensor as claimed in claim 11, which is characterized in that oxygen in first note oxygen technique
Ion implantation dosage is 1E14sccm~5E18sccm, and energy is 50Kev~250Kev.
13. the forming method of imaging sensor as claimed in claim 11, which is characterized in that oxygen in second note oxygen technique
Ion dose is 1E14sccm~5E18sccm, and energy is 50Kev~250Kev.
14. the forming method of imaging sensor as claimed in claim 9, which is characterized in that first annealing process and institute
It is furnace anneal or short annealing to state the second annealing process.
15. the forming method of imaging sensor as claimed in claim 14, which is characterized in that when first annealing process and
When second annealing process is furnace anneal, furnace tube temperature is 800 DEG C~1300 DEG C, and annealing time is 1 hour~5 hours.
16. the forming method of imaging sensor as claimed in claim 14, which is characterized in that when first annealing process and
When second annealing process is short annealing, annealing temperature is 900 DEG C~1300 DEG C, and annealing time is 3 seconds~30 minutes.
17. the forming method of imaging sensor as described in claim 1, which is characterized in that before forming first groove, also
Including：
Pad oxide is formed on the semiconductor substrate；
Silicon nitride layer is formed on the pad oxide.
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| US20060063338A1 (en) * | 2004-09-20 | 2006-03-23 | Lsi Logic Corporation | Shallow trench isolation depth extension using oxygen implantation |
| CN101826458A (en) * | 2009-03-02 | 2010-09-08 | 中芯国际集成电路制造(上海)有限公司 | Etching method and double-depth groove formation method |
| CN101826485A (en) * | 2009-03-02 | 2010-09-08 | 中芯国际集成电路制造(上海)有限公司 | Method for forming dual-depth trench |
| US20110284985A1 (en) * | 2010-05-20 | 2011-11-24 | Globalfoundries Inc. | Shallow trench isolation extension |
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2018
- 2018-04-02 CN CN201810282396.1A patent/CN108470743A/en active Pending
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060063338A1 (en) * | 2004-09-20 | 2006-03-23 | Lsi Logic Corporation | Shallow trench isolation depth extension using oxygen implantation |
| CN101826458A (en) * | 2009-03-02 | 2010-09-08 | 中芯国际集成电路制造(上海)有限公司 | Etching method and double-depth groove formation method |
| CN101826485A (en) * | 2009-03-02 | 2010-09-08 | 中芯国际集成电路制造(上海)有限公司 | Method for forming dual-depth trench |
| US20110284985A1 (en) * | 2010-05-20 | 2011-11-24 | Globalfoundries Inc. | Shallow trench isolation extension |
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Application publication date: 20180831 |