KR100720492B1 - Cmos image sensor and method for manufacturing the same - Google Patents

Abstract

The present invention relates to a CMOS image sensor and a method of manufacturing the same, which effectively performs isolation for device isolation between pixels and improves crosstalk prevention and operation characteristics between pixels, and includes an active region including a photodiode region and a transistor region. A first conductivity type semiconductor substrate having a device isolation region defined therein, a trench formed to a predetermined depth in the device isolation region of the semiconductor substrate, and a junction formed in the trench and buried with an annealing process or an insulating material and having a thickness of 1 to 2 µm. A device isolation film having a depth, an oxygen diffusion region formed in the surface of the trench, and having a junction depth of 1 to 2 µm greater than that of the device isolation film, a gate electrode formed through a gate insulating film in an active region of the semiconductor substrate; Formed in the photodiode region at regular intervals from the device isolation layer Is a low concentration second conductivity type diffusion region, a high concentration second conductivity type diffusion region formed in the transistor region, and a low concentration first conductivity type diffusion region formed in the surface of the semiconductor substrate on which the low concentration second conductivity type diffusion region is formed. Characterized in that further comprises.

Image Sensor, Device Isolation, Photodiode, Oxygen Diffusion Zone, Trench

Description

CMOS image sensor and method for manufacturing the same

1 is an equivalent circuit diagram of a typical 4T CMOS image sensor

2 is a layout showing unit pixels of a general 4T CMOS image sensor

3A to 3F are cross-sectional views illustrating a method of manufacturing a CMOS image sensor according to the prior art along line II ′ of FIG. 2.

Figure 4 is a cross-sectional view showing a CMOS image sensor according to the present invention

5A to 5H are cross-sectional views illustrating a method of manufacturing a CMOS image sensor according to the present invention taken along line II ′ of FIG. 2.

Explanation of symbols for the main parts of the drawings

101 semiconductor substrate 102 epi layer

103: pad oxide film 104: pad nitride film

105: trench 106: oxygen diffusion region

107 device isolation film 108 gate insulating film

109: gate electrode 112: insulating film sidewall

111: low concentration n-type diffusion region 114: high concentration n + type diffusion region

The present invention relates to a CMOS image sensor, and more particularly to a CMOS image sensor and a method of manufacturing the same to improve the characteristics of the image sensor.

In general, an image sensor is a semiconductor device that converts an optical image into an electrical signal, and is generally classified into a charge coupled device (CCD) and a CMOS image sensor. .

In the charge coupled device (CCD), a plurality of photo diodes (PDs) for converting a signal of light into an electrical signal are arranged in a matrix form, and the photo diodes in each vertical direction arranged in the matrix form. A plurality of vertical charge coupled device (VCCD) formed between the plurality of vertical charge coupled devices (VCCD) for vertically transferring charges generated in each photodiode, and horizontally transferring charges transferred by the respective vertical charge transfer regions; A horizontal charge coupled device (HCCD) for transmitting to the sensor and a sense amplifier (Sense Amplifier) for outputting an electrical signal by sensing the charge transmitted in the horizontal direction.

However, such a CCD has a disadvantage in that the manufacturing method is complicated because the driving method is complicated, the power consumption is large, and the multi-step photo process is required.

In addition, the charge coupling device has a disadvantage in that it is difficult to integrate a control circuit, a signal processing circuit, an analog-to-digital conversion circuit (A / D converter), and the like into a charge coupling device chip, which makes it difficult to downsize the product.

Recently, CMOS image sensors have attracted attention as next generation image sensors for overcoming the disadvantages of the charge coupled device.

The CMOS image sensor uses CMOS technology that uses a control circuit, a signal processing circuit, and the like as peripheral circuits to form MOS transistors corresponding to the number of unit pixels on a semiconductor substrate, thereby forming the MOS transistors of each unit pixel. The device adopts a switching method that sequentially detects output.

That is, the CMOS image sensor implements an image by sequentially detecting an electrical signal of each unit pixel by a switching method by forming a photodiode and a MOS transistor in the unit pixel.

The CMOS image sensor has advantages such as relatively low power consumption, a simple manufacturing process with a relatively small number of photo process steps, and the like.

In addition, since the CMOS image sensor can integrate a control circuit, a signal processing circuit, an analog / digital conversion circuit, and the like into the CMOS image sensor chip, the CMOS image sensor has an advantage of easy miniaturization.

Therefore, the CMOS image sensor is currently widely used in various application parts such as a digital still camera, a digital video camera, and the like.

CMOS image sensors are classified into 3T type, 4T type, and 5T type according to the number of transistors. The 3T type consists of one photodiode and three transistors, and the 4T type consists of one photodiode and four transistors.

Herein, the layout of the unit pixels of the 4T-type CMOS image sensor will be described.

1 is an equivalent circuit diagram of a general 4T CMOS image sensor, and FIG. 2 is a layout showing unit pixels of a typical 4T CMOS image sensor.

As illustrated in FIG. 1, the unit pixel 100 of the CMOS image sensor includes a photo diode 10 as a photoelectric converter and four transistors.

Here, each of the four transistors is a transfer transistor 20, a reset transistor 30, a source floor transistor 40, and a select transistor 50. In addition, the load transistor 60 is electrically connected to the output terminal OUT of each unit pixel 100.

Here, reference numeral FD is a floating diffusion region, Tx is a gate voltage of the transfer transistor 20, Rx is a gate voltage of the reset transistor 30, Dx is a gate voltage of the source floor transistor 40, Sx Is the gate voltage of the select transistor 50.

In the unit pixel of a typical 4T type CMOS image sensor, as shown in FIG. One photodiode PD is formed in a wide portion of the active region, and gate electrodes 23, 33, 43, and 53 of four transistors are formed in the active region of the remaining portion, respectively.

That is, the transfer transistor 20 is formed by the gate electrode 23, the reset transistor 30 is formed by the gate electrode 33, and the source floor transistor 40 is formed by the gate electrode 43. Is formed, and the select transistor 50 is formed by the gate electrode 53.

Here, impurity ions are implanted into the active region of each transistor except for the lower portion of each gate electrode 23, 33, 43, 53 to form a source / drain region S / D of each transistor.

3A to 3F are cross-sectional views illustrating a method of manufacturing a CMOS image sensor according to the prior art along line II ′ of FIG. 2.

As shown in FIG. 3A, an epitaxial process is performed on the high concentration P ++ type semiconductor substrate 61 to form a low concentration P-type epi layer 62.

Subsequently, an active region and an isolation region are defined in the semiconductor substrate 61, and an isolation layer 63 is formed in the isolation region using an STI process.

Here, although not shown, a method of forming the device isolation layer 63 will be described below.

First, a pad oxide film, a pad nitride film, and a TEOS (Tetra Ethyl Ortho Silicate) oxide film are sequentially formed on a semiconductor substrate, and a photoresist film is formed on the TEOS oxide film.

Subsequently, the photoresist is exposed and developed using a mask defining an active region and a device isolation region to pattern the photoresist. At this time, the photoresist of the device isolation region is removed.

The pad oxide film, the pad nitride film and the TEOS oxide film of the device isolation region are selectively removed using the patterned photoresist as a mask.

Subsequently, the semiconductor substrate in the device isolation region is etched to a predetermined depth using the patterned pad oxide film, the pad nitride film, and the TEOS oxide film as a mask to form a trench. Then, all of the photosensitive film is removed.

Subsequently, an insulating material is buried in the trench to form the device isolation layer 63 in the trench. Next, the pad oxide film, the pad nitride film, and the TEOS oxide film are removed.

 The gate insulating layer 64 and the conductive layer (for example, a high concentration polycrystalline silicon layer) are sequentially deposited on the entire epitaxial layer 62 on which the device isolation layer 63 is formed, and the conductive layer and the gate insulating layer are selectively removed. The gate electrode 65 is formed.

As shown in FIG. 3B, the first photosensitive film 66 is coated on the entire surface of the semiconductor substrate 61 including the gate electrode 65, the photodiode region is covered by an exposure and development process, and the source / drain of each transistor is shown. Pattern the area to be exposed.

The n-type diffusion region 67 is formed by implanting low concentration n-type impurity ions into the exposed source / drain region using the patterned first photoresist layer 66 as a mask.

As shown in FIG. 3C, after the first photoresist layer 66 is removed, the second photoresist layer 68 is coated on the entire surface of the semiconductor substrate 61, and blue, green ( Green) and red are patterned to expose each photodiode region.

In addition, low concentration n-type impurity ions are implanted into the epitaxial layer 62 using the patterned second photoresist layer 68 to form the blue, exposed, and red photodiode regions 69.

Here, impurity ion implantation for forming each photodiode region 69 is formed deeper by ion implantation with a higher energy than the low concentration n-type diffusion region 67 of the source / drain region.

Each photodiode region 69 is a source region of a reset transistor (Rx in FIGS. 1 and 2).

On the other hand, if a reverse bias is applied between each of the photodiode regions 69 and the low concentration P-type epi layer 62, a depletion layer is generated and electrons generated by the light source are turned off when the reset transistor is turned off. The potential of the floor transistor is lowered, and since the potential of the reset transistor is turned on and then turned off, the potential is continuously lowered to generate a voltage difference, thereby operating the image sensor using the signal processing.

Here, the depths A of the photodiode regions 69 are formed at the same depth as 2 to 4 µm.

In other words, impurity ions are implanted into each photodiode region with the same ion implantation energy to form the same depth.

As shown in FIG. 3D, the second photoresist film 68 is completely removed, an insulating film is deposited on the entire surface of the semiconductor substrate 61, and then an etch back process is performed on both sides of the gate electrode 65. The sidewall insulating film 70 is formed.

Subsequently, a third photoresist layer 71 is coated on the entire surface of the semiconductor substrate 61, and is patterned such that the photodiode region is covered and the source / drain regions of the transistors are exposed by exposure and development processes.

The n + type diffusion region 72 is formed by implanting high concentration n + type impurity ions into the exposed source / drain regions using the patterned third photoresist layer 71 as a mask.

As shown in FIG. 3E, after removing the third photoresist film 71 and applying the fourth photoresist film 73 to the entire surface of the semiconductor substrate 61, each photodiode region is exposed through an exposure and development process. Pattern as much as possible.

Subsequently, p0 type impurity ions are implanted into the photodiode region in which the n-type diffusion region 69 is formed using the patterned fourth photoresist layer 73 as a mask, thereby forming a p0 diffusion region 74 in the surface of the semiconductor substrate. To form.

As shown in FIG. 3F, the fourth photosensitive film 73 is removed, and the impurity diffusion region is diffused by performing a heat treatment process on the semiconductor substrate 61.

However, there is a problem in the method of manufacturing the CMOS image sensor according to the prior art as described above.

First, since the n-type diffusion region, which is a photodiode region, is included at the interface of the device isolation layer, the portion having the collapsed lattice structure during the trench etching to form the device isolation layer is an interface electron trap or a junction package ( It is vulnerable to low light by playing a role of junction leakage.

Second, since the red (R) light having a large wavelength reaches 5 to 10 μm in silicon, the device isolation film having a depth within 0.5 μm cannot be effectively isolated.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and provides a CMOS image sensor and a method of manufacturing the same, which effectively perform isolation for device separation between pixels and improve crosstalk prevention and operation characteristics between pixels. There is a purpose.

According to an embodiment of the present invention, a CMOS image sensor includes a first conductive semiconductor substrate having an active region and a device isolation region including a photodiode region and a transistor region, and a device isolation region of the semiconductor substrate. A trench formed to a predetermined depth, a device isolation film formed in the trench and having a junction depth of 1 to 2 µm by embedding an annealing process or an insulating material, and formed in the surface of the trench and having a thickness of 1 to 2 µm than that of the device isolation film. An oxygen diffusion region having a junction depth, a gate electrode formed in the active region of the semiconductor substrate via a gate insulating film, and a low concentration second conductivity type diffusion region formed in the photodiode region at regular intervals from the device isolation layer. And a high concentration second conductivity type diffusion region formed in the transistor region; Also it features configured by further comprising a low concentration first conductivity type diffusion regions formed in the surface of the semiconductor substrate of the second conductivity type diffusion regions formed.

In addition, the method for manufacturing the CMOS image sensor according to the present invention for achieving the above object is in the device isolation region of the first conductivity type semiconductor substrate in which an active region and a device isolation region consisting of a photodiode region and a transistor region are defined. Forming a trench having a predetermined depth; Implanting oxygen ions into the device isolation region of the trench-formed semiconductor substrate to form an oxygen diffusion region in the surface of the trench; Embedding an annealing process or an insulating material in the semiconductor substrate to form a device isolation layer having a depth of 1 to 2 μm in the trench; Forming a gate electrode through a gate insulating layer in an active region of the semiconductor substrate; Forming a low concentration second conductivity type diffusion region in said photodiode region; And forming a high concentration first conductivity type diffusion region in the transistor region.

Hereinafter, a CMOS image sensor and a method of manufacturing the same according to the present invention will be described in detail with reference to the accompanying drawings.

4 is a cross-sectional view showing the CMOS image sensor according to the present invention.

As shown in FIG. 4, the p-type epitaxial layer 102 formed on the p ++ type conductive semiconductor substrate 101 defined by an active region and a device isolation region composed of a photodiode region and a transistor region, and the semiconductor substrate. A trench 105 formed at a predetermined depth in the device isolation region to define an active region of the 101, an oxygen diffusion region 106 formed in the surface of the trench 105, and the oxygen diffusion region 106. The device isolation film 107 formed in the formed trench 105, the gate electrode 109 formed through the gate insulating film 108 in the active region of the semiconductor substrate 101, and the gate electrode 109. A low concentration n-type diffusion region 111 formed spaced apart from the device isolation layer 107 by a predetermined interval in one side of the photodiode region, an insulating film sidewall 112 formed on both sides of the gate electrode 109, The gate The highly concentrated n + type diffusion region 114 formed in the transistor region on the other side of the electrode 109 and the P0 type diffusion region 116 formed in the surface of the semiconductor substrate 101 on which the low concentration n-type diffusion region 111 is formed. It is configured to include.

Here, the device isolation layer 107 is formed to a depth of 1 ~ 2㎛, the oxygen diffusion region 106 is formed 1 ~ 2㎛ deeper than the device isolation layer 107.

5A through 5H are cross-sectional views illustrating a method of manufacturing a CMOS image sensor according to the present invention taken along line II ′ of FIG. 2.

As shown in FIG. 5A, the low-concentration first conductivity-type (P-type) epi layer 102 is applied to a semiconductor substrate 101 such as a high-concentration first conductivity type (P ++ type) single crystal silicon by an epitaxial process. Form.

Here, the epi layer 102 forms a large and deep depletion region in the photodiode in order to increase the ability of the low voltage photodiode to collect photocharge and further improve the light sensitivity.

On the other hand, the semiconductor substrate 101 may form a p-type epi layer on the n-type substrate.

As shown in FIG. 5B, a pad oxide film 103 is formed on the semiconductor substrate 101 on which the epi layer 102 is formed, and a pad nitride film 104 is formed on the pad oxide film 103.

Subsequently, the device isolation region is defined by selectively removing the pad nitride layer 104 and the pad oxide layer 103 through photo and etching processes.

The semiconductor substrate 101 is selectively removed by using the selectively removed pad nitride film 104 and pad oxide film 103 as a mask to form a trench 105 having a predetermined depth in the device isolation region.

Subsequently, oxygen (O 2) ions are implanted into the semiconductor substrate 101 on which the trench 105 is formed to form an oxygen diffusion region 106 in the surface of the trench 105.

As shown in FIG. 5C, an annealing process is performed on the semiconductor substrate 101 to diffuse oxygen ions implanted into the oxygen diffusion region 106 and to form an isolation layer 107 in the trench 105. do.

In this case, when the device isolation layer 107 anneals the semiconductor substrate 101 into which the oxygen ions have been implanted, a thermal oxide film is formed to fill the trench 105.

Meanwhile, since the device isolation layer 107 is formed in the trench 105 into which oxygen is injected, the device isolation layer 107 is formed to have a depth of 1 to 2 μm.

In an embodiment of the present invention, the device isolation layer 107 is formed through an annealing process. However, the present invention is not limited thereto, and the device isolation layer 107 may be formed through a planarization process such as CMP after depositing a separate insulating material. It may be formed in the trench 105.

In addition, the high concentration oxygen diffusion region 106 is formed to a junction depth of 1 ~ 2㎛ deeper than the device isolation layer 107.

As shown in FIG. 5D, the pad nitride film 104 and the pad oxide film 103 are removed, and the gate insulating film 108 and the conductive layer (for example, the entire surface of the epitaxial layer 102 on which the device isolation film 107 is formed). For example, a high concentration polycrystalline silicon layer) is sequentially deposited.

Here, the gate insulating film 108 may be formed by a thermal oxidation process or may be formed by a CVD method.

The conductive layer and the gate insulating layer are selectively removed to form the gate electrode 108.

Here, the gate electrode 109 becomes a gate electrode of the transfer transistor.

As shown in FIG. 5E, the first photosensitive film 110 is coated on the entire surface of the semiconductor substrate 101, and patterned so that each photodiode region is exposed through an exposure and development process.

The low concentration second conductive (n-type) impurity ions are implanted into the epitaxial layer 102 using the patterned first photoresist layer 110 as a mask to form an n-type diffusion region 111.

As shown in FIG. 5F, the first photoresist film 110 is completely removed, an insulating film is deposited on the entire surface of the semiconductor substrate 101, and an etch back process is performed to perform the gate electrode 109. The insulating film side wall 112 is formed in both sides of the ().

Subsequently, a second photoresist layer 113 is coated on the entire surface of the semiconductor substrate 101 on which the insulating film sidewalls 112 are formed, and each photodiode region is covered by an exposure and development process, and a source / drain region of each transistor is Pattern to expose.

The n + type diffusion region 114 is formed by implanting high concentration n + type impurity ions into the exposed source / drain regions using the patterned second photoresist layer 113 as a mask.

As shown in FIG. 5G, the second photoresist layer 113 is removed, the third photoresist layer 115 is coated on the entire surface of the semiconductor substrate 101, and each photodiode region is exposed through an exposure and development process. Pattern as much as possible.

Subsequently, the first conductive type (p0 type) impurity ions are implanted into the epitaxial layer 102 on which the n-type diffusion region 111 is formed using the patterned third photoresist film 115 as a mask. A p0 diffusion region 116 is formed in the surface of 102.

As shown in FIG. 5H, the third photosensitive film 115 is removed, and the impurity diffusion region is diffused by performing a heat treatment process on the semiconductor substrate 101.

Subsequently, although the process is not shown in the figure, the metal wiring of the plurality of interlayer insulating films is formed on the front surface, and then the color filter layer and the microlens are formed to complete the image sensor.

The present invention described above is not limited to the above-described embodiment and the accompanying drawings, and it is common in the art that various substitutions, modifications, and changes can be made without departing from the technical spirit of the present invention. It will be evident to those who have knowledge of.

CMOS image sensor and a method of manufacturing the same according to the present invention as described in detail above has the following advantages.

First, after implanting oxygen ions, an annealing process is performed to form an isolation layer and an oxygen diffusion region around the isolation layer to maximize isolation and prevent crosstalk between pixels.

Secondly, the photodiode region is prevented by the lattice defect region at the element isolation layer interface, thereby preventing the junction architecture and the interface electron trap at the interface, thereby improving the sensitivity of the image sensor.

Third, after the trench is formed, oxygen ions are implanted and the device isolation layer is formed through the annealing process, thereby forming a device isolation layer having a depth of 1 to 2 μm, thereby maximizing the isolation effect for device separation between pixels.

Claims (8)

A first conductivity type semiconductor substrate having an active region and a device isolation region formed of a photodiode region and a transistor region; A trench formed at a predetermined depth in the device isolation region of the semiconductor substrate; An isolation layer formed in the trench and having a junction depth of 1 to 2 μm by embedding an annealing process or an insulating material; An oxygen diffusion region formed in the surface of the trench and having a junction depth of 1 to 2 μm more than an element isolation film; A gate electrode formed in an active region of the semiconductor substrate via a gate insulating film; A low concentration second conductivity type diffusion region formed in the photodiode region at regular intervals from the device isolation layer; A high concentration second conductivity type diffusion region formed in the transistor region; And a low concentration first conductivity type diffusion region formed in a surface of the semiconductor substrate on which the low concentration second conductivity type diffusion region is formed. delete delete delete Forming a trench having a predetermined depth in an element isolation region of the first conductivity type semiconductor substrate in which an active region consisting of a photodiode region and a transistor region and an element isolation region are defined; Implanting oxygen ions into the device isolation region of the semiconductor substrate on which the trench is formed to form an oxygen diffusion region in the surface of the trench; Embedding an annealing process or an insulating material in the semiconductor substrate to form a device isolation layer having a depth of 1 to 2 μm in the trench; Forming a gate electrode through a gate insulating layer in an active region of the semiconductor substrate; Forming a low concentration second conductivity type diffusion region in the photodiode region; And forming a high concentration first conductivity type diffusion region in said transistor region. delete delete delete

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