KR100672686B1 - Cmos image sensor and method for manufacturing the same - Google Patents

Abstract

A CMOS image sensor and a method for manufacturing the same are provided to prevent dark current by forming an indium-diffusion region on an upper surface of a photodiode. A photodiode region(103) is formed at an active region of a substrate(101). An indium-diffused region(104) is formed on the surface of the photodiode region. An interlayer dielectric(105) is formed on the resultant structure. A color filter layer(106) is formed on the interlayer dielectric corresponding to the photodiode region. A planarization layer(107) is formed on the resultant structure. A micro-lens(108) is formed on the planarization layer corresponding to the color filter.

Description

CMOS image sensor and method for manufacturing the same

1 is an equivalent circuit diagram of a typical 4T CMOS image sensor

2 is a layout diagram showing unit pixels of a general 4T CMOS image sensor;

3A to 3E are cross-sectional views illustrating a method of manufacturing a CMOS image sensor according to the prior art.

FIG. 4 is a view showing a profile in which boron ions are implanted into an upper surface of a photodiode region in manufacturing a CMOS image sensor according to the prior art; FIG.

5 shows the potential according to the profile of FIG. 4.

6 is a cross-sectional view showing a CMOS image sensor according to the present invention

7A to 7E are cross-sectional views illustrating a method of manufacturing a CMOS image sensor according to the present invention.

FIG. 8 is a view showing a profile in which indium ions are implanted into an upper surface of a photodiode region when manufacturing a CMOS image sensor according to the present invention.

9 shows the potential according to the profile of FIG. 8.

Explanation of symbols for the main parts of the drawings

101 semiconductor substrate 102 device isolation film

103: photodiode region 104: indium diffusion region

105: interlayer insulating film 106: color filter layer

107: planarization layer 108: microlens

The present invention relates to a CMOS image sensor, and more particularly to a CMOS image sensor and a method of manufacturing the same to improve the characteristics of the image sensor.

In general, an image sensor is a semiconductor device that converts an optical image into an electrical signal, and is generally classified into a charge coupled device (CCD) and a CMOS image sensor. .

In the charge coupled device (CCD), a plurality of photo diodes (PDs) for converting a signal of light into an electrical signal are arranged in a matrix form, and the photo diodes in each vertical direction arranged in the matrix form. A plurality of vertical charge coupled device (VCCD) formed between the plurality of vertical charge coupled devices (VCCD) for vertically transferring charges generated in each photodiode, and horizontally transferring charges transferred by the respective vertical charge transfer regions; A horizontal charge coupled device (HCCD) for transmitting to the sensor and a sense amplifier (Sense Amplifier) for outputting an electrical signal by sensing the charge transmitted in the horizontal direction.

However, such a CCD has a disadvantage in that the manufacturing method is complicated because the driving method is complicated, the power consumption is large, and the multi-step photo process is required.

In addition, the charge coupling device has a disadvantage in that it is difficult to integrate a control circuit, a signal processing circuit, an analog / digital converter (A / D converter), and the like into a charge coupling device chip, which makes it difficult to miniaturize a product.

Recently, CMOS image sensors have attracted attention as next generation image sensors for overcoming the disadvantages of the charge coupled device.

The CMOS image sensor uses CMOS technology that uses a control circuit, a signal processing circuit, and the like as peripheral circuits to form MOS transistors corresponding to the number of unit pixels on a semiconductor substrate, thereby forming the MOS transistors of each unit pixel. The device adopts a switching method that sequentially detects output.

That is, the CMOS image sensor implements an image by sequentially detecting an electrical signal of each unit pixel by a switching method by forming a photodiode and a MOS transistor in the unit pixel.

The CMOS image sensor has advantages such as relatively low power consumption, a simple manufacturing process with a relatively small number of photo process steps, and the like.

In addition, since the CMOS image sensor can integrate a control circuit, a signal processing circuit, an analog / digital conversion circuit, and the like into the CMOS image sensor chip, the CMOS image sensor has an advantage of easy miniaturization.

Therefore, the CMOS image sensor is currently widely used in various application parts such as a digital still camera, a digital video camera, and the like.

On the other hand, CMOS image sensors are classified into 3T type, 4T type, and 5T type according to the number of transistors. The 3T type consists of one photodiode and three transistors, and the 4T type consists of one photodiode and four transistors.

Here, the equivalent circuit and the layout (lay-out) of the unit pixel of the 4T type CMOS image sensor will be described.

1 is an equivalent circuit diagram of a general 4T CMOS image sensor, and FIG. 2 is a layout showing unit pixels of a typical 4T CMOS image sensor.

As illustrated in FIG. 1, the unit pixel 100 of the CMOS image sensor includes a photo diode 10 as a photoelectric converter and four transistors.

Here, each of the four transistors is a transfer transistor 20, a reset transistor 30, a drive transistor 40, and a select transistor 50. In addition, the load transistor 60 is electrically connected to the output terminal OUT of each unit pixel 100.

Here, reference numeral FD is a floating diffusion region, Tx is a gate voltage of the transfer transistor 20, Rx is a gate voltage of the reset transistor 30, Dx is a gate voltage of the drive transistor 40, Sx is It is the gate voltage of the select transistor 50.

In the unit pixel of a typical 4T type CMOS image sensor, as shown in FIG. One photodiode PD is formed in a wide portion of the active region, and gate electrodes 23, 33, 43, and 53 of four transistors are formed in the active region of the remaining portion, respectively.

That is, the transfer transistor 20 is formed by the gate electrode 23, the reset transistor 30 is formed by the gate electrode 33, and the drive transistor 40 is formed by the gate electrode 43. The select transistor 50 is formed by the gate electrode 53.

Here, impurity ions are implanted into the active region of each transistor except for the lower portion of each gate electrode 23, 33, 43, 53 to form a source / drain region S / D of each transistor.

3A to 3E are cross-sectional views illustrating a method of manufacturing a CMOS image sensor according to the prior art.

As shown in FIG. 3A, the device isolation layer 62 is formed using a shallow trench isolation (STI) process or a LOCOS process in the device isolation region of the p-type semiconductor substrate 61 defined as the device isolation region and the active region. .

Here, a p-type epitaxial layer (not shown) is formed on the surface of the semiconductor substrate 61.

Subsequently, a photodiode region (PD) 63 is formed by implanting P (Phosphorus) or As (Arsenic), which is an n-type impurity ion, into an active region of the semiconductor substrate 61.

As shown in FIG. 3B, p-type impurity ions such as boron are implanted into the photodiode region 63 to form a p ⁰ -type diffusion region 64 in the surface.

Here, since electrons generated by defects present at the semiconductor substrate interface move from the surface to the photodiode region 63 to produce an unwanted signal, holes (or holes) are formed on the surface of the photodiode region 63. Holes are formed to form a large number of p ⁰ diffusion regions 64 so as to combine and remove electrons and holes.

As shown in FIG. 3C, an interlayer insulating film 65 is formed on the entire surface of the semiconductor substrate 61 including the photodiode region 63, a metal film is deposited on the interlayer insulating film 65, and then selectively patterned. To form various metal wires (not shown).

The interlayer insulating layer 65 and the metal wires may be formed of various layers, and a light blocking layer (not shown) may be formed on the interlayer insulating layer 65 to prevent light from entering the photodiode region 63. Formed.

As shown in FIG. 3D, a color filter layer 66 is applied to each of the wavelength bands by applying a blue, red, and green resist layer on the interlayer insulating layer 65 and then performing exposure and development processes. To form.

At this time, since the color filter layers 66 are formed through different photo and etching processes, the color filter layers 66 have different heights.

As shown in FIG. 3E, a planarization layer 67 is formed on the entire surface of the semiconductor substrate 61 including the color filter layer 66, and a material layer for forming a microlens is coated on the planarization layer 67. Subsequently, the material layer is patterned by an exposure and development process to form a microlens pattern.

Subsequently, the microlens pattern is reflowed to form a hemispherical microlens 68.

In this case, the microlens 68 is a polymer material and is weak in heat, and thus, the microlens 68 has no choice but to proceed in the last process during device fabrication.

In other words, the microlens 68 is manufactured in the form of a convex lens by applying, patterning, and applying a layer of material for microlens.

FIG. 4 is a view illustrating a profile in which boron ions are implanted into an upper surface of a photodiode region in manufacturing a CMOS image sensor according to the prior art, and FIG. 5 is a view showing potential according to the profile of FIG. 4.

As shown in FIG. 4, the boron itself has a small mass of 11, which diffuses well even in a small amount of heat, and thus has a high electron (e) at the surface region interface and decreases with depth from the semiconductor substrate.

Here, A is a region having many holes formed to reduce the dark current, and B represents a state in which the dark current is removed by combining electrons of the interface with holes of boron.

According to this profile, as shown in FIG. 5, the electrons e move to a higher potential.

The electrons that do not bond with the holes on the surface move toward the higher potential region and eventually to the lower photodiode region. This generates a dark current.

However, the manufacturing method of the CMOS image sensor according to the prior art as described above had the following problems.

That is, by forming a p ⁰ diffusion region on the upper surface of the photodiode region, holes and electrons are combined and removed, but electrons are not removed and dark current is generated to deteriorate the characteristics of the image sensor.

The present invention has been made to solve the above problems, the CMOS image sensor to improve the characteristics of the image sensor by preventing the dark current by forming indium ions having a mass larger than boron on the upper surface of the photodiode region and Its purpose is to provide its manufacturing method.

CMOS image sensor according to the present invention for achieving the above object is a photodiode region formed at a predetermined interval in the active region of the semiconductor substrate, an indium diffusion region formed on the upper surface of the photodiode region, and An interlayer insulating film formed on the front surface of the semiconductor substrate including the photodiode region, a color filter layer formed on the interlayer insulating film so as to correspond to each photodiode region, and a planarization layer formed on the front surface of the semiconductor substrate including the color filter layer. And a microlens formed on the planarization layer to correspond to the color filter layer.

In addition, the method for manufacturing the CMOS image sensor according to the present invention for achieving the above object comprises the steps of forming a photodiode region having a predetermined interval in the active region of the semiconductor substrate, the indium on the upper surface of the photodiode region Implanting ions to form an indium diffusion region, forming an interlayer insulating film on an entire surface of the semiconductor substrate including the photodiode region, and forming a color filter layer on the interlayer insulating film to correspond to each photodiode region. And forming a planarization layer on the entire surface of the semiconductor substrate including the color filter layer, and forming a microlens on the planarization layer to correspond to the color filter layer.

Hereinafter, the CMOS image sensor and a method of manufacturing the same according to the present invention will be described in detail with reference to the accompanying drawings.

6 is a structural cross-sectional view showing a CMOS image sensor according to the present invention.

As shown in FIG. 6, an isolation layer 102 formed in the isolation region of the semiconductor substrate 101 defined as an isolation region and an active region, and a photodiode formed in the active region of the semiconductor substrate 101. The front surface of the semiconductor substrate 101 including the region PD, the indium diffusion region 104 formed on the upper surface of the photodiode region 103, and the photodiode region 103. A semiconductor substrate 101 including an interlayer insulating film 105 formed on the interlayer insulating film 105, a color filter layer 106 formed on the interlayer insulating film 105 to correspond to each photodiode region 103, and the color filter layer 105. ) And a microlens 108 formed on the planarization layer 107 to correspond to the color filter layer 104.

7A to 7E are cross-sectional views illustrating a method of manufacturing a CMOS image sensor according to the present invention.

As shown in FIG. 7A, the device isolation layer 102 is formed using a shallow trench isolation (STI) process or a LOCOS process in the device isolation region of the semiconductor substrate 101 defined as the device isolation region and the active region.

Although not shown in the drawings, a method of forming the device isolation layer 102 will be described below.

First, a pad oxide film, a pad nitride film, and a TEOS (Tetra Ethyl Ortho Silicate) oxide film are sequentially formed on a semiconductor substrate, and a photoresist film is formed on the TEOS oxide film.

Subsequently, the photoresist is exposed and developed using a mask defining an active region and a device isolation region to pattern the photoresist. At this time, the photoresist of the device isolation region is removed.

The pad oxide film, the pad nitride film and the TEOS oxide film of the device isolation region are selectively removed using the patterned photoresist as a mask.

Subsequently, the semiconductor substrate in the device isolation region is etched to a predetermined depth using the patterned pad oxide film, the pad nitride film, and the TEOS oxide film as a mask to form a trench. Then, all of the photosensitive film is removed.

Subsequently, a thin sacrificial oxide film is formed on the entire surface of the substrate on which the trench is formed, and an O ₃ TEOS film is formed on the substrate to fill the trench. In this case, the sacrificial oxide film is also formed on the inner wall of the trench, and the O ₃ TEOS film proceeds at a temperature of about 1000 ° C. or more.

Subsequently, the O ₃ TEOS film is removed on the entire surface of the semiconductor substrate so as to remain only in the trench region by a chemical mechanical polishing (CMP) process to form a device isolation layer 102 in the trench. Next, the pad oxide film, the pad nitride film, and the TEOS oxide film are removed.

Here, a p-type epitaxial layer (not shown) is formed on the surface of the semiconductor substrate 101.

Next, a photodiode region (PD) 103 is formed by implanting P (Phosphorus) or As (Arsenic), which is an n-type impurity ion, into the active region of the semiconductor substrate 101.

As shown in FIG. 7B, indium ions are implanted into the photodiode region 103 to form an indium diffusion region 104 in the surface.

Here, since electrons generated by defects present at the semiconductor substrate interface move from the surface to the photodiode region 103 to produce an unwanted signal, holes are formed on the surface of the photodiode region 103. Holes are formed to form many indium diffusion regions 104 to combine and remove electrons and holes.

The indium diffusion region 104 is formed with an ion implantation energy of 40 KeV to 60 KeV and a dose of 5E11 to 5E12 atoms / cm 2.

As shown in FIG. 7C, an interlayer insulating film 105 is formed on the entire surface of the semiconductor substrate 101 including the photodiode region 103, a metal film is deposited on the interlayer insulating film 105, and then selectively patterned. To form various metal wires (not shown).

The interlayer insulating layer 105 and the metal wires may be formed of various layers, and a light blocking layer (not shown) may be formed on the interlayer insulating layer 105 to prevent light from entering the photodiode region 103. Formed.

As shown in FIG. 7D, after applying a blue, red, and green resist layer on the interlayer insulating layer 105, the color filter layer 106 for filtering light for each wavelength band by performing exposure and development processes To form.

At this time, since the color filter layers 106 are formed through different photo and etching processes, the color filter layers 106 have different heights.

As shown in FIG. 7E, a planarization layer 107 is formed on the entire surface of the semiconductor substrate 101 including the color filter layer 106, and a material layer for forming a microlens is coated on the planarization layer 107. Subsequently, the material layer is patterned by an exposure and development process to form a microlens pattern.

Subsequently, the microlens pattern is reflowed at a temperature of 150 to 300 ° C. to form a hemispherical microlens 108.

That is, the microlens 108 is manufactured in the form of a convex lens by applying, patterning, and applying a layer of material for microlens.

FIG. 8 is a view illustrating a profile in which indium ions are implanted into an upper surface of a photodiode region during fabrication of the CMOS image sensor according to the present invention, and FIG. 9 is a view illustrating potentials according to the profile of FIG. 8.

As shown in FIG. 8, the mass of indium is 114, which does not move well once ion implanted, thereby easily making the subsurface a high concentration and making the surface smaller than this to make the potential as shown in FIG. 9. Can be.

Therefore, the potential at the lower surface of the surface having a smaller potential than the surface can be prevented from moving to the photodiode region by creating an energy barrier against electron (e) movement.

The present invention described above is not limited to the above-described embodiment and the accompanying drawings, and it is common in the art that various substitutions, modifications, and changes can be made without departing from the technical spirit of the present invention. It will be evident to those who have knowledge of.

CMOS image sensor and a method of manufacturing the same according to the present invention as described in detail above has the following advantages.

That is, a p-type diffusion region for preventing dark current is formed on the upper surface of the photodiode region by injecting indium ions with a heavier mass instead of boron to increase the concentration of the lower portion of the surface than the surface to act as an energy barrier for electrons to prevent dark current. The characteristics of the sensor can be improved.

Claims (4)

A photodiode region formed at regular intervals in the active region of the semiconductor substrate, An indium diffusion region formed on an upper surface of the photodiode region; An interlayer insulating film formed on the entire surface of the semiconductor substrate including the photodiode region; A color filter layer formed on the interlayer insulating layer so as to correspond to each of the photodiode regions; A planarization layer formed on an entire surface of the semiconductor substrate including the color filter layer; And a microlens formed on the planarization layer to correspond to the color filter layer. Forming a photodiode region at regular intervals in the active region of the semiconductor substrate; Implanting indium ions into an upper surface of the photodiode region to form an indium diffusion region; Forming an interlayer insulating film on an entire surface of the semiconductor substrate including the photodiode region; Forming a color filter layer on the interlayer insulating layer so as to correspond to each of the photodiode regions; Forming a planarization layer on an entire surface of the semiconductor substrate including the color filter layer; And forming a microlens on the planarization layer to correspond to the color filter layer. The method of claim 2, wherein the indium ions are implanted with an ion implantation energy of 40 to 60 KeV. The method of claim 2, wherein the indium ions are implanted at a dose of 5E11 to 5E12 atoms / cm 2.

Images