CN101826485A - Method for forming dual-depth trench - Google Patents
Method for forming dual-depth trench Download PDFInfo
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- CN101826485A CN101826485A CN200910046894A CN200910046894A CN101826485A CN 101826485 A CN101826485 A CN 101826485A CN 200910046894 A CN200910046894 A CN 200910046894A CN 200910046894 A CN200910046894 A CN 200910046894A CN 101826485 A CN101826485 A CN 101826485A
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Abstract
The utility model relates to a method for forming a dual-depth trench, which includes the steps that: a semiconductor substrate, which sequentially consists of a silicon substrate, a buried oxide layer, a barrier layer and an oxide layer, is provided; the semiconductor substrate comprises a pixel area and a peripheral area; a photoresist pattern is formed on the oxide layer; with the photoresist pattern as a mask, the oxide layer is implanted with ions and annealed, so that an ion-implanted layer is formed in the oxide layer of the peripheral area; the oxide layer, the barrier layer, the buried oxide layer and the silicon substrate are etched, so that a first trench and a second trench are formed; and the depth of the first trench is smaller than the depth of the second trench. The invention can effectively increase the image quality of a CMOS image sensor.
Description
Technical field
The present invention relates to field of semiconductor manufacture, particularly a kind of double-depth groove formation method.
Background technology
Present charge coupled device (charge coupled device, CCD) be main practicability solid-state image sensing device, have that the noise of reading is low, dynamic range is big, the response sensitivity advantages of higher, but CCD has the complementary metal oxide semiconductors (CMOS) (Complementary-Metal-Oxide-Semiconductor that is difficult to main flow simultaneously, CMOS) the compatible mutually shortcoming of technology, promptly the imageing sensor based on charge coupled device is difficult to realize that single-chip is integrated.And cmos image sensor (CMOS Imagesensor, CIS) owing to adopted identical CMOS technology, pel array and peripheral circuit can be integrated on the same chip, compare with charge coupled device, cmos image sensor has that volume is little, in light weight, low in energy consumption, programming is convenient, be easy to control and advantage that average unit cost is low.
Usually, in being the United States Patent (USP) of US2008/0265295A1, publication number can find the technology of conventional images transducer.Cmos image sensor comprises pixel unit array, as shown in Figure 1, each pixel cell has generally included photodiode active area a11, transistor active area a13, and the shallow trench isolation regions a12 between photodiode active area and transistor active area.Photodiode active area a11 and be defined as fill factor, curve factor with the area ratio of the corresponding total transistor active area (generally being made up of 3 or 4 transistors) of described photodiode active area a11, described fill factor, curve factor is one of greatest factor of weighing cmos image sensor picture quality.
The inventor finds on the basis that the whole pixel unit array gross area and transistor active area a13 area all can't change, in order to improve the cmos image sensor fill factor, curve factor, the interval that unique solution route only dwindles isolated area increases photodiode active area a11 area.Under the existing processes basis, the interval that dwindles isolated area can cause improving aspect ratio (the Aspect ratio of groove, A/R) or reduce the degree of depth of groove, and the aspect ratio that improves groove makes follow-up shallow trench isolation (shallow trench iso1ation, STI) problem in space appears in the raceway groove fill process, and the device fine ratio of product reduces; The degree of depth that reduces groove can influence peripheral circuit work, causes component failure.
Summary of the invention
The problem that the present invention solves provides a kind of double-depth groove formation method, can improve cmos image sensor picture quality effectively.
For addressing the above problem, the invention provides a kind of double-depth groove formation method, comprising: Semiconductor substrate is provided, and described Semiconductor substrate comprises silicon substrate, oxygen buried layer, barrier layer, oxide layer successively; Described Semiconductor substrate comprises pixel region and outer peripheral areas; On described oxide layer, form the photoresist figure; With the photoresist figure is mask, and oxide layer is carried out ion injection and annealing, forms ion implanted layer in the oxide layer of described outer peripheral areas; Etching oxidation layer, barrier layer, oxygen buried layer and silicon substrate form first groove and second groove; The degree of depth of described first groove is less than the degree of depth of second groove.
Compared with prior art, the present invention has the following advantages: by form the photoresist figure on described oxide layer; With the photoresist figure is mask, and oxide layer is carried out ion injection and annealing, forms ion implanted layer in the oxide layer of described outer peripheral areas; Etching oxidation layer, barrier layer, oxygen buried layer and silicon substrate form first groove and second groove; The degree of depth of described first groove is less than the degree of depth of second groove.Can make the cmos image sensor process in reality, groove at active area of isolation of pixel and peripheral active area of isolation formation different depth, that is to say, form the more shallow groove of the degree of depth at the active area of isolation of pixel, form lower aspect ratio, effectively increase the photodiode active area area, and can not increase difficulty, improve the cmos image sensor fill factor, curve factor effectively and and can not influence the operate as normal of pixel array circuit to subsequent process steps.Be with the source area of isolation outside and form the bigger groove of the degree of depth, can satisfy normal peripheral circuit job requirement, improved yield of devices.
Description of drawings
Fig. 1 is the pixel unit array ESEM picture of cmos image sensor;
Fig. 2 is the flow chart of the execution mode of double-depth groove formation method of the present invention;
Fig. 3 to Figure 11 is the schematic diagram of the embodiment of double-depth groove formation method of the present invention;
Embodiment
The invention provides a kind of double-depth groove formation method, comprising: Semiconductor substrate is provided, and described Semiconductor substrate comprises silicon substrate, oxygen buried layer, barrier layer, oxide layer successively; Described Semiconductor substrate comprises pixel region and outer peripheral areas; On described oxide layer, form the photoresist figure; With the photoresist figure is mask, and oxide layer is carried out ion injection and annealing, forms ion implanted layer in the oxide layer of described outer peripheral areas; Etching oxidation layer, barrier layer, oxygen buried layer and silicon substrate form first groove and second groove; The degree of depth of described first groove is less than the degree of depth of second groove.
Below in conjunction with accompanying drawing the embodiment that the present invention forms double-depth groove is described in detail.
With reference to Fig. 2, embodiment of the present invention provides a kind of double-depth groove formation method of pixel unit array, comprises the steps:
Step S1 provides Semiconductor substrate, and described Semiconductor substrate comprises silicon substrate, oxygen buried layer, barrier layer, oxide layer successively; Described Semiconductor substrate comprises pixel region and outer peripheral areas.
Step S2 forms the first photoresist figure on described oxide layer;
Step S3 is a mask with the first photoresist figure, and oxide layer is carried out ion injection and annealing, forms ion implanted layer in the oxide layer of described outer peripheral areas;
Step S4 removes the first photoresist figure;
Step S5 forms the second photoresist figure on described oxide layer and ion implanted layer;
Step S6 is a mask with the second photoresist figure, and etching forms first groove and second groove; Described first channel shaped is formed in pixel region, and described second channel shaped is formed in outer peripheral areas; The degree of depth of described first groove is less than the degree of depth of second groove.
Be elaborated for above-mentioned example procedure below in conjunction with accompanying drawing.In conjunction with Fig. 2 and shown in Figure 3, as described in step S1, provide Semiconductor substrate, described Semiconductor substrate comprises silicon substrate 100 successively, oxygen buried layer 110, barrier layer 120, oxide layer 130; Described Semiconductor substrate comprises pixel region IA and outer peripheral areas IIA.
Particularly, grid oxide layer 110 concrete formation technologies can or be the CVD deposition process for known oxidizing process.Be example exemplary illustration in addition with the oxidizing process in the present embodiment, oxidation can be carried out in the tubular type oxidation furnace, and oxidizing temperature is 750 ℃ to 1100 ℃, and reaction atmosphere can be N
2, H
2, O
2Any two of perhaps above three kinds of gases or three kinds of mists that all comprise.Preferred scheme can be at pure O
2Atmosphere, temperature are that 850 ℃, reaction time are 5 minutes, oxidation; Then according to required oxidated layer thickness, at O
2And H
2Under the atmosphere, synthesize oxidation; Then at pure O
2Atmosphere, temperature are that 850 ℃, reaction time are 5 minutes, oxidation; At last at pure N
2Atmosphere, temperature are that 900 ℃, time are 30 minutes, annealing.
Particularly, the barrier layer 120 concrete technologies that form can be known plasma enhanced chemical vapor deposition method (Plasma Enhanced Chemical Vapor deposition, PECVD), reaction condition can be 200 watts to 500 watts of power, pressure is 2 handkerchief to 50 handkerchiefs, temperature is 200 ℃ to 800 ℃, and reacting gas is ammonia and silane.
Particularly, the oxide layer 130 concrete technologies that form can be known inferior aumospheric pressure cvd method (Sub-Atmospheric Chemical Vapor deposition, SACVD), specifically comprise, reaction cavity pressure is 100 handkerchief to 600 handkerchiefs, temperature is 200 ℃ to 600 ℃, and reacting gas is tetraethoxysilane (TEOS) and ozone (O
3), assist gas is N2 or Ar.Preferred scheme can be 200Pa for reaction pressure, and temperature is 500 ℃, and reacting gas is tetraethoxysilane (TEOS) and ozone (O
3), assist gas is Ar.
Prior art can form the consistent groove of the degree of depth with outer peripheral areas IIA at pixel region IA, can cause like this in order to improve the cmos image sensor fill factor, curve factor, the interval that dwindles isolated area increases the photodiode active area area, thereby improve groove aspect ratio (Aspect ratio, A/R) or reduce the degree of depth of groove.And the aspect ratio that has improved groove can cause follow-up shallow trench isolation difficulty, makes the device shallow trench isolation space occur easily and cause component failure.The minimizing of gash depth can cause gash depth can not satisfy the requirement of normal outer peripheral areas IIA circuit working, causes component failure.
In conjunction with Fig. 2 and shown in Figure 4, as described in step S2, on described oxide layer 130, form the first photoresist figure 140; Specifically comprise, on oxide layer 130, form the first photoresist figure 140; Specifically comprise photoresist in spin coating on the oxide layer 130 (not shown), and the formation photoresist figure 140 that exposes, develops.Described photoresist can form on described oxide layer 130 by modes such as for example rotary coating.After the coating photoresist, by exposure mask pattern is transferred on the photoresist from mask, and utilized developer solution that the photoresist of corresponding site is removed to form the photoresist figure 140 consistent with mask pattern.
The photoresist of the described formation first photoresist figure can be eurymeric photoresist or negative photoresist, and preferred version is a negative photoresist, specifically comprises, the first photoresist figure 140 of described formation forms covering pixel region IA and exposes outer peripheral areas IIA.That is to say that the formation first photoresist figure 140 is opposite with the figure that the light shield that adopts traditional handicraft forms.Adopt negative photoresist to utilize existing light shield and need not make new light shield.Reduce the cost of making new light shield, saved expenditure.
In conjunction with Fig. 2 and shown in Figure 5, as described in step S3, be mask with the first photoresist figure 140, oxide layer is carried out ion inject 150, annealing.Form ion implanted layer 131 at described outer peripheral areas IIA; Described ion injects the 150 at least one ion implantation steps of can serving as reasons and constitutes, and such as injecting by secondary or three secondary ions, main purpose be at outer peripheral areas formation ion implanted layer.As an execution mode of present embodiment, the ion of described ion injection 150 is the N ion, and energy range is 20KeV to 40KeV, and dosage range is 3E14cm
-2To 5E15cm
-2, oxide layer 130 is carried out ion injects.Main purpose is injected for adopting the N ion, makes the oxide layer of outer peripheral areas IIA form rich N structure, exists simultaneously as Si-O-N structure or Si-N structure or above-mentioned two kinds of structures, forms ion implanted layer 131 (referring to shown in Figure 6).
Described annealing process can be tube annealing, pulse annealing or rapid thermal treatment annealing.As an execution mode of present embodiment, described ion is annealed into rapid thermal treatment annealing.Described annealing temperature is 600 ℃ to 1100 ℃; Annealing time is 10 to 100 seconds.As the preferred version of present embodiment, optional 1070 ℃ of annealing temperature, annealing time is 20.5 seconds.
In conjunction with Fig. 2 and shown in Figure 6, as described in step S4, remove the first photoresist figure; Remove photoresist process and can remove technology, comprise that photoresist is removed solution removal, plasma bombardment is removed or the like for known photoresist.
In conjunction with Fig. 2 and shown in Figure 7, as described in step S5, on described oxide layer 130 and ion implanted layer 131, form the second photoresist figure; Specifically comprise photoresist in spin coating on oxide layer 130 and the ion implanted layer 131, and the formation photoresist figure 160 that exposes, develops.Described photoresist can form on described oxide layer 130 and ion implanted layer 131 by modes such as for example rotary coating.After the coating photoresist, by exposure mask pattern is transferred on the photoresist from mask, and utilized developer solution that the photoresist of corresponding site is removed to form the photoresist figure 160 consistent with mask pattern.
In conjunction with Fig. 2 and Fig. 8, Fig. 9, Figure 10, shown in Figure 11, as described in step S6, be mask with the second photoresist figure, etching forms first groove 101 and second groove 102; Described first groove 101 is formed at pixel region IA, and described second groove 102 is formed at outer peripheral areas IIA; The degree of depth of described first groove 101 is less than the degree of depth of second groove 102.
Particularly, as shown in Figure 8, be mask with the second photoresist figure, the oxide layer 130 of pixel region IA and the ion implanted layer 131 of outer peripheral areas IIA are carried out etching, until the barrier layer 120 that exposes pixel region IA.Concrete technology can be for adopting known anisotropic plasma etching technics, and selection nitride etch rate and oxide etching rate ratio are 4: 1～8: 1 etching processing procedure.Selection process can be chosen reactive ion etching equipment, and the etching apparatus chamber pressure is 12 millitorrs, and the top radio-frequency power is 300 watts, and the bottom radio-frequency power is 60 watts, and upper electrode temperature is 70 ℃, and the hearth electrode temperature is 20 ℃.CHF
3Flow is 30SCCM (a per minute standard milliliter), CH
2F
2Flow is 50SCCM, O
2Flow is 10SCCM.Etching is until the barrier layer 120 that exposes outer peripheral areas IIA.
As shown in Figure 9, be mask with the second photoresist figure, etching is carried out on the barrier layer 120 of pixel region IA and the barrier layer 120 of outer peripheral areas IIA, until the substrate silicon 100 that exposes outer peripheral areas IIA.Concrete technology comprises that adopt known anisotropic plasma etching technics, selection process can be chosen reactive ion etching equipment, the etching apparatus chamber pressure is 20 millitorrs, and the top radio-frequency power is 600 watts, and the bottom radio-frequency power is 150 watts, upper electrode temperature is 70 ℃, and the hearth electrode temperature is 20 ℃.The CF4 flow is 70SCCM, and the HBr flow is 40SCCM, and He and O2 mixed gas flow are 15SCCM (ratio of He is 70% in the wherein said mist, and the O2 ratio is 30%).Etching is until the substrate silicon 100 that exposes outer peripheral areas IIA.
As shown in figure 10, be mask with the second photoresist figure, etching is carried out on the barrier layer 120 of pixel region IA and the substrate silicon 100 of outer peripheral areas IIA, until forming first groove 101 at pixel region IA and forming second groove 102 at outer peripheral areas IIA.Remove the second photoresist figure.Concrete technology comprises that concrete technology comprises that adopt known anisotropic plasma etching technics, selective oxidation thing etching rate and nitride etch rate ratio are 2: 1～4: 1 etching processing procedure.Selection process can be chosen reactive ion etching equipment, and the etching apparatus chamber pressure is 15 millitorrs, and the top radio-frequency power is 700 watts, and the bottom radio-frequency power is 130 watts, and upper electrode temperature is 70 ℃, and the hearth electrode temperature is 20 ℃.Cl
2Flow is 30SCCM, and the HBr flow is 70SCCM, CF
4Flow is 15SCCM, He and O
2Mixed gas flow is that (ratio of He is 70% to 3SCCM in the wherein said mist, O
2Ratio is 30%).Etching is until forming first groove 101 at pixel region IA and forming second groove 102 at outer peripheral areas IIA.
As shown in figure 11, remove the second photoresist figure.Remove photoresist process and can remove technology, comprise that photoresist is removed solution removal, plasma bombardment is removed or the like for known photoresist.
In the lump with reference to Fig. 4 to Figure 11, in the present invention, by on described oxide layer 130, forming the first photoresist figure 140; With the first photoresist figure 140 is mask, and oxide layer 130 is carried out ion injection and annealing, forms ion implanted layer 131 in the dielectric layer of described outer peripheral areas IIA; Remove the first photoresist figure 140; On described oxide layer 130 and ion implanted layer 131, form the second photoresist figure 150; With the second photoresist figure 150 is mask, and etching forms first groove 101 and second groove 102.The degree of depth of described first groove 101 is less than the degree of depth of second groove 102.Formed the less groove of depth ratio at pixel region specifically, form the bigger groove of depth ratio at peripheral circuit region, like this, satisfied the area that improves the pixel active area, and formed depth ratio less groove at pixel region and make the trench aspect ratios of pixel region in the acceptable scope; Can satisfy the requirement of normal outer peripheral areas IIA circuit working and form the bigger groove of depth ratio at peripheral circuit region.Improve the cmos image sensor fill factor, curve factor, improved cmos image sensor picture quality effectively.
Though the present invention discloses as above with preferred embodiment, the present invention is defined in this.Any those skilled in the art without departing from the spirit and scope of the present invention, all can do various changes and modification, so protection scope of the present invention should be as the criterion with claim institute restricted portion.
Claims (7)
1. a double-depth groove formation method is characterized in that, comprising:
Semiconductor substrate is provided, and described Semiconductor substrate comprises silicon substrate, oxygen buried layer, barrier layer, oxide layer successively; Described Semiconductor substrate comprises pixel region and outer peripheral areas;
On described oxide layer, form the photoresist figure;
With the photoresist figure is mask, and oxide layer is carried out ion injection and annealing, forms ion implanted layer in the oxide layer of described outer peripheral areas;
Etching oxidation layer, barrier layer, oxygen buried layer and silicon substrate form first groove and second groove; The degree of depth of described first groove is less than the degree of depth of second groove.
2. double-depth groove formation method as claimed in claim 1 is characterized in that, described barrier layer is a nitride structure.
3. double-depth groove formation method as claimed in claim 1 is characterized in that, the photoresist of described photoresist figure is a negative photoresist.
4. double-depth groove formation method as claimed in claim 1 is characterized in that, described ion is injected to by at least one ion implantation step and constitutes.
5. double-depth groove formation method as claimed in claim 4 is characterized in that, described ion is injected to the N ion and injects.
6. double-depth groove formation method as claimed in claim 1 is characterized in that, described lithographic method is a plasma etching.
7. double-depth groove formation method as claimed in claim 1 is characterized in that, described lithographic method is the lithographic method of oxide etching rate greater than nitride etch rate ratio.
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102437030A (en) * | 2011-08-04 | 2012-05-02 | 上海华力微电子有限公司 | Method for forming dual-depth isolation channels through P type ion injection |
| CN103137458A (en) * | 2011-12-05 | 2013-06-05 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of high dielectric layer metal gate |
| CN106328515A (en) * | 2015-06-30 | 2017-01-11 | 北大方正集团有限公司 | Current regulative diode and manufacturing method thereof |
| CN107293491A (en) * | 2016-04-12 | 2017-10-24 | 北大方正集团有限公司 | The preparation method of VDMOS device |
| CN107464781A (en) * | 2016-06-03 | 2017-12-12 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and preparation method thereof, electronic installation |
| CN108470743A (en) * | 2018-04-02 | 2018-08-31 | 德淮半导体有限公司 | The forming method of imaging sensor |
| CN109962035A (en) * | 2019-04-09 | 2019-07-02 | 德淮半导体有限公司 | The forming method of semiconductor structure and imaging sensor |
| CN112420722A (en) * | 2019-08-22 | 2021-02-26 | 长鑫存储技术有限公司 | Embedded grid structure and method for forming semiconductor memory |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101207064B (en) * | 2006-12-22 | 2010-08-11 | 中芯国际集成电路制造(上海)有限公司 | Method for forming device isolation region |
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2009
- 2009-03-02 CN CN 200910046894 patent/CN101826485B/en not_active Expired - Fee Related
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102437030A (en) * | 2011-08-04 | 2012-05-02 | 上海华力微电子有限公司 | Method for forming dual-depth isolation channels through P type ion injection |
| CN102437030B (en) * | 2011-08-04 | 2013-09-11 | 上海华力微电子有限公司 | Method for forming dual-depth isolation channels through P type ion injection |
| CN103137458A (en) * | 2011-12-05 | 2013-06-05 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of high dielectric layer metal gate |
| CN103137458B (en) * | 2011-12-05 | 2016-03-30 | 中芯国际集成电路制造(上海)有限公司 | The manufacture method of high dielectric layer metal gate |
| CN106328515A (en) * | 2015-06-30 | 2017-01-11 | 北大方正集团有限公司 | Current regulative diode and manufacturing method thereof |
| CN107293491A (en) * | 2016-04-12 | 2017-10-24 | 北大方正集团有限公司 | The preparation method of VDMOS device |
| CN107464781A (en) * | 2016-06-03 | 2017-12-12 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and preparation method thereof, electronic installation |
| CN107464781B (en) * | 2016-06-03 | 2020-09-11 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device, manufacturing method thereof and electronic device |
| CN108470743A (en) * | 2018-04-02 | 2018-08-31 | 德淮半导体有限公司 | The forming method of imaging sensor |
| CN109962035A (en) * | 2019-04-09 | 2019-07-02 | 德淮半导体有限公司 | The forming method of semiconductor structure and imaging sensor |
| CN112420722A (en) * | 2019-08-22 | 2021-02-26 | 长鑫存储技术有限公司 | Embedded grid structure and method for forming semiconductor memory |
| CN112420722B (en) * | 2019-08-22 | 2022-06-10 | 长鑫存储技术有限公司 | Embedded grid structure and method for forming semiconductor memory |
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