CN108470534B - Pixel unit circuit applied to self-luminescence, test circuit and test method - Google Patents
Pixel unit circuit applied to self-luminescence, test circuit and test method Download PDFInfo
- Publication number
- CN108470534B CN108470534B CN201810517858.3A CN201810517858A CN108470534B CN 108470534 B CN108470534 B CN 108470534B CN 201810517858 A CN201810517858 A CN 201810517858A CN 108470534 B CN108470534 B CN 108470534B
- Authority
- CN
- China
- Prior art keywords
- transistor
- circuit
- output
- test
- gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B20/00—Energy efficient lighting technologies, e.g. halogen lamps or gas discharge lamps
- Y02B20/30—Semiconductor lamps, e.g. solid state lamps [SSL] light emitting diodes [LED] or organic LED [OLED]
Abstract
The invention discloses a pixel unit circuit applied to self-luminescence, which is characterized by comprising: the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the sample-and-hold capacitor C1, the data signal line IDATA, the switch control signal line smp_hld, the power supply line VDD, the common cathode power supply line VCOM of the light emitting device, and the light emitting device. The test scheme of the output current of the pixel array unit circuit can evaluate the difference of the output currents of all the pixel unit circuits, and further evaluate the consistency of the current output of the whole pixel array.
Description
Technical Field
The invention relates to a pixel unit array current testing circuit of self-luminous display, in particular to a pixel unit array current testing circuit of OLED/LED micro-display.
Background
With the development of AR (Augmented Reality )/VR (Virtual Reality) technology, there has been a great deal of attention in recent years to micro display technology which is a branch of the display technology field, and generally displays with a diagonal size of less than 1 inch (2.54 cm) or displays which are as small as required for optical magnification are called micro displays.
Unlike conventional technology using amorphous silicon, microcrystalline silicon or low-temperature polysilicon, the oled and led os microdisplay uses monocrystalline silicon chips as substrates, that is, it can use the existing mature integrated circuit CMOS (Complementary Metal-Oxide-Semiconductor) technology, so that it can realize not only the active addressing matrix of the display screen pixels but also the driving control circuits of various functions such as scan chain circuits, digital-analog conversion circuits, band gap references, etc., thereby greatly reducing the external connection of the devices, increasing the reliability, and realizing light weight.
The pixel cell circuit is the most basic unit in the micro display driving circuit, and the consistency of the output current of the pixel cell circuit can greatly influence the final display effect. Therefore, the uniformity analysis of the pixel cell array circuit output current has great value for analyzing and evaluating the overall driving scheme.
Disclosure of Invention
The invention provides a testing scheme which can be suitable for the output current of a pixel unit array circuit, and the analysis of the current consistency of the pixel unit array can be easily completed through the scheme.
The technical scheme is as follows:
the invention discloses a pixel unit circuit applied to self-luminescence, which comprises: a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a sample-and-hold capacitor C1, a data signal line IDATA, a switch control signal line SMP_HLD, a power line VDD, a common cathode power line VCOM of the light emitting device,
the power line VDD is connected with the source electrode of the first transistor M1 on the one hand and the upper polar plate of the sample-hold capacitor C1 on the other hand; the lower polar plate of the sampling hold capacitor C1 is respectively connected with the grid electrode of the first transistor M1, the source electrode of the second transistor M2 and the drain electrode of the third transistor M3;
the switch control signal line smp_hld is connected to the gate of the second transistor M2, the gate of the third transistor M3, and the gate of the fourth transistor M4, respectively;
the data signal line IDATA is connected with the drain electrode of the second transistor M2;
the drain electrode of the fourth transistor M4 is respectively connected with the drain electrode of the first transistor M1 and the source electrode of the third transistor M3;
the source electrode of the fourth transistor M4 is connected to the common cathode power line VCOM of the light emitting device through the light emitting device.
Preferably, the light emitting device is an OLED or an LED.
Preferably, the first transistor M1, the second transistor M2 and the third transistor M3 are PMOS transistors, and the fourth transistor M4 is an NMOS transistor.
The invention also discloses a test circuit suitable for consistency of output current of the pixel unit array circuit, the pixel unit array circuit is composed of a plurality of pixel unit circuits applied to self-luminescence, and the test circuit comprises:
pixel cell copy circuit P': for a single pixel unit circuit P, the pixel unit replication circuit P ' comprises a first replication transistor M1' and a fourth replication transistor M4', and the layout and the size of the first replication transistor M1' and the fourth replication transistor M4' are consistent with those of the first transistor M1 and the fourth transistor M4 in the pixel unit circuit; the grid electrode of the fourth replica transistor M4' is connected with a power line VDD; the grid electrode of the first replica transistor M1' and the grid electrode of the first transistor M1 are connected together to form a structure of a current mirror;
test selection control circuit: the test selection control circuit comprises a scan chain circuit, a plurality of test mode control circuits, a test mode selection control port S, a clock control port CP of a row scan chain and an input control port D of the row scan chain, wherein the test mode control circuits are in one-to-one correspondence with the pixel unit circuits,
the input end of each test mode control circuit is connected with a scan chain circuit, the output end of each test mode control circuit is respectively connected with the grid electrode of the second transistor M2, the grid electrode of the third transistor M3 and the grid electrode of the fourth transistor M4 of the corresponding pixel unit circuit, each test mode control circuit is connected with a test mode selection control port S, the scan chain circuit is respectively connected with a clock control port CP of a row scan chain and an input control port D of the row scan chain, and the scanning sequence of the row scan chain is from top to bottom.
Preferably, the test mode control circuit includes a first inverter INV1 AND a second inverter INV2, an AND gate AND, an OR gate OR AND a transmission gate; the transmission gate comprises NMOS and PMOS tubes: the source end and the source end of the NMOS tube and the source end of the PMOS tube are connected, and the drain end are connected; the input IN is respectively connected to one input end of the AND gate AND input end of the first inverter INV1, AND the input S end is respectively connected to the other input end of the AND gate AND input end of the second inverter INV 2; the output end of the AND gate AND is connected to the gate end of the NMOS tube in the transmission gate; the output end of the first inverter INV1 is respectively connected to the input end of the transmission gate and one input end of the OR gate OR; the second inverter INV2 is connected to the other input end of the OR gate, and the output end of the OR gate is connected to the gate end of the PMOS tube in the transmission gate; the output of the transmission gate is connected to the OUT output port.
The invention also discloses a testing method suitable for the consistency of the output current of the pixel unit array circuit, and based on the testing circuit, the testing selection control circuit has two working modes:
when the test mode selection control port S=0, the pixel array is in a normal working mode, all the test mode control circuits output high resistance, and the switch control signal line SMP_HLD of the pixel unit circuit is not influenced by the output of the test mode control circuits; the switch control signal line SMP_HLD of each row is controlled by the output of the original row scanning chain circuit, and the whole pixel array is in a normal working state;
when the test mode selection control port s=1, a current test mode is output for the pixel unit circuit, and the specific workflow is as follows:
(1) In the first period of the clock CP, the input control port D of the line scanning chain is high level, the first output of the scanning chain circuit is 1, and the other outputs are 0; at this time, the input IN of the first test mode control circuit is 1, so the smp_hld signal of the pixel cell circuit of the first row is 0, which is IN the data sampling stage; at this time, the input IDATA of the pixel unit circuits of the first row is copied as ITEST and output to the test circuit board;
(2) In the kth period of the clock CP, the input control port D of the line scanning chain is 0 level, the kth output of the scanning chain circuit is 1, and the rest outputs are 0; at this time, the input IN of the kth test mode control circuit is 1, so the smp_hld signal of the pixel unit circuit of the kth row is 0, which is IN the data sampling stage; at this time, the input IDATA of the pixel unit circuit of the kth row is copied as ITEST and output to the test circuit board;
(3) In the nth period of the clock CP, n is the total number of rows of the pixel array, the input control port D of the line scanning chain is 0 level, the nth output of the scanning chain circuit is 1, and the rest outputs are 0; at this time, the input IN of the nth test mode control circuit is 1, so the smp_hld signal of the pixel unit circuit of the nth row is 0, which is IN the data sampling stage; at this time, the input IDATA of the pixel cell circuit of the nth row is copied as ITEST and output to the test circuit board.
The beneficial effects of the invention are that
The test scheme of the output current of the pixel array unit circuit can evaluate the difference of the output currents of all the pixel unit circuits, and further evaluate the consistency of the current output of the whole pixel array.
Drawings
FIG. 1 shows a current-mode pixel cell circuit according to the present invention
FIG. 2 is a schematic diagram of a pixel cell copy circuit P' constructed in accordance with an embodiment
FIG. 3 is a circuit configuration diagram of a circuit current test for two pixel units in an embodiment
FIG. 4 shows a test mode control circuit according to the present invention
FIG. 5 is a timing diagram illustrating the operation of the test scheme of the present invention
Detailed Description
The invention is further illustrated below with reference to examples, but the scope of the invention is not limited thereto:
example 1: referring to fig. 1, a pixel unit circuit applied to self-luminescence includes: the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the sample-and-hold capacitor C1, the data signal line IDATA, the switch control signal line smp_hld, the power supply line VDD, the common cathode power supply line VCOM of the light emitting device, and the light emitting device.
The power line VDD is connected with the source electrode of the first transistor M1 on the one hand and the upper polar plate of the sample-hold capacitor C1 on the other hand; the lower polar plate of the sampling hold capacitor C1 is respectively connected with the grid electrode of the first transistor M1, the source electrode of the second transistor M2 and the drain electrode of the third transistor M3;
the switch control signal line smp_hld is connected to the gate of the second transistor M2, the gate of the third transistor M3, and the gate of the fourth transistor M4, respectively;
the data signal line IDATA is connected with the drain electrode of the second transistor M2;
the drain electrode of the fourth transistor M4 is respectively connected with the drain electrode of the first transistor M1 and the source electrode of the third transistor M3;
the source electrode of the fourth transistor M4 is connected to the common cathode power line VCOM of the light emitting device through the light emitting device.
Wherein: the light emitting device is an OLED or an LED. The first transistor M1, the second transistor M2 and the third transistor M3 are PMOS transistors, and the fourth transistor M4 is an NMOS transistor.
The conventional current test scheme cannot meet the test requirements of the circuit structure described in embodiment 1, for the following reasons: for the current-type pixel cell circuit shown in fig. 1, it is divided into two operation phases: a data sampling phase and a holding phase.
In the sampling phase, the SAM_HLD signal is 0, so M2 and M3 are turned on, and M4 is turned off; since the input IDATA is a current signal, if an additional extraction port in the pixel unit circuit has a shunt effect on the input current IDATA, the actual output current of the pixel unit cannot be accurately tested.
In the hold phase, the sam_hld signal is 1, so M2, M3 are off, M4 is on; at this time, the current of M1 is completely maintained by the voltage held on the capacitor C1, and the holding time of the capacitor C1 often cannot meet the test requirement because the output current is required to have a longer settling time for the actual test.
Example 2: the invention discloses a test circuit suitable for consistency of output current of a pixel unit array circuit, wherein the pixel unit array circuit consists of a plurality of pixel unit circuits applied to self-luminescence, and the test circuit comprises:
pixel cell copy circuit P': referring to fig. 2, for a single pixel unit circuit P, the pixel unit replica circuit P ' includes a first replica transistor M1' and a fourth replica transistor M4', and the layout and the size of the first replica transistor M1' and the fourth replica transistor M4' are consistent with those of the first transistor M1 and the fourth transistor M4 in the pixel unit circuit; the grid electrode of the fourth replica transistor M4' is connected with a power line VDD; the grid electrode of the first replica transistor M1' and the grid electrode of the first transistor M1 are connected together to form a structure of a current mirror;
test selection control circuit: referring to fig. 3, the test selection control circuit includes a scan chain circuit, a plurality of test mode control circuits, a test mode selection control port S, a clock control port CP of a row scan chain, and an input control port D of a row scan chain, the test mode control circuits are in one-to-one correspondence with the pixel unit circuits,
the input end of each test mode control circuit is connected with a scan chain circuit, the output end of each test mode control circuit is respectively connected with the grid electrode of the second transistor M2, the grid electrode of the third transistor M3 and the grid electrode of the fourth transistor M4 of the corresponding pixel unit circuit, each test mode control circuit is connected with a test mode selection control port S, the scan chain circuit is respectively connected with a clock control port CP of a row scan chain and an input control port D of the row scan chain, and the scanning sequence of the row scan chain is from top to bottom;
referring to fig. 4, the test mode control circuit includes a first inverter INV1 AND a second inverter INV2, an AND gate AND, an OR gate OR, AND a transmission gate; the transmission gate comprises NMOS and PMOS tubes: the source end and the source end of the NMOS tube and the source end of the PMOS tube are connected, and the drain end are connected; the input IN is respectively connected to one input end of the AND gate AND input end of the first inverter INV1, AND the input S end is respectively connected to the other input end of the AND gate AND input end of the second inverter INV 2; the output end of the AND gate AND is connected to the gate end of the NMOS tube in the transmission gate; the output end of the first inverter INV1 is respectively connected to the input end of the transmission gate and one input end of the OR gate OR; the second inverter INV2 is connected to the other input end of the OR gate, and the output end of the OR gate is connected to the gate end of the PMOS tube in the transmission gate; the output of the transmission gate is connected to the OUT output port.
The operation timing diagram of the test selection control circuit is shown in fig. 5, and the test selection control circuit has two operation modes:
when the test mode selection control port S=0, the pixel array is in a normal working mode, all the test mode control circuits output high resistance, and the switch control signal line SMP_HLD of the pixel unit circuit is not influenced by the output of the test mode control circuits; the switch control signal line SMP_HLD of each row is controlled by the output of the original row scanning chain circuit, and the whole pixel array is in a normal working state;
when the test mode selection control port s=1, a current test mode is output for the pixel unit circuit, and the specific workflow is as follows:
(1) In the first period of the clock CP, the input control port D of the line scanning chain is high level, the first output of the scanning chain circuit is 1, and the other outputs are 0; at this time, the input IN of the first test mode control circuit is 1, so the smp_hld signal of the pixel cell circuit of the first row is 0, which is IN the data sampling stage; at this time, the input IDATA of the pixel unit circuits of the first row is copied as ITEST and output to the test circuit board;
(2) In the kth period of the clock CP, the input control port D of the line scanning chain is 0 level, the kth output of the scanning chain circuit is 1, and the rest outputs are 0; at this time, the input IN of the kth test mode control circuit is 1, so the smp_hld signal of the pixel unit circuit of the kth row is 0, which is IN the data sampling stage; at this time, the input IDATA of the pixel unit circuit of the kth row is copied as ITEST and output to the test circuit board;
(3) In the nth period of the clock CP, n is the total number of rows of the pixel array, the input control port D of the line scanning chain is 0 level, the nth output of the scanning chain circuit is 1, and the rest outputs are 0; at this time, the input IN of the nth test mode control circuit is 1, so the smp_hld signal of the pixel unit circuit of the nth row is 0, which is IN the data sampling stage; at this time, the input IDATA of the pixel cell circuit of the nth row is copied as ITEST and output to the test circuit board.
The test scheme of the output current of the pixel array unit circuit can evaluate the difference of the output currents of all the pixel unit circuits, and further evaluate the consistency of the current output of the whole pixel array.
The driving method can be applied to the test of OLED and LED current type pixel unit circuits, and is also suitable for the test of the output current of any voltage type pixel unit circuit.
The specific embodiments described herein are offered by way of example only to illustrate the spirit of the invention. Those skilled in the art may make various modifications or additions to the described embodiments or substitutions thereof without departing from the spirit of the invention or exceeding the scope of the invention as defined in the accompanying claims.
Claims (6)
1. A pixel cell circuit for self-luminescence, characterized in that it comprises: a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a sample-and-hold capacitor C1, a data signal line IDATA, a switch control signal line SMP_HLD, a power line VDD, a common cathode power line VCOM of the light emitting device,
the power line VDD is connected with the source electrode of the first transistor M1 on the one hand and the upper polar plate of the sample-hold capacitor C1 on the other hand; the lower polar plate of the sampling hold capacitor C1 is respectively connected with the grid electrode of the first transistor M1, the source electrode of the second transistor M2 and the drain electrode of the third transistor M3;
the switch control signal line smp_hld is connected to the gate of the second transistor M2, the gate of the third transistor M3, and the gate of the fourth transistor M4, respectively;
the data signal line IDATA is connected with the drain electrode of the second transistor M2;
the drain electrode of the fourth transistor M4 is respectively connected with the drain electrode of the first transistor M1 and the source electrode of the third transistor M3;
the source electrode of the fourth transistor M4 is connected to the common cathode power line VCOM of the light emitting device through the light emitting device.
2. The circuit of claim 1, wherein the light emitting device is an OLED or LED.
3. The circuit of claim 1, wherein the first transistor M1, the second transistor M2 and the third transistor M3 are PMOS transistors, and the fourth transistor M4 is an NMOS transistor.
4. A test circuit adapted for output current uniformity of a pixel cell array circuit, said pixel cell array circuit being comprised of a plurality of pixel cell circuits as recited in claim 1, said test circuit comprising:
pixel cell copy circuit P': for a single pixel unit circuit P, the pixel unit replication circuit P ' comprises a first replication transistor M1' and a fourth replication transistor M4', and the layout and the size of the first replication transistor M1' and the fourth replication transistor M4' are consistent with those of the first transistor M1 and the fourth transistor M4 in the pixel unit circuit; the grid electrode of the fourth replica transistor M4' is connected with a power line VDD; the grid electrode of the first replica transistor M1' and the grid electrode of the first transistor M1 are connected together to form a structure of a current mirror;
test selection control circuit: the test selection control circuit comprises a scan chain circuit, a plurality of test mode control circuits, a test mode selection control port S, a clock control port CP of a row scan chain and an input control port D of the row scan chain, wherein the test mode control circuits are in one-to-one correspondence with the pixel unit circuits,
the input end of each test mode control circuit is connected with a scan chain circuit, the output end of each test mode control circuit is respectively connected with the grid electrode of the second transistor M2, the grid electrode of the third transistor M3 and the grid electrode of the fourth transistor M4 of the corresponding pixel unit circuit, each test mode control circuit is connected with a test mode selection control port S, the scan chain circuit is respectively connected with a clock control port CP of a row scan chain and an input control port D of the row scan chain, and the scanning sequence of the row scan chain is from top to bottom.
5. The test circuit according to claim 4, wherein the test mode control circuit comprises a first inverter INV1 AND a second inverter INV2, an AND gate AND, an OR gate OR AND a transmission gate; the transmission gate comprises NMOS and PMOS tubes: the source end and the source end of the NMOS tube and the source end of the PMOS tube are connected, and the drain end are connected; the input IN is respectively connected to one input end of the AND gate AND input end of the first inverter INV1, AND the input S end is respectively connected to the other input end of the AND gate AND input end of the second inverter INV 2; the output end of the AND gate AND is connected to the gate end of the NMOS tube in the transmission gate; the output end of the first inverter INV1 is respectively connected to the input end of the transmission gate and one input end of the OR gate OR; the second inverter INV2 is connected to the other input end of the OR gate, and the output end of the OR gate is connected to the gate end of the PMOS tube in the transmission gate; the output of the transmission gate is connected to the OUT output port.
6. A test method suitable for consistency of output current of a pixel unit array circuit, based on the test circuit of claim 4, characterized in that the test selection control circuit has two operation modes:
when the test mode selection control port S=0, the pixel array is in a normal working mode, all the test mode control circuits output high resistance, and the switch control signal line SMP_HLD of the pixel unit circuit is not influenced by the output of the test mode control circuits; the switch control signal line SMP_HLD of each row is controlled by the output of the original row scanning chain circuit, and the whole pixel array is in a normal working state;
when the test mode selection control port s=1, a current test mode is output for the pixel unit circuit, and the specific workflow is as follows:
(1) In the first period of the clock CP, the input control port D of the line scanning chain is high level, the first output of the scanning chain circuit is 1, and the other outputs are 0; at this time, the input IN of the first test mode control circuit is 1, so the smp_hld signal of the pixel cell circuit of the first row is 0, which is IN the data sampling stage; at this time, the input IDATA of the pixel unit circuits of the first row is copied as ITEST and output to the test circuit board;
(2) In the kth period of the clock CP, the input control port D of the line scanning chain is 0 level, the kth output of the scanning chain circuit is 1, and the rest outputs are 0; at this time, the input IN of the kth test mode control circuit is 1, so the smp_hld signal of the pixel unit circuit of the kth row is 0, which is IN the data sampling stage; at this time, the input IDATA of the pixel unit circuit of the kth row is copied as ITEST and output to the test circuit board;
(3) In the nth period of the clock CP, n is the total number of rows of the pixel array, the input control port D of the line scanning chain is 0 level, the nth output of the scanning chain circuit is 1, and the rest outputs are 0; at this time, the input IN of the nth test mode control circuit is 1, so the smp_hld signal of the pixel unit circuit of the nth row is 0, which is IN the data sampling stage; at this time, the input IDATA of the pixel cell circuit of the nth row is copied as ITEST and output to the test circuit board.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810517858.3A CN108470534B (en) | 2018-05-25 | 2018-05-25 | Pixel unit circuit applied to self-luminescence, test circuit and test method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810517858.3A CN108470534B (en) | 2018-05-25 | 2018-05-25 | Pixel unit circuit applied to self-luminescence, test circuit and test method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN108470534A CN108470534A (en) | 2018-08-31 |
| CN108470534B true CN108470534B (en) | 2023-08-04 |
Family
ID=63261573
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810517858.3A Active CN108470534B (en) | 2018-05-25 | 2018-05-25 | Pixel unit circuit applied to self-luminescence, test circuit and test method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN108470534B (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11257419B2 (en) * | 2018-09-14 | 2022-02-22 | Novatek Microelectronics Corp. | Current driving digital pixel apparatus for micro light emitting device array |
| CN113767466A (en) * | 2019-04-25 | 2021-12-07 | 株式会社索思未来 | Semiconductor device with a plurality of semiconductor chips |
| CN110570820B (en) * | 2019-08-06 | 2020-10-16 | 深圳市华星光电技术有限公司 | AMOLED display device and driving method thereof |
| CN111025697B (en) * | 2019-12-16 | 2021-06-01 | 武汉华星光电技术有限公司 | Liquid crystal display panel and display device |
| TWI802215B (en) | 2022-01-11 | 2023-05-11 | 友達光電股份有限公司 | Driving circuit |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1684132A (en) * | 2003-10-29 | 2005-10-19 | 三星Sdi株式会社 | Light-emitting display, driving method thereof, and light-emitting display panel |
| CN102044213A (en) * | 2009-10-21 | 2011-05-04 | 京东方科技集团股份有限公司 | Current-driven pixel circuit, drive method thereof and organic light emitting display device |
| CN104240639A (en) * | 2014-08-22 | 2014-12-24 | 京东方科技集团股份有限公司 | Pixel circuit, organic electroluminescence display panel and display device |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR102047005B1 (en) * | 2013-05-31 | 2019-11-21 | 삼성디스플레이 주식회사 | Organic Light Emitting Display Panel |
-
2018
- 2018-05-25 CN CN201810517858.3A patent/CN108470534B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1684132A (en) * | 2003-10-29 | 2005-10-19 | 三星Sdi株式会社 | Light-emitting display, driving method thereof, and light-emitting display panel |
| CN102044213A (en) * | 2009-10-21 | 2011-05-04 | 京东方科技集团股份有限公司 | Current-driven pixel circuit, drive method thereof and organic light emitting display device |
| CN104240639A (en) * | 2014-08-22 | 2014-12-24 | 京东方科技集团股份有限公司 | Pixel circuit, organic electroluminescence display panel and display device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN108470534A (en) | 2018-08-31 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN108470534B (en) | Pixel unit circuit applied to self-luminescence, test circuit and test method | |
| CN110176213B (en) | Pixel circuit, driving method thereof and display panel | |
| CN109509433B (en) | Pixel circuit, display device and pixel driving method | |
| US11380261B2 (en) | Pixel circuit, pixel driving method and display device | |
| US11127359B2 (en) | Display panel, method for driving the same and display device | |
| CN105243996A (en) | AMOLED driving circuit structure adopting external compensation | |
| JP5174938B2 (en) | Signal drive circuit | |
| CN110728946A (en) | Pixel circuit, driving method thereof and display panel | |
| CN108538249A (en) | Pixel-driving circuit and method, display device | |
| CN111754941B (en) | Pixel circuit, driving method thereof, display substrate and display device | |
| US10580380B2 (en) | Level conversion circuit, display apparatus, and driving method | |
| CN108550344B (en) | Current-type pixel unit circuit applied to self-luminescence, driving current generation method and image or video display method | |
| US20020186183A1 (en) | Image display panel and image viewer with an image display panel | |
| US11037508B1 (en) | Pixel driving circuit, display panel and methods for driving the same | |
| TW202334936A (en) | Method for driving display panel and display driver circuit using the same | |
| KR102598198B1 (en) | Light Emitting Display Device | |
| CN208208302U (en) | Applied to self luminous current mode pixel unit circuit | |
| CN207966467U (en) | Pixel circuit and display panel | |
| CN110379372B (en) | Pixel driving unit, circuit, method, display panel and display device | |
| CN212461111U (en) | Current mode pixel unit circuit, combination and array for fast data writing | |
| KR20220078234A (en) | Pixel sensing circuit and pixel sensing method | |
| CN208208304U (en) | Self-luminous current mode pixel unit circuit suitable for common-anode | |
| CN108091301B (en) | Voltage sampling circuit and method and display device | |
| CN113035117A (en) | Array substrate, driving method thereof and display device | |
| CN208208294U (en) | Applied to self luminous pixel unit circuit, test circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |