CN108461534A - 化合物半导体基板以及功率放大模块 - Google Patents

化合物半导体基板以及功率放大模块 Download PDF

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CN108461534A
CN108461534A CN201810140616.7A CN201810140616A CN108461534A CN 108461534 A CN108461534 A CN 108461534A CN 201810140616 A CN201810140616 A CN 201810140616A CN 108461534 A CN108461534 A CN 108461534A
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compound semiconductor
mentioned
semiconductor substrate
interarea
recess portion
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CN108461534B (zh
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大部功
梅本康成
柴田雅博
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Murata Manufacturing Co Ltd
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Murata Manufacturing Co Ltd
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    • H01L2224/29138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
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    • H01L2224/29199—Material of the matrix
    • H01L2224/29294—Material of the matrix with a principal constituent of the material being a liquid not provided for in groups H01L2224/292 - H01L2224/29291
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    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29338—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
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    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L29/107—Substrate region of field-effect devices
    • H01L29/1075—Substrate region of field-effect devices of field-effect transistors
    • H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
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    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/10155—Shape being other than a cuboid
    • H01L2924/10158—Shape being other than a cuboid at the passive surface
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/141—Analog devices
    • H01L2924/1424—Operational amplifier
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3512—Cracking
    • H01L2924/35121—Peeling or delaminating

Abstract

本发明提供耐剥离性提高的化合物半导体基板。化合物半导体基板具有与第一方向以及和第一方向正交的第二方向平行的第一主面、与第一主面对置的第二主面、以及从第一主面朝向第二主面形成的凹部，凹部具有形成在第一主面的开口部、与开口部对置的底面、以及在开口部与底面之间形成凹部的多个侧面，多个侧面包含沿着第一方向延伸且在凹部的内部与底面所成的角大致为θ(0＜θ＜90)度的至少一个第一侧面、和沿着第二方向延伸且在凹部的内部与底面所成的角大致为φ(90＜φ＜180)度的至少一个第二侧面，第一主面与至少一个第一侧面的接线的总长度比第一主面与至少一个第二侧面的接线的总长度长。

Description

化合物半导体基板以及功率放大模块
技术领域
本发明涉及化合物半导体基板以及功率放大模块。
背景技术
在搭载于移动电话等移动体通信机的功率放大模块中，一般使用化合物半导体器件。在化合物半导体器件中，例如要求高温、高湿环境下的吸湿后的高温回流(reflow)时的特性变动的抑制等，对可靠性的要求较严格。在这样的高温、高湿环境下，存在化合物半导体芯片从模块基板剥离这样的问题。对于该问题，例如专利文献1公开了在硅半导体芯片的背面形成凹部，并在该凹部填充粘合剂从而与收纳容器的工作台(stage)粘合的构成。在该构成中，由于凹部的形状是与开口部相比内部更宽广的壶形，所以与基板的接合强度提高。
专利文献1：日本实开昭61－4430号公报
但是，专利文献1所公开的构成涉及硅半导体芯片，对于考虑了化合物半导体的性质的构成并未进行研究。
发明内容
本发明是鉴于这样的情况而完成的，其目的在于，提供耐剥离性提高的化合物半导体基板。
为了实现这样的目的，本发明的一个方面所涉及的化合物半导体基板具有与第一方向以及和第一方向正交的第二方向平行的第一主面、与第一主面对置的第二主面、以及从第一主面朝向第二主面形成的凹部，凹部具有形成在第一主面的开口部、与开口部对置的底面、以及在开口部与底面之间形成凹部的多个侧面，多个侧面包含：沿着第一方向延伸的至少一个第一侧面，该第一侧面在凹部的内部与底面所成的角大致为θ(0＜θ＜90)度；和沿着第二方向延伸的至少一个第二侧面，该第二侧面在凹部的内部与底面所成的角大致为φ(90＜φ＜180)度，第一主面与至少一个第一侧面的接线的总长度比第一主面与至少一个第二侧面的接线的总长度长。
根据本发明，能够提供耐剥离性提高的化合物半导体基板。
附图说明
图1是本发明的第一实施方式所涉及的化合物半导体芯片的俯视图。
图2是图1的A－A线剖视图。
图3是图1的B－B线剖视图。
图4A是用于说明凹部3的制造过程的图。
图4B是用于说明凹部3的制造过程的图。
图4C是用于说明凹部3的制造过程的图。
图4D是用于说明凹部3的制造过程的图。
图4E是用于说明凹部3的制造过程的图。
图5A是安装了本发明的第一实施方式所涉及的化合物半导体芯片的模块的剖视图。
图5B是安装了本发明的第一实施方式所涉及的化合物半导体芯片的模块的剖视图。
图6A是安装了形成有凹部(比较例A)的化合物半导体芯片的模块的剖视图。
图6B是安装了形成有凹部(比较例A)的化合物半导体芯片的模块的剖视图。
图7A是安装了形成有凹部(比较例B)的化合物半导体芯片的模块的剖视图。
图7B是安装了形成有凹部(比较例B)的化合物半导体芯片的模块的剖视图。
图8A是安装了本发明的第一实施方式所涉及的化合物半导体芯片的模块的剖视图。
图8B是安装了形成有HBT的化合物半导体芯片的模块的剖视图。
图9是本发明的第一实施方式的变形例所涉及的化合物半导体芯片的俯视图。
图10是本发明的第一实施方式的其它变形例所涉及的化合物半导体芯片的俯视图。
图11是图10的E－E线剖视图。
图12是图10的F－F线剖视图。
图13是图10的G－G线剖视图。
图14是用于说明通孔(via hole)的功能的图。
图15是本发明的第二实施方式所涉及的化合物半导体芯片的俯视图。
图16是本发明的第二实施方式的变形例所涉及的化合物半导体芯片的俯视图。
图17是本发明的第二实施方式的其它变形例所涉及的化合物半导体芯片的俯视图。
图18A是表示本发明的第一实施方式的其它变形例所涉及的化合物半导体芯片的制造方法的顺序的图。
图18B是表示本发明的第一实施方式的其它变形例所涉及的化合物半导体芯片的制造方法的顺序的图。
图18C是表示本发明的第一实施方式的其它变形例所涉及的化合物半导体芯片的制造方法的顺序的图。
图18D是表示本发明的第一实施方式的其它变形例所涉及的化合物半导体芯片的制造方法的顺序的图。
图18E是表示本发明的第一实施方式的其它变形例所涉及的化合物半导体芯片的制造方法的顺序的图。
图18F是表示本发明的第一实施方式的其它变形例所涉及的化合物半导体芯片的制造方法的顺序的图。
图18G是表示本发明的第一实施方式的其它变形例所涉及的化合物半导体芯片的制造方法的顺序的图。
图18H是表示本发明的第一实施方式的其它变形例所涉及的化合物半导体芯片的制造方法的顺序的图。
图18I是表示本发明的第一实施方式的其它变形例所涉及的化合物半导体芯片的制造方法的顺序的图。
图18J是表示本发明的第一实施方式的其它变形例所涉及的化合物半导体芯片的制造方法的顺序的图。
图18K是表示本发明的第一实施方式的其它变形例所涉及的化合物半导体芯片的制造方法的顺序的图。
图18L是表示本发明的第一实施方式的其它变形例所涉及的化合物半导体芯片的制造方法的顺序的图。
图19是安装了本发明的第一实施方式的其它变形例所涉及的化合物半导体芯片的功率放大模块的剖视图。
具体实施方式
以下对本发明的实施方式进行说明。在以下的附图的记载中，相同或者类似的构成要素以相同或者类似的附图标记进行表示。附图是例示，各部的尺寸、形状是示意的尺寸、形状，而不应理解为将本申请发明的技术范围限定于该实施方式。
首先，参照图1～图8B，对本发明的第一实施方式所涉及的化合物半导体芯片进行说明。图1是本发明的第一实施方式所涉及的化合物半导体芯片的俯视图，图2是图1的A－A线剖视图，图3是图1的B－B线剖视图。本实施方式所涉及的化合物半导体芯片100A包含化合物半导体基板1和电路形成区域2。此外，在图1～图3中，一并标注了化合物半导体基板1的晶体取向。在本说明书中为了方便表述，对于晶体取向的负方向的坐标代替上划线而示为“－1”。另外，在晶体取向的表述中，[011]方向与[0－1－1]方向平行但朝向相反，[01－1]方向与[0－11]方向平行但朝向相反。
化合物半导体基板1例如由GaAs构成，根据GaAs的晶体取向，具有与[011]方向(第一方向)平行的长边、与和[011]方向正交的[01－1]方向(第二方向)平行的短边、以及与[100]方向平行的厚度。另外，具有：与面方位(100)平行且具有大致矩形形状的第一主面10、以及与第一主面10对置的第二主面12。以下，以该晶体取向为基准对化合物半导体芯片的各构成进行说明。此外，化合物半导体基板1的第一主面10以及第二主面12的面方位也可以在(100)±4度的范围内。另外，化合物半导体基板1的材料并不限于GaAs，也可以是InP等其它的化合物半导体。
在化合物半导体基板1的第二主面12侧([100]方向)设有电路形成区域2。在电路形成区域2形成异质结双极晶体管(HBT：Heterojunction Bipolar Transistor)、场效应晶体管(FET：Field Effect Transistor)、高电子迁移率晶体管(HEMT：High ElectronMobility Transistor)、激光二极管(Laser Diode)、光电二极管(Photodiode)等有源元件，或者电阻元件、电容元件、电感元件等无源元件，或者布线，层间绝缘膜或钝化膜(passivation)等。通过这些有源元件、无源元件、布线、绝缘膜或者钝化膜等的组合形成电路。
在化合物半导体基板1从第一主面10朝向第二主面12(即，朝向[100]方向)形成有凹部3。凹部3具有形成在化合物半导体基板1的第一主面10的开口部31、与开口部对置的底面32、以及在开口部与底面之间形成凹部3的多个侧面33。另外，多个侧面33具有沿着[011]方向(第一方向)延伸的对置的一组侧面33a(第一侧面)、和沿着[01－1]方向(第二方向)延伸的对置的一组侧面33b(第二侧面)。此外，图1所示的虚线示出化合物半导体基板1的第一主面10与凹部3的侧面33a、33b的接线34(即，开口部31的形状)。
如图1所示，接线34大致为矩形形状，与和[01－1]方向平行的接线的长度(Wva)相比，和[011]方向平行的接线的长度(Wha)更长(参照图1)。例如，在本实施方式中，Wva为200μm，Wha为1000μm。因此，在凹部3中，第一主面10与侧面33a的接线的总长度(2×Wha)比第一主面10与侧面33b的接线的总长度(2×Wva)长。
凹部3的剖面形状在A－A线剖面和B－B线剖面不同。具体而言，在A－A线剖面的剖面形状中，凹部3的内部的底面32与侧面33a所成的角θ是锐角(即，0＜θ＜90)(参照图2)。即，与凹部3的开口部31的[01－1]方向的长度Wva相比，底面32的[01－1]方向的长度Wvb的长度更长。以下，也将构成该凹部的剖面形状的侧面称为“反向台面型”(inverted mesa)。
另一方面，在B－B线剖面的剖面形状中，凹部3的内部的底面32与侧面33b所成的角φ为钝角(即，90＜φ＜180)(参照图3)。即，与凹部3的开口部31的[0－1－1]方向的长度Wha相比，底面32的[0－1－1]方向的长度Whb的长度更短。以下，也将构成该凹部的剖面形状的侧面称为“正向台面型”(normal mesa)。
此外，设定为凹部3的深度(从开口部31到底面32的[100]方向的距离)D为化合物半导体基板1的厚度以下。例如，本实施方式中的化合物半导体基板1的厚度为75μm，凹部3的深度D为20μm。接下来，参照图4A～图4E，对凹部3的反向台面型以及正向台面型的侧面的制造过程进行说明。
图4A～图4E是用于说明凹部3的制造过程的图。此外，图4B示出图4A的C－C线剖视图，图4C示出图4A的D－D线剖视图。另外，为了方便说明，对于凹部使用与图1～图3中的附图标记相同的附图标记。
首先，如图4A～图4C所示，在化合物半导体基板21上形成具有开口部22的光致抗蚀剂23。光致抗蚀剂23的开口部22是具有与[011]方向平行的长边、和与[01－1]方向平行的短边的大致矩形形状。通过将该光致抗蚀剂23作为掩模的湿式蚀刻，在开口部22下形成凹部3。
图4D以及图4E示出实施了湿式蚀刻之后的C－C线剖视图以及D－D线剖视图。通过湿式蚀刻，光致抗蚀剂23的开口部22之下的化合物半导体基板21被蚀刻除去。这里，化合物半导体是由两种以上的原子种类构成的材料，具有晶体取向依赖性。例如，由于根据晶体取向而电化学性质不同，所以蚀刻去除的速度不同。由此，若对化合物半导体基板21实施湿式蚀刻，则该化合物半导体基板21并不沿着光致抗蚀剂23的开口部22垂直地被除去，在构成与晶体取向对应的倾斜的同时被除去。具体而言，在与面方位(0－1－1)平行的剖面，成为凹部的底面32与侧面33a所成的角θ为锐角的反向台面型(参照图4D)。θ的角度例如θ＝54.7±4度。另一方面，在与面方位(0－11)平行的剖面，成为凹部的底面32与侧面33b所成的角φ为钝角的正向台面型(参照图4E)。φ的角度例如φ＝180－θ＝125.3±4度。这里，由于如上述那样光致抗蚀剂23的开口部22具有与[011]方向平行的长边，所以反向台面型的侧面33a形成得比正向台面型的侧面33b长。
这样，若利用化合物半导体的晶体取向依赖性，则能够不经过繁琐的作业工序而形成反向台面型的侧面33a。另外，能够与光致抗蚀剂23的开口部22的形状对应地，将凹部3形成为反向台面型的侧面33a比正向台面型的侧面33b长。
接下来，参照图5A～图7B，对本实施方式所涉及的化合物半导体芯片的粘合力进行说明。图5A以及图5B是安装了本发明的第一实施方式所涉及的化合物半导体芯片的模块的剖视图。图6A以及图6B是安装了形成有凹部(比较例A)的化合物半导体芯片的模块的剖视图。图7A以及图7B是安装了形成有凹部(比较例B)的化合物半导体芯片的模块的剖视图。此外，图5A～图7B所示的剖视图均示出与图1中的化合物半导体芯片100A的A－A线剖视图相同的方向。
在图5A以及图5B所示的模块中，通过粘合剂210在模块基板200的主面上粘合化合物半导体芯片100A。粘合剂210夹在化合物半导体芯片100A与模块基板200之间，并进一步填充到形成于化合物半导体基板1的凹部3的内部。另外，通过固化树脂220覆盖化合物半导体芯片100A。
在图6A以及图6B示出形成在化合物半导体基板的凹部为正向台面型的构成(以下，也称为比较例A。)。另外，在图7A以及图7B示出形成在化合物半导体基板的凹部具有底面和垂直的侧面的构成(以下，也称为比较例B。)。此外，由于图6A～图7B所示的除了凹部之外的模块的构成与图5A以及图5B所示的模块相同，所以使用与图5A以及图5B中的附图标记相同的附图标记来省略详细的说明。
另外，图5A、图6A以及图7A设想了引起化合物半导体芯片的剥离的主要的应力是拉伸应力(即，从化合物半导体基板1的第一主面10侧向第二主面12侧拉动的力)的情况。另一方面，图5B、图6B以及图7B设想了引起化合物半导体芯片的剥离的主要的应力是剪切应力(即，与上述的拉伸应力垂直方向的力)的情况。
首先，在图5A所示的凹部3中，若在化合物半导体芯片100A作用拉伸应力230，则由于凹部3的几何学形状而物理的楔效应(或者固着效果：anchor effect)起作用。由此，在凹部3的侧面33a与粘合剂210的界面产生与拉伸应力230相反方向的反作用力230R。另一方面，在图6A所示的比较例A或者图7A所示的比较例B中，即使在化合物半导体芯片作用拉伸应力230，物理的楔效应(或者固着效果)也不起作用，在凹部的侧面40、41与粘合剂210的界面不产生反作用力。根据以上可知，对于拉伸应力，反向台面型的凹部3与比较例A或者比较例B的构成相比使化合物半导体基板与模块基板的粘合稳固，使耐剥离性提高。
接下来，在图5B所示的凹部3中，若在化合物半导体芯片100A作用剪切应力240，则由于凹部3的几何学形状而物理的楔效应(或者固着效果)起作用。由此，在凹部3的侧面33a与粘合剂210的界面产生与剪切应力240相反方向的反作用力240R。另外，在图6B所示的比较例A或者图7B所示的比较例B中，若也在化合物半导体芯片作用剪切应力240，则与凹部3同样在凹部的侧面40、41与粘合剂210的界面产生反作用力240R。根据以上可知，对于剪切应力，反向台面型的凹部3具有与比较例A或者比较例B的构成相同的粘合力。
根据以上，可以说反向台面型的凹部3对于拉伸应力以及剪切应力双方粘合力稳固，耐剥离性优异。对于这一点，在化合物半导体芯片100A中，如上述那样将凹部3形成为反向台面型的侧面33a比正向台面型的侧面33b长。由此，化合物半导体芯片100A与比较例A或者比较例B相比，化合物半导体基板与模块基板的粘合变得稳固，耐剥离性提高。
接下来，参照图8A以及图8B，对本实施方式所涉及的化合物半导体芯片的散热性进行说明。图8A是安装了本发明的第一实施方式所涉及的化合物半导体芯片的模块的剖视图，图8B是安装了形成有HBT的化合物半导体芯片的模块的剖视图。此外，图8A以及图8B所示的剖视图示出与图1中的化合物半导体芯片100A的A－A线剖视图相同的方向。
在图8A中，除了凹部3的侧面33a(实线)之外，还示出比较例A的侧面40(虚线)以及比较例B的侧面41(虚线)。若凹部3、比较例A以及比较例B的开口部的宽度Wva相等，则凹部的内部的体积(即，填充到凹部内部的粘合剂210的体积)成为凹部3＞比较例B＞比较例A的顺序。
设粘合剂210具有比化合物半导体基板1的导热率高的导热率。例如，在化合物半导体基板为GaAs(导热率：46W/mK左右)的情况下，粘合剂210使用导热率比46W/mK更高的材料。虽然粘合剂210的材质并不特别限定，但例如可以是银膏等。另外，粘合剂210既可以是导电性，或者也可以是绝缘性。
化合物半导体芯片100A的电路形成区域2包括因电路引起的发热区域Rx。从该发热区域Rx朝向模块基板200传导热。因此，若设在发热区域Rx之下([－100]方向)的材质的导热率较高，则热容易导向模块基板200侧，从而因电路引起的热的散热性提高。换言之，可以说在粘合剂210的导热率比化合物半导体基板1的导热率高的情况下，化合物半导体基板中的粘合剂210所占的体积较大的情况散热性更好。因此，根据凹部的内部的体积的顺序，散热性按凹部3＞比较例B＞比较例A的顺序出色。即，化合物半导体芯片100A与比较例A或者比较例B相比，安装于模块基板200的情况下的散热性提高。
此外，也可以根据形成在电路形成区域2的电路的配置来调整凹部3的形成位置。例如，如图8B所示那样在电路形成区域2形成HBT300(放大元件)的情况下，HBT300在[01－1]方向的中心附近发热量最大。因此，通过在化合物半导体基板1的第二主面12上，在与凹部3的开口部31对置的区域配置HBT300的大致中心，化合物半导体芯片的散热性进一步提高。
如以上所说明那样，在化合物半导体基板1中，能够利用晶体取向依赖性，将凹部3形成为反向台面型的侧面33a比正向台面型的侧面33b长。由此，化合物半导体基板1能够不经过繁琐的作业工序，而与比较例A或者比较例B相比使化合物半导体基板与模块基板的粘合更稳固，提高耐剥离性。另外，化合物半导体基板1与比较例A或者比较例B相比填充到凹部3的粘合剂的体积增大，从而安装于模块基板的情况下的散热性提高。
接下来，参照图9，对本实施方式的变形例进行说明。图9是本发明的第一实施方式的变形例所涉及的化合物半导体芯片的俯视图。此外，在以下所示的其它实施方式以及变形例中，对与化合物半导体芯片100A相同的要素附加相同的附图标记而省略说明。另外，省略对与第一实施方式共同的事项的记述，仅对不同点进行说明。特别是对于相同的构成所带来的相同的作用效果并不在每个实施方式中依次提及。
图9所示的化合物半导体芯片100B具备多个(在本变形例中是六个)凹部3。具体而言，例如在[01－1]方向排列三个凹部3，在[011]方向排列两个凹部3。各凹部3的尺寸并不特别限定，但例如在本实施方式中，开口部的短边为100μm，长边为400μm。此外，由于凹部3的构成与化合物半导体芯片100A中的凹部3相同，所以省略详细的说明。
根据这样的构成，化合物半导体芯片100B也能够得到与化合物半导体芯片100A相同的效果。此外，凹部3的总数以及排列的构成并不限定于此。另外，多个凹部的尺寸即可全部相同，也可以按每个凹部不同。
接下来，参照图10～图14，对本实施方式的其它的变形例进行说明。图10是本发明的第一实施方式的其它的变形例所涉及的化合物半导体芯片的俯视图，图11是图10的E－E线剖视图，图12是图10的F－F线剖视图，图13是图10的G－G线剖视图。
图10所示的化合物半导体芯片100C除了化合物半导体芯片100B的构成之外，还具有多个通孔。具体而言，例如在化合物半导体基板1的周边区域以及[011]方向的中央区域设置多个通孔130、131，在凹部3的区域内设置多个通孔132、133。通孔130～133形成为从化合物半导体基板1的第一主面10朝向第二主面12侧，贯通化合物半导体基板1而到达电路形成区域2。另外，在化合物半导体基板1的第一主面10侧依次层叠有电极层140、141。具体而言，电极层140、141形成在化合物半导体基板1的第一主面、和凹部3的内表面以及通孔130～133的内表面。由此，经由电极层140、141，能够实现形成在电路形成区域2的各个电路与化合物半导体芯片100C的外部的电导通。
图14是用于说明通孔的功能的图。在图14中，作为一个例子，例示了在电路形成区域2形成有HBT，该HBT的发射极与形成在通孔133的内表面的电极层140、141电连接的情况。具体而言，在化合物半导体基板1上依次形成有缓冲层150(非掺杂GaAs)、子集电极层151(n型GaAs)、集电极层152(n型GaAs)、基极层153(p型GaAs)、发射极层154(n型InGaP)、接触层155(n型GaAs)、以及接触层156(n型InGaAs)。另外，在子集电极层151上形成有集电极电极157以及集电极布线158，在基极层153上形成有基极电极159以及基极布线160，在接触层156上形成有发射极电极161以及发射极布线162。并且，在形成于通孔133的内表面的电极层140上形成有连接用电极163。此外，未形成HBT的区域是绝缘注入区域170，电路被绝缘膜171(SiN)以及钝化膜172(SiN)覆盖。
发射极布线162向通孔133侧延伸突出，并与连接用电极163电连接。由此，发射极层154经由接触层155、接触层156、发射极电极161、发射极布线162以及连接用电极163与形成在通孔133的内表面的电极层140以及电极层141电连接。
此外，图14所示的构成是一个例子，与通孔内的电极层电连接的电极并不限定于HBT的发射极。另外，上述的HBT的各材料只是一个例子，并不限定于此。
另外，通孔的形状并不特别限定。例如通孔的开口部既可以如通孔130、132那样为正圆形，也可以如通孔131、133那样为椭圆形。另外，在本实施方式中，在化合物半导体基板形成了凹部3的区域、和未形成凹部3的区域双方形成有通孔，但通孔的形成位置并不特别限定。
接下来，参照图15～图17，对本发明的第二实施方式所涉及的化合物半导体芯片进行说明。图15是本发明的第二实施方式所涉及的化合物半导体芯片的俯视图，图16是本发明的第二实施方式的变形例所涉及的化合物半导体芯片的俯视图，图17是本发明的第二实施方式的其它的变形例所涉及的化合物半导体芯片的俯视图。此外，图15～图17所示的图是从第一主面10侧俯视化合物半导体基板1时的俯视图。另外，在图15～图17中，通过实线示出化合物半导体基板1的第一主面10与形成在化合物半导体基板1的各个凹部4a～4c的开口部的接线。
图15～图17所示的化合物半导体芯片100D～100F中的凹部4a～4c与化合物半导体芯片100A～100C中的凹部3相比，开口部的形状不同。具体而言，凹部4a的开口部是形成为到达化合物半导体基板1的[0－1－1]方向的两端部的大致矩形形状。即，凹部4a成为在[0－1－1]方向贯通的槽状。另外，凹部4b的开口部是多边形(在图16所示的例子中为八边形)状。另外，凹部4c的开口部是十字型。根据这样的构成，在凹部4a～4c中与[0－1－1]方向平行的接线所对应的侧面也成为反向台面型，与[01－1]方向平行的接线所对应的侧面也成为正向台面型。另外，在凹部4a～4c的开口部中，也与凹部3的开口部相同，与[0－1－1]方向平行的接线的总长度比与[01－1]方向平行的接线的总长度长。因此，化合物半导体芯片100D～100F能够得到与化合物半导体芯片100A相同的效果。
此外，凹部的开口部的形状并不限定于此。另外，虽然图15～图17所示的例子在化合物半导体基板内形成一种且一个凹部，但也可以在化合物半导体基板形成多种或者多个凹部。
接下来，参照图18A～图18L，对本发明的第一实施方式的其它的变形例所涉及的化合物半导体芯片100C的制造方法进行说明。这里，图18A～图18L是表示本发明的第一实施方式的其它的变形例所涉及的化合物半导体芯片的制造方法的顺序的图。图18A～图18L所示的图示出与图1中的A－A线剖视图相同的方向。此外，在以下的说明中，作为电路的一个例子，示出在电路形成区域形成了HBT的情况。另外，为了方便说明，对于与图4A～图4E或者图14所示的要素对应的要素，使用与在该附图中使用的附图标记相同的附图标记而省略说明。
首先，如图18A所示，通过一般的半导体工序，在化合物半导体基板1上的电路形成区域形成HBT。
接下来，如图18B所示，夹着蜡(wax)180将钝化膜172粘贴于蓝宝石基板181。另外，对化合物半导体基板1进行磨削，使化合物半导体基板1的第一主面10露出。化合物半导体基板1的厚度例如是75μm左右。
接下来，如图18C所示，在化合物半导体基板1的第一主面10上形成具有开口部22a、22b的光致抗蚀剂23。光致抗蚀剂23起到凹部形成工序中的掩模的作用。
接下来，如图18D所示，将光致抗蚀剂23作为掩模，通过湿式蚀刻在开口部22a、22b之下形成凹部3a、3b。湿式蚀刻液的组成例如是磷酸：过氧化氢溶液：水＝1：2：40(体积比)。此外，由于化合物半导体的晶体取向依赖性与图4A～图4E中的说明相同所以省略。
接下来，如图18E所示，除去光致抗蚀剂23。
接下来，如图18F所示，在化合物半导体基板1的第一主面10上形成具有开口部190的光致抗蚀剂191。光致抗蚀剂191起到通孔形成工序中的掩模的作用。
接下来，如图18G所示，将光致抗蚀剂191作为掩模，通过各向异性干式蚀刻在开口部190之下形成通孔130。通孔130贯通化合物半导体基板1以及绝缘注入区域170，并延伸到连接用电极163。
接下来，如图18H所示，除去光致抗蚀剂191。
接下来，如图18I所示，在化合物半导体基板1的第一主面10、凹部3a、3b的内表面以及通孔130的内表面的整个面形成电极层140。电极层140例如通过无电镀法(electroless plating)形成，例如由厚度0.05μm左右的Pd构成。
接下来，如图18J所示，在电极层140之上层叠电极层141。电极层141例如通过电镀法形成，例如由厚度4.5μm左右的Au构成。
接下来，如图18K所示，取下蜡180以及蓝宝石基板181。
接下来，如图18L所示，使晶圆上下反转，并通过切割等得到化合物半导体芯片。
通过上述的制造方法，能够制造在化合物半导体基板1具备凹部以及通孔的化合物半导体芯片100C。此外，化合物半导体芯片的制造方法并不限定于此。
接下来，参照图19，对安装了化合物半导体芯片的功率放大模块进行说明。图19是安装了本发明的第一实施方式的其它的变形例所涉及的化合物半导体芯片的功率放大模块的剖视图。此外，虽然安装化合物半导体芯片100A～100F的模块的用途并不特别限定，但例如可以搭载于移动电话等移动体通信机，并作为放大发送信号的功率放大模块使用。图19所示的功率放大模块1000示出与图10中的F－F线剖视图相同的方向。此外，虽然图19示出化合物半导体芯片100C作为化合物半导体芯片的一个例子，但对于其它的变形例以及其它的实施方式也能够同样地安装。另外，虽然在图19中省略图示，但也可以在功率放大模块1000安装有传递电信号的键合线、电容器、电感器或者电阻器等表面安装器件(SMD：Surface Mount Device)，或者硅IC等。
在功率放大模块1000中，化合物半导体芯片100C被安装在模块基板1100上。模块基板1100通过在[100]方向交替地层叠绝缘体基板1110以及导体层1120而构成。绝缘体基板1110例如由玻璃环氧树脂构成，导体层1120例如由Cu构成。另外，在模块基板1100形成有在[100]方向贯通的通孔1130。在通孔1130例如填充有Cu。
通过粘合剂1140在模块基板1100的主面上粘合化合物半导体芯片100C。粘合剂1140夹在化合物半导体芯片100C中的化合物半导体基板1的第一主面10与模块基板1100之间，并进一步填充到形成于化合物半导体基板1的凹部3以及通孔132、133中。另外，化合物半导体芯片100C被固化树脂1150覆盖。
粘合剂1140具有比化合物半导体基板1的导热率(例如，46W/mK左右)高的导热率(例如，140W/mK左右)。由此，如在图8A中说明的那样，因电路引起的热容易传递到模块基板1100侧。因此，安装了化合物半导体芯片100C的功率放大模块1000的散热性提高。
此外，安装了化合物半导体芯片100A～100F的模块并不限定于功率放大模块，也可以安装于其它的任何的电子部件模块。
以上，对本发明的例示性实施方式进行了说明。在化合物半导体芯片100A～100F中，形成于化合物半导体基板1的凹部3具有与底面32所成的角为锐角的侧面33a、和与底面32所成的角为钝角的侧面33b，且化合物半导体基板1的第一主面10与侧面33a的接线的总长度比该第一主面10与侧面33b的接线的总长度长。由此，将凹部3形成为反向台面型的侧面33a比正向台面型的侧面33b长。因此，化合物半导体基板1与形成了比较例A或者比较例B的基板相比化合物半导体基板与模块基板的粘合变得稳固，耐剥离性提高。
另外，侧面33a沿着化合物半导体基板1的晶体取向[011]方向延伸，侧面33b沿着晶体取向[01－1]方向延伸。由此，能够利用化合物半导体基板1的晶体取向依赖性，来形成反向台面型的侧面33a以及正向台面型的侧面33b。因此，化合物半导体基板1能够不经过繁琐的作业工序而与形成了比较例A或者比较例B的基板相比提高耐剥离性。
另外，也可以在凹部3的内部，底面32与侧面33a所成的角θ为θ＝54.7±4度，底面32与侧面33b所成的角φ为φ＝180－θ度。
另外，也可以凹部3的深度D为化合物半导体基板1的厚度以下。
另外，虽然化合物半导体基板1的材料并不特别限定，但例如也可以由GaAs或者InP构成。
另外，在化合物半导体芯片100C中，化合物半导体基板1具有从第一主面10贯穿第二主面12的通孔130～133。由此，能够经由形成在通孔130～133的内表面的电极层140、141，实现电路与化合物半导体芯片100C的外部的电导通。
另外，在模块基板安装了化合物半导体芯片100A～100F的功率放大模块中，夹在化合物半导体基板1与模块基板之间的粘合剂的导热率比化合物半导体基板1的导热率高。由此，因电路引起的热容易传递至模块基板侧。因此，该功率放大模块与形成了比较例A或者比较例B的基板相比散热性提高。
另外，虽然形成于电路形成区域2的放大元件的配置并不特别限定，但例如可以将放大元件形成为放大元件的[01－1]方向的大致中心被配置在与凹部3的开口部31对置的区域。由此，功率放大模块的散热性进一步提高。
以上说明的各实施方式是用于使本发明的理解变得容易的实施方式，并不用于对本发明进行限定解释。本发明在不脱离其主旨的范围内，能够变更或者改进，并且在本发明中包含其等效物。即，只要具备本发明的特征则本领域技术人员对各实施方式适当地施加设计变更后的实施方式也包含于本发明的范围。例如，各实施方式所具备的各要素及其配置、材料、条件、形状、尺寸等并不限定于例示的实施方式而能够适当地变更。另外，各实施方式所具备的各要素只要在技术上可能则能够组合，将它们组合后的实施方式只要包含本发明的特征则也包含于本发明的范围。
附图标记说明
1、21…化合物半导体基板，2…电路形成区域，3、3a、3b、4a、4b、4c…凹部，10…第一主面，12…第二主面，22、22a、22b、31、190…开口部，23、191…光致抗蚀剂，32…底面，33、33a、33b、40、41…侧面，34…接线，100A～100F…化合物半导体芯片，130～133、1130…通孔，140、141…电极层，150…缓冲层，151…子集电极层，152…集电极层，153…基极层，154…发射极层，155…接触层，156…接触层，157…集电极电极，158…集电极布线，159…基极电极，160…基极布线，161…发射极电极，162…发射极布线，163…连接用电极，170…绝缘注入区域，171…绝缘膜，172…钝化膜，180…蜡，181…蓝宝石基板，200、1100…模块基板，210、1140…粘合剂，220、1150…固化树脂，1000…功率放大模块，1110…绝缘体基板，1120…导体层。

Claims (8)

1.一种化合物半导体基板，其中，
具有与第一方向以及和上述第一方向正交的第二方向平行的第一主面、与上述第一主面对置的第二主面、以及从上述第一主面朝向上述第二主面形成的凹部，
上述凹部具有形成在上述第一主面的开口部、与上述开口部对置的底面、以及在上述开口部与上述底面之间形成上述凹部的多个侧面，
上述多个侧面包含：
沿着上述第一方向延伸的至少一个第一侧面，上述第一侧面在上述凹部的内部与上述底面所成的角大致为θ度；以及
沿着上述第二方向延伸的至少一个第二侧面，上述第二侧面在上述凹部的内部与上述底面所成的角大致为φ度，
上述第一主面与上述至少一个第一侧面的接线的总长度比上述第一主面与上述至少一个第二侧面的接线的总长度长，
其中，0＜θ＜90，90＜φ＜180。
2.根据权利要求1所述的化合物半导体基板，其中，
上述第一方向与上述化合物半导体基板的晶体取向的[011]方向或者[0－1－1]方向平行，
上述第二方向与上述化合物半导体基板的晶体取向的[01－1]方向或者[0－11]方向平行。
3.根据权利要求1或者2所述的化合物半导体基板，其中，
上述θ为54.7±4，上述φ为180－θ。
4.根据权利要求1～3中任意一项所述的化合物半导体基板，其中，
上述凹部的从上述开口部到上述底面的距离为上述化合物半导体基板的厚度以下。
5.根据权利要求1～4中任意一项所述的化合物半导体基板，其中，
上述化合物半导体基板由GaAs或者InP构成。
6.根据权利要求1～5中任意一项所述的化合物半导体基板，其中，
上述化合物半导体基板具有从上述第一主面贯穿上述第二主面的通孔。
7.一种功率放大模块，其中，具有：
权利要求1～6中任意一项所述的化合物半导体基板；
放大元件，形成在上述化合物半导体基板的上述第二主面上；
模块基板，安装了上述化合物半导体基板；以及
粘合剂，夹在上述化合物半导体基板与上述模块基板之间，并填充到上述凹部，
上述粘合剂的导热率比上述化合物半导体基板的导热率高。
8.根据权利要求7所述的功率放大模块，其中，
上述放大元件形成为在上述第二主面上上述放大元件的大致中心被配置在与上述凹部的上述开口部对置的区域。
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