CN108428702A - The manufacturing method of dynamic random access memory - Google Patents
The manufacturing method of dynamic random access memory Download PDFInfo
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- CN108428702A CN108428702A CN201810379119.2A CN201810379119A CN108428702A CN 108428702 A CN108428702 A CN 108428702A CN 201810379119 A CN201810379119 A CN 201810379119A CN 108428702 A CN108428702 A CN 108428702A
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
Abstract
The present invention provides a kind of manufacturing method of dynamic random access memory, wordline array, digit line array, contact bolt array, contact pad array and array of capacitors including preparing dynamic random access memory, each contact pad are all connected to above a contact bolt；Wherein, the offset direction of adjacent two row contact pad is on the contrary, make the contact pad array arrange in six sides；Each capacitor is all connected to the top of a contact pad.In dynamic random access memory prepared by the present invention, six sides that planar layout structure is transformed to capacitor by the four directions arrangement of contact bolt arrange, and can improve the area of capacitor in storage unit, obtain the capacitance of bigger.The present invention is 6F in the six sides layout and memory cell area for realizing capacitor2While, ensure that active area, wordline, bit line are linear type, layout is more simple, advantageously reduces process complexity, improves the stability of memory.
Description
Technical field
The invention belongs to memory areas, are related to a kind of manufacturing method of dynamic random access memory.
Background technology
Capacitor is a kind of passive electronic components storing energy with electrostatic format of field.In simplest form, capacitor
Including two conductive plates, and it is isolated by being referred to as dielectric insulating materials between two conductive plates.The capacitance of capacitor
It is directly proportional to the surface area of pole plate, between pole plate at a distance from be inversely proportional.The capacitance of capacitor additionally depends on the object of separation pole plate
The dielectric constant of matter.
The standard unit of capacitance is method (farad, referred to as F), this is a big unit, and more conventional unit is microfarad
(microfarad, abbreviation μ F) and pico farad (picofarac, abbreviation PF), wherein 1 μ F=10-6F, 1pF=10-12F。
Capacitor can be manufactured on integrated circuit (IC) chip.In dynamic random access memory (dynamic
Random access memory, abbreviation DRAM) in, capacitance is commonly used in connecting with transistor.Capacitor, which helps to maintain, to be deposited
The content of reservoir.Due to its small physical size, these components have low capacitance.They must be with thousands of frequencies per second
It recharges, otherwise, DRAM will lose data.
In integrated circuit fabrication process field, with size of electronic devices reduce minimum feature feature so that 20 nanometers with
Under.However 20 nanometers or less capacitance array designs are selected with six side's closest packings for best geometry.Existing dynamic randon access
In the manufacturing method of memory, to realize six side's closest packings of capacitance array, usually there is complicated manufacturing process, and bit line
Using Curve Design, technology difficulty is substantially increased.
Therefore, how to propose a kind of manufacturing method of the more simple dynamic random access memory of manufacturing process, and reach
To smaller memory cell area and higher charge storage, it is important to become those skilled in the art urgently to be resolved hurrily one
Technical problem.
Invention content
In view of the foregoing deficiencies of prior art, the purpose of the present invention is to provide a kind of dynamic random access memory
Manufacturing method, for solves the problems, such as dynamic random access memory in the prior art manufacturing method complexity.
In order to achieve the above objects and other related objects, the present invention provides a kind of manufacturer of dynamic random access memory
Method includes the following steps：
S1：Semiconductor structure is provided, the semiconductor structure includes substrate, positioned at the multilayer film of the substrate top surface
Structure and contact pad positioned at the multi-layer film structure upper surface；
S2：The passivation layer of a covering contact pad is formed on the semiconductor structure；
S3：The first sacrificial layer, the first supporting layer, the second sacrificial layer and the second support are sequentially formed on the passivation layer
Layer；
S4：It is formed up and down through second supporting layer, the second sacrificial layer, the first supporting layer, the first sacrificial layer and described
Multiple through-holes of passivation layer, each through-hole are located at the surface of a contact pad, and expose the Contact welding
The upper surface of disk；
S5：The first conductive material layer is formed in the side wall of the through-hole and bottom；
S6：Multiple openings for running through second supporting layer up and down are formed, the opening exposes second sacrificial layer
A part, and formed around the opening and be laid out while opening the opening；
S7：It is open as etching solution through window with described, wet etching removes second sacrifice around the through-hole
Layer；
S8：Part first supporting layer is removed, and wet etching removes first sacrificial layer around the through-hole；
And
S9：The high-K dielectric layer for covering the first conductive material layer inner surface and outer surface is formed, and is formed described in covering
Second conductive material layer of high-K dielectric layer outer surface；Wherein, first conductive material layer is made respectively with the second conductive material layer
For the bottom crown and top crown of capacitor, first conductive material layer, high-K dielectric layer and the second conductive material layer composition are two-sided
Capacitor arrangement.
Optionally, it is located at the high-K dielectric layer of first conductive material layer outer surface and second conductive material
It is isolated by the passivation layer between the bottom and the contact pad of layer, the capacitance characteristic of capacitor can be improved, is obtained highly reliable
The capacitor of property and high stability.
Optionally, the material of first sacrificial layer or the second sacrificial layer includes silica or silane oxide；It is described blunt
Change layer, the material of the first supporting layer or the second supporting layer include in silicon nitride, silicon oxynitride, aluminium oxide any one or it is arbitrary
Two or more combinations；The etching solution includes hydrofluoric acid solution.
Optionally, in first sacrificial layer and the second sacrificial layer doped in boron or phosphorus one kind or combination, Ke Yibao
The uniformity of critical size is demonstrate,proved, and improves oxide removal efficiency.
Optionally, in step S6, an opening is overlapping with multiple through-holes simultaneously, the through-hole only a fraction
It is overlapping with the opening.
Optionally, the opening is overlapping with 2~10 through-holes simultaneously.
Optionally, in step S6, layout includes having identical opening shape and each institute around the opening of formation
State opening and 3 through-holes overlap mutually around be laid out, process complexity can be reduced, and form the capacitor arrangement of stabilization.
Optionally, the semiconductor structure further includes：
Wordline array is located in the substrate, including a plurality of linear type wordline, these wordline are parallel with Y-direction, and
Equidistantly arrangement in X direction, wherein X-direction is mutually perpendicular to Y-direction；
Digit line array is located in the multi-layer film structure, including a plurality of linear type bit line, these bit lines are flat with X-direction
Row, and equidistantly arranged along Y-direction；
Contact bolt array is located in the multi-layer film structure, including multiple contact bolts, wherein the figure of the wordline array
Shape defines multiple independent rectangular areas on a substrate with the digit line array, and each contact bolt is respectively formed in one
In the rectangular area, the contact bolt array is made to arrange in four directions；
Contact pad array, including multiple contact pads, each contact pad are all connected to a contact bolt
Top, and pre-determined distance is deviated in the Y direction relative to the contact bolt；Wherein, the offset direction of adjacent two row contact pad
On the contrary, an i.e. wherein row contact pad is deviated along positive Y-direction, in addition an adjacent column contact pad is deviated along Y-direction is born, and is made described
Contact pad array is arranged in six sides.
Optionally, the spacing of adjacent two bit lines be D, each contact pad both with respect to the contact bolt in the Y direction or
Offset distance D/4 in negative Y-direction.
Optionally, the spacing of adjacent two wordline is 2F, and the spacing of adjacent two bit lines is 3F, and F is minimum feature size.
Optionally, the semiconductor structure further includes active area array, and the active area array includes multiple arranged in parallel
Linear type active area, the active area and X-direction are in predetermined angle inclination, the projected length of the active area in the X direction
For Lx, and meet 4F<Lx<6F；
The center of the active area is arranged on bit line center line in X direction, and simultaneously in alignment with adjacent two wordline
Between interval center line on；
For multiple active areas corresponding to same bit line, the center of two neighboring active area is apart in X direction
4F；
For multiple active areas corresponding to not corresponding lines, the center of the two neighboring active area arranged side by side that misplaces is in the side X
Upward projection interval is 2F, the two neighboring projection interval at the same center for arranging the active area on straight line in the X direction
For 6F.
Optionally, the predetermined angle is the active zone centerline and acute angle θ formed by X-direction, and meets 15 °
<θ<35°。
Optionally, the intersection region of the bit line and the active area is equipped with bit line contact portion, and the bit line passes through described
Bit line contact portion is connect with the active area.
Optionally, in the contact bolt upper surface, equivalent deviates the contact pad in same direction so that the contact
Pad is arranged in six sides；And the double sided capacitor structure have it is identical with the contact pad be in six sides arrangement capacitor
Array.
Optionally, top electrode is connected on the top crown, the high-K dielectric layer includes zirconium oxide layer and aluminium oxide
Layer, at least one section of the bottom crown is U-shaped, and the corresponding section of the high-K dielectric layer and the top crown is M types.
As described above, the manufacturing method of the dynamic random access memory of the present invention, has the advantages that：The present invention
In the dynamic random access memory of preparation, six sides that layout structure is transformed to capacitor by the four directions arrangement of contact bolt arrange,
The area that capacitor in storage unit can be improved obtains the capacitance of bigger.The dynamic random access memory of the present invention exists
The six sides layout and memory cell area for realizing capacitor are 6F2While, ensure that active area, wordline, bit line are straight line
Type advantageously reduces process complexity, improves the stability of memory to realize more simple layout structure.The present invention
Dynamic random access memory manufacturing method, by contact bolt four directions arrangement array be transformed into the contact arranged in six sides
Pad array then can conveniently produce the two-sided capacitance arranged with six sides above the contact pad arranged with six sides
Therefore device structure can realize the capacitance of bigger on identical memory cell area, improve dynamic random access memory
Storage capacity.
Description of the drawings
Fig. 1 is shown as the plane figure of dynamic random access memory prepared by the present invention.
Fig. 2 is shown as the plane figure of wordline array in dynamic random access memory prepared by the present invention.
Fig. 3 is shown as the plane figure of dynamic random access memory neutrality line array prepared by the present invention.
Fig. 4 is shown as the plane figure of wordline array and digit line array in dynamic random access memory prepared by the present invention
Figure.
Fig. 5 is shown as wordline array, digit line array and contact bolt battle array in dynamic random access memory prepared by the present invention
The plane figure of row.
Fig. 6 is shown as wordline array, digit line array, contact bolt array in dynamic random access memory prepared by the present invention
And the plane figure of contact pad array.
Fig. 7 is shown as the plane of the contact bolt array in four directions arrangement in dynamic random access memory prepared by the present invention
Layout.
Fig. 8 is shown as the flat of the contact pad array arranged in six sides in dynamic random access memory prepared by the present invention
Face layout.
Fig. 9 is shown as the plane of the array of capacitors in six sides arrangement in dynamic random access memory prepared by the present invention
Layout.
Figure 10 is shown as the plane figure of active area array in dynamic random access memory prepared by the present invention.
Figure 11 is shown as active area array, wordline array and bit line battle array in dynamic random access memory prepared by the present invention
The plane figure of row.
The intersection region that Figure 12 is shown as dynamic random access memory neutrality line and active area prepared by the present invention is equipped with
The schematic diagram in bit line contact portion.
Figure 13 is shown as sectional view of the dynamic random access memory of the invention prepared along dotted line shown in Figure 12.
Figure 14 is shown as the enlarged structure schematic diagram of wordline in dynamic random access memory prepared by the present invention.
Figure 15 is shown as the structural schematic diagram of capacitor in dynamic random access memory prepared by the present invention.
Figure 16 is shown as the present invention and prepares the passivation for forming a covering contact pad in dynamic random access memory
The schematic diagram of layer.
Figure 17 is shown as the present invention and prepares that on the passivation layer to sequentially form first in dynamic random access memory sacrificial
The schematic diagram of domestic animal layer, the first supporting layer, the second sacrificial layer and the second supporting layer.
Figure 18 is shown as the present invention and prepares to be formed in dynamic random access memory up and down through second supporting layer, the
Two sacrificial layers, the first supporting layer, the first sacrificial layer and the passivation layer multiple through-holes schematic diagram.
Figure 19 is shown as the present invention and prepares in dynamic random access memory to form the in the side wall of the through-hole and bottom
The schematic diagram of one conductive material layer.
Figure 20 is shown as being formed in present invention preparation dynamic random access memory multiple up and down through second support
The schematic diagram of the opening of layer.
Figure 21-Figure 22 is shown as the plane figure of the opening.
It is etching solution by window that Figure 23, which is shown as the present invention in preparing dynamic random access memory with the opening,
Wet etching removes second sacrificial layer around the through-hole；And continue to remove part first supporting layer, and wet method
The schematic diagram of first sacrificial layer around through-hole described in erosion removal.
Figure 24 is shown as the present invention and forms covering first conductive material layer in preparing dynamic random access memory
The schematic diagram of the high-K dielectric layer of inner surface and outer surface.
Figure 25 is shown as the present invention and forms the covering high-K dielectric layer outer surface in preparing dynamic random access memory
The second conductive material layer schematic diagram.
Figure 26 is shown as the present invention and continuously forms showing for third conductive material layer in preparing dynamic random access memory
It is intended to.
Component label instructions
100 semiconductor structures
1 wordline array
101 wordline
1011 gate dielectric layers
1012 the first metal layers
1013 second metal layers
1014 separation layers
2 digit line arrays
201 bit lines
3 contact bolt arrays
301 contact bolts
4 contact pad arrays
401 contact pads
5 array of capacitors
501 capacitors
5011 top crowns
5012 bottom crowns
5013 high-K dielectric layers
5014 top electrodes
6 active area arrays
601 active areas
7 bit line contact portions
8 substrates
9 multi-layer film structures
10 passivation layers
11 first sacrificial layers
12 first supporting layers
13 second sacrificial layers
14 second supporting layers
15 through-holes
16 first conductive material layers
17 openings
18 high-K dielectric layers
19 second conductive material layers
20 third conductive material layers
21 fleet plough groove isolation structures
Specific implementation mode
Illustrate that embodiments of the present invention, those skilled in the art can be by this specification below by way of specific specific example
Disclosed content understands other advantages and effect of the present invention easily.The present invention can also pass through in addition different specific realities
The mode of applying is embodied or practiced, the various details in this specification can also be based on different viewpoints with application, without departing from
Various modifications or alterations are carried out under the spirit of the present invention.
It please refers to Fig.1 to Figure 26.It should be noted that the diagram provided in the present embodiment only illustrates this in a schematic way
The basic conception of invention, package count when only display is with related component in the present invention rather than according to actual implementation in schema then
Mesh, shape and size are drawn, when actual implementation kenel, quantity and the ratio of each component can be a kind of random change, and its
Assembly layout kenel may also be increasingly complex.
Embodiment one
The present invention prepares a kind of dynamic random access memory, the dynamic random access memory include wordline array,
Digit line array, contact bolt array, contact pad array and array of capacitors.Wherein, Fig. 1 is shown as the dynamic randon access and deposits
The plane figure of reservoir.The relative position between arrangement mode and different arrays in order to clearly show that each array itself is closed
System, Fig. 2, Fig. 3, Fig. 7, Fig. 8, Fig. 9 are respectively indicated as the wordline array 1, digit line array 2, contact bolt array 3, contact pad
Array 4,5 respective plane figure of array of capacitors, Fig. 4 are shown as the wordline array 1 and the common plane of digit line array 2
Layout, Fig. 5 are shown as the wordline array 1, digit line array 2 and the common plane figure of contact bolt array 3, Fig. 6 and show
For the wordline array 1, the plane figure of digit line array 2, contact bolt array 3 and contact pad array 4.
Specifically, as shown in Figures 1 and 2, the wordline array 1 includes a plurality of linear type wordline 101, these wordline 101
It is parallel with Y-direction, and equidistantly arrangement in X direction, wherein X-direction is mutually perpendicular to Y-direction.
As an example, the spacing of adjacent two wordline is 2F, wherein F is minimum feature size.Herein, minimal characteristic ruler
Very little (Minimum feature size) refer to refer to minimum dimension in semiconductor devices, minimum feature size is smaller, chip
Integrated level it is higher, performance is better, and power consumption is lower.For the CMOS technology of present mainstream, minimum feature size typically refers to
The width of polysilicon as grid, that is, transistor channel length.The present invention is suitable for the semiconductor work of a variety of processing procedures
Skill, as an example, minimum feature size range can be 14-130nm.
As shown in Figures 1 and 3, the digit line array 2 include a plurality of linear type bit line 201, these bit lines 201 with the side X
It to parallel, and is equidistantly arranged along Y-direction, wherein the spacing of adjacent two bit lines is D.As an example, adjacent two bit lines
Space D=3F, in the dynamic random access memory, the area of storage unit is 6F2, so as to realize higher deposit
Store up density.
Although being pointed out that in dynamic random access memory that each capacitance corresponds to a storage unit,
Above-mentioned " area of storage unit " is not necessarily referring to the floor space of capacitance, the capacitor board surface area of whole up or down electrode or outermost
Layer metallic surface product, and refer to the area in dynamic random access memory shared by average each storage unit.Such as dynamic
The total storage area of random access memory is 600F2, include 100 storage units in the dynamic random access memory, then
Area shared by average each storage unit is 600F2÷ 100=6F2, single so as to claim to store in the dynamic random access memory
The area of member is 6F2.In the present embodiment, the figure of the wordline array defines more on a substrate with the digit line array
A independent rectangular area, each rectangular area correspond to a capacitance respectively, that is, correspond to a storage unit, and due to adjacent two
The spacing of wordline is 2F, and the spacing of adjacent two bit lines is 3F, then the area of storage unit is 2F × 3F=6F2。
As shown in figure 4, the figure of the wordline array 1 defined with digit line array 2 it is multiple independent on a substrate
Rectangular area.The figure of the wordline array 1 can be specifically be covered in the linear type wordline 101 and with the bit line battle array
The hard mask (hard mask) that row 2 do not overlap mutually.
As shown in Fig. 1, Fig. 5 and Fig. 7, the contact bolt array 3 includes multiple contact bolts 301, and each contact bolt 301 is distinguished
It is formed in a rectangular area, the contact bolt array 3 is made to arrange in four directions.
As shown in Fig. 1, Fig. 6 and Fig. 8, the contact pad array 4 includes multiple contact pads 401, each contact pad
401 are all connected to 301 top of the contact bolt, and deviate pre-determined distance in the Y direction relative to the contact bolt 301；
Wherein, the offset direction of adjacent two row contact pad 401 (shows different lines contact pad in Fig. 6 using hollow arrow on the contrary
Offset direction), i.e., a wherein row contact pad 401 along positive Y-direction deviate, in addition an adjacent column contact pad 401 is along the negative side Y
To offset, the contact pad array 4 is made to arrange in six sides.
As an example, each contact pad 401 is all connected to 301 top of the contact bolt, and connect relative to described
Touch the offset distance D/4 in the Y direction or in negative Y-direction of bolt 301.The material of the contact pad 401 may include polysilicon or tungsten,
It can connect up with periphery local interlinkage and be formed simultaneously.
As shown in Fig. 1 and Fig. 9, the array of capacitors 5 includes multiple capacitors 501；Each capacitor 501 is all connected to
The top of one contact pad 401, the array of capacitors 5 are arranged in six sides.
In dynamic random access memory prepared by the present invention, layout structure is converted by the four directions arrangement of contact bolt 301
It arranges for six sides of capacitor 501, the area of capacitor in storage unit can be improved, obtain the capacitance of bigger.
Specifically, preparing the dynamic random access memory further includes active area array.As shown in Figure 10, it is shown as institute
State the plane figure of active area array 6.The active area array 6 includes multiple linear type active areas 601 arranged in parallel, institute
Active area 601 is stated to tilt in predetermined angle with X-direction.In the present embodiment, the predetermined angle is 601 center line of the active area
With acute angle θ formed by X-direction, and meet 15 °<θ<35°.The projected length of the active area 601 in the X direction is Lx,
And meet 4F<Lx<6F。
As shown in figure 11, the active area array 6, wordline array 1 and the common plane figure of digit line array 2 are shown as
Figure, it is seen then that the center of the active area 601 is arranged on bit line center line in X direction, and simultaneously in alignment with adjacent two words
On interval center line between line.And for multiple active areas 601 corresponding to same bit line 201, phase in X direction
The center of adjacent two active areas 601 is at a distance of 4F；For multiple active areas 601, two neighboring mistake corresponding to not corresponding lines 201
The projection interval of the center of position active area arranged side by side in the X direction is 2F, the two neighboring active area on same arrangement straight line
Center projection interval in the X direction be 6F.
As shown in figure 12, in the present embodiment, the bit line 201 and the intersection region of the active area 601 connect equipped with bit line
Contact portion 7 (shown in dotted line source), the bit line 201 are connect by bitline contact portion 7 of institute with the active area 601.
As an example, Figure 13 is shown as the dynamic random access memory of the invention prepared along one of dotted line shown in Figure 12
Kind sectional view, as shown, the dynamic random access memory includes semiconductor structure 100, the semiconductor structure 100 wraps
Substrate 8 and the multi-layer film structure being formed on the substrate 89 are included, the wordline array 1 and the active area array 6 are respectively provided with
In the substrate 8, and (the abbreviation of fleet plough groove isolation structure 21 between each active area 601 by being set in the substrate 8
STI) it is isolated, the digit line array 2 (not illustrating in fig. 13) and the contact bolt array 3 may be contained within the multilayer film knot
In structure 9, the contact pad array 4 is set to 9 top of the multi-layer film structure.
In the present embodiment, the wordline 101 is groove-shaped, is located in the substrate 8.4 are please referred to Fig.1, is shown as described
The enlarged structure schematic diagram of wordline 101.As an example, the wordline 101 includes metal gates (by the first metal layer 1012 grades the
Two metal layers 1013 form), surround the gate dielectric layer 1011 of the metal gates outer surface and be located at the metal gates and grid
The separation layer 1014 of 1011 top of dielectric layer.
Certainly, in other embodiments, the wordline 101 can also use other structures, should not excessively limit this herein
The protection domain of invention.
In dynamic random access memory prepared by the present invention, the capacitor 501 is located at the upper of the contact pad 401
Side.As an example, as shown in figure 15, the capacitor includes top crown 5011, bottom crown 5012 and is formed in the upper pole
High-K dielectric layer 5013 between plate 5011 and bottom crown 5012, wherein top electrode 5014 is connected on the top crown 5011,
The bottom crown 5012 is connect with the contact pad 401.
In the present embodiment, the bottom crown 5012 at least one section is U-shaped, the high-K dielectric layer 5013 and described
The corresponding section of top crown 5011 is M types, i.e., the high-K dielectric layer 5013 is formed simultaneously the interior table in U-shaped bottom crown 5012
Face and outer surface, the top crown 5011 are formed in the outer surface of the high-K dielectric layer 5013, constitute double sided capacitor structure.
Relative to single side capacitor arrangement, higher capacitance may be implemented in double sided capacitor structure.As an example, the high K dielectric
Layer includes zirconium oxide layer and alumina layer, wherein zirconium oxide and aluminium oxide are hafnium.
In dynamic random access memory prepared by the present invention, layout structure is transformed to capacitance by the four directions arrangement of contact bolt
Six sides of device arrange, and can improve the area of capacitor in storage unit, obtain the capacitance of bigger.The dynamic random of the present invention
Access memory is 6F in the six sides layout and memory cell area for realizing capacitor2While, ensure active area, wordline,
Bit line is linear type, to realize more simple layout structure, advantageously reduces process complexity, improves the steady of memory
It is qualitative.
Embodiment two
The present invention also provides a kind of manufacturing methods of dynamic random access memory, include the following steps：Referring initially to
Figure 16 executes step S1 and S2：Semiconductor structure 100 is provided, the semiconductor structure 100 includes substrate 8, is located at the lining
The multi-layer film structure 9 of 8 upper surface of bottom and contact pad 401 positioned at 9 upper surface of the multi-layer film structure.In the semiconductor
100 upper surface of structure forms the passivation layer 10 of a covering contact pad.As an example, the material of the passivation layer 10 includes
Any one or any two or more combinations in silicon nitride, silicon oxynitride, aluminium oxide.
Referring next to Figure 17, step S3 is executed：The first sacrificial layer 11, first is sequentially formed on the passivation layer 10
Support layer 12, the second sacrificial layer 13 and the second supporting layer 14.
Specifically, first sacrificial layer, 11 and second sacrificial layer 13 can be removed during subsequent technique, therefore claim
For sacrificial layer.First supporting layer, 12 and second supporting layer 14 be used for during subsequent technique first sacrificial layer 11 and
Second sacrificial layer 13 is used as braced frame after being removed.
As an example, the material of first sacrificial layer, 11 or second sacrificial layer 13 includes but not limited to silica, silane
Oxide etc. is easy to the material removed by wet etching.The passivation layer 10, the first supporting layer 12 or the second supporting layer 14
Material includes any one or any two or more combinations in silicon nitride, silicon oxynitride, aluminium oxide.
In the present embodiment, doped with boron or phosphorus in first sacrificial layer, 11 and second sacrificial layer 13, it is ensured that crucial
The uniformity of size, and improve oxide removal efficiency.
Then 8, S4 are please referred to Fig.1：It is formed and is supported up and down through second supporting layer 14, the second sacrificial layer 13, first
Multiple through-holes 15 of the 12, first sacrificial layer 11 of layer and the passivation layer 10, each through-hole are located at a contact pad
401 surface, and expose 401 upper surface of the contact pad.
Specifically, multilayer hard mask can be formed on second supporting layer 14 first, and it is based on bottom contact pads
Position and capacitor concrete structure, corresponding mask pattern is formed by photoetching process, is then based on the mask graph
Etch the through-hole 15.
9 are please referred to Fig.1 again, execute step S5：The first conductive material layer 16 is formed in the side wall of the through-hole 15 and bottom.
Specifically, first conductive material layer 16 is the bottom crown as capacitor, material includes but not limited to TiN
Equal metal materials.The high-K dielectric layer 18 positioned at 16 outer surface of the first conductive material layer and second conductive material
It is isolated by the passivation layer 10 between the bottom and the contact pad 401 of layer 19, the electricity of the capacitor subsequently prepared can be improved
Hold characteristic, obtains the capacitor of high reliability and high stability.
Figure 20 is please referred to again, executes step S6：Multiple openings 17 for running through second supporting layer 14 up and down are formed, it is described
Opening 17 exposes a part for second sacrificial layer 13, and the week of the opening is formed while opening the opening
Cloth office.
Specifically, an opening 17 not only can be only overlapping with a through-hole 15, can also simultaneously with it is multiple
(such as 2-10) described through-hole 15 is overlapping.
As an example, Figure 21-Figure 22 is shown as several plane figures of the opening 17.Wherein, it is shown in Figure 21
The situation of corresponding 1,2,3,4,5 through-hole of one opening.In the present embodiment, it is preferred to use layout side shown in Figure 22
Formula, the shape all same of multiple openings 17, and each opening is overlapping with 3 through-holes.
In the present embodiment, 15 only a fraction of the through-hole and the opening 17 are overlapping, to can around each through-hole
Retain a part of support construction, to ensure the structural stability of the first conductive material layer 16 described in subsequent wet corrosion process.
Figure 23 is please referred to again, executes step S7 and step S8：
Step S7：With it is described opening 17 for etching solution by window, wet etching removes described around the through-hole 15
Second sacrificial layer 13.
Step S8：Part first supporting layer 12 (not shown) is removed, and wet etching removes around the through-hole 15
First sacrificial layer 11；
As an example, the etching solution includes hydrofluoric acid solution.
Figure 24-Figure 25 is finally please referred to, step S9 is executed：It is formed and covers 16 inner surface of the first conductive material layer and outer
The high-K dielectric layer 18 (as shown in figure 24) on surface, and form the second conductive material layer 19 for covering the high-K dielectric layer outer surface
(as shown in figure 25).
Specifically, first conductive material layer, 16 and second conductive material layer 19 is respectively as the capacitor 501
Bottom crown and top crown, first conductive material layer 16, high-K dielectric layer 18 and the second conductive material layer 19 form two-sided capacitance
Device structure.
Specifically, according to the design requirement of capacitor, different film layer structures can be used in the high-K dielectric layer 18.This reality
It applies in example, the high-K dielectric layer 18 includes zirconium oxide layer and alumina layer, wherein zirconium oxide and aluminium oxide are high K materials
Material.Certainly in other embodiments, the high-K dielectric layer can also use other hafniums, should not excessively limit this hair herein
Bright protection domain.
Further, as shown in figure 26, the manufacturing method of dynamic random access memory of the invention further includes continuation shape
At the schematic diagram of third conductive material layer 20.The third conductive material layer 20 is connected on the top crown of capacitor, as
The top electrode of capacitor.As an example, the material of the third conductive material layer 20 may include polysilicon or tungsten.Subsequently more wrap
The making of contact hole and the making of rear road wiring layer (BEOL) are included, this is well known to those skilled in the art, no longer superfluous herein
It states.
The manufacturing method of dynamic random access memory of the present invention can conveniently produce double sided capacitor structure, can be with
The capacitance that bigger is realized on identical memory cell area, improves the storage capacity of dynamic random access memory.
In conclusion in dynamic random access memory prepared by the present invention, layout structure is arranged by the four directions of contact bolt
It is transformed to the six sides arrangement of capacitor, the area of capacitor in storage unit can be improved, obtain the capacitance of bigger.The present invention
Dynamic random access memory realize capacitor six sides layout and memory cell area be 6F2While, ensure have
Source region, wordline, bit line are linear type, to realize more simple layout structure, advantageously reduce process complexity, improve
The stability of memory.The manufacturing method of the dynamic random access memory of the present invention can conveniently produce double sided capacitor knot
Structure can realize the capacitance of bigger on identical memory cell area, improve the storage energy of dynamic random access memory
Power.So the present invention effectively overcomes various shortcoming in the prior art and has high industrial utilization.
The above-described embodiments merely illustrate the principles and effects of the present invention, and is not intended to limit the present invention.It is any ripe
The personage for knowing this technology can all carry out modifications and changes to above-described embodiment without violating the spirit and scope of the present invention.Cause
This, institute is complete without departing from the spirit and technical ideas disclosed in the present invention by those of ordinary skill in the art such as
At all equivalent modifications or change, should by the present invention claim be covered.
Claims (15)
1. a kind of manufacturing method of dynamic random access memory, which is characterized in that include the following steps：
S1：Semiconductor structure is provided, the semiconductor structure includes substrate, positioned at the multi-layer film structure of the substrate top surface
And the contact pad positioned at the multi-layer film structure upper surface；
S2：The passivation layer of a covering contact pad is formed on the semiconductor structure；
S3：The first sacrificial layer, the first supporting layer, the second sacrificial layer and the second supporting layer are sequentially formed on the passivation layer；
S4：It is formed and runs through second supporting layer, the second sacrificial layer, the first supporting layer, the first sacrificial layer and the passivation up and down
Multiple through-holes of layer, each through-hole is located at the surface of a contact pad, and exposes the contact pad
Upper surface；
S5：The first conductive material layer is formed in the side wall of the through-hole and bottom；
S6：Multiple openings for running through second supporting layer up and down are formed, the opening exposes the one of second sacrificial layer
Part, and formed around the opening and be laid out while opening the opening；
S7：It is open as etching solution through window with described, wet etching removes second sacrificial layer around the through-hole；
S8：Part first supporting layer is removed, and wet etching removes first sacrificial layer around the through-hole；And
S9：The high-K dielectric layer for covering the first conductive material layer inner surface and outer surface is formed, and forms the covering high K
Second conductive material layer of dielectric layer outer surface；Wherein, first conductive material layer and the second conductive material layer respectively as
The bottom crown and top crown of capacitor, first conductive material layer, high-K dielectric layer and the second conductive material layer form two-sided electricity
Structure of container.
2. the manufacturing method of dynamic random access memory according to claim 1, it is characterised in that：Positioned at described first
Between the high-K dielectric layer of conductive material layer outer surface and the bottom and the contact pad of second conductive material layer by
The passivation layer isolation.
3. the manufacturing method of dynamic random access memory according to claim 1, it is characterised in that：Described first sacrifices
The material of layer or the second sacrificial layer includes silica or silane oxide；The passivation layer, the first supporting layer or the second supporting layer
Material include any one or any two or more combinations in silicon nitride, silicon oxynitride, aluminium oxide；The etching solution packet
Include hydrofluoric acid solution.
4. the manufacturing method of dynamic random access memory according to claim 1, it is characterised in that：Described first sacrifices
Layer and the second sacrificial layer in doped in boron or phosphorus one kind or combination.
5. the manufacturing method of dynamic random access memory according to claim 1, it is characterised in that：In step S6, one
A opening is overlapping with multiple through-holes simultaneously, and the through-hole only a fraction and the opening are overlapping.
6. the manufacturing method of dynamic random access memory according to claim 5, it is characterised in that：The opening is simultaneously
It is overlapping with 2~10 through-holes.
7. the manufacturing method of dynamic random access memory according to claim 1, it is characterised in that：In step S6, institute
It includes surrounding's cloth that there is identical opening shape and each opening to overlap mutually with 3 through-holes to state layout around opening
Office.
8. the manufacturing method of dynamic random access memory according to claim 1, which is characterized in that the semiconductor junction
Structure further includes：
Wordline array is located in the substrate, including a plurality of linear type wordline, these wordline are parallel with Y-direction, and along X
Direction equidistantly arranges, wherein X-direction is mutually perpendicular to Y-direction；
Digit line array is located in the multi-layer film structure, including a plurality of linear type bit line, these bit lines are parallel with X-direction, and
And it is equidistantly arranged along Y-direction；
Contact bolt array is located in the multi-layer film structure, including multiple contact bolts, wherein the figure of the wordline array with
The digit line array defines multiple independent rectangular areas on a substrate, and each contact bolt is respectively formed in described in one
In rectangular area, the contact bolt array is made to arrange in four directions；
Contact pad array, including multiple contact pads, each contact pad are all connected to above a contact bolt,
And pre-determined distance is deviated in the Y direction relative to the contact bolt；Wherein, adjacent two row contact pad offset direction on the contrary,
I.e. wherein a row contact pad is deviated along positive Y-direction, and in addition an adjacent column contact pad is deviated along Y-direction is born, and makes the contact
Pad array is arranged in six sides.
9. the manufacturing method of dynamic random access memory according to claim 8, it is characterised in that：Adjacent two bit lines
Spacing be D, each contact pad offset distance D/4 in the Y direction or in negative Y-direction both with respect to the contact bolt.
10. the manufacturing method of dynamic random access memory according to claim 8, it is characterised in that：Adjacent two words
The spacing of line is 2F, and the spacing of adjacent two bit lines is 3F, and F is minimum feature size.
11. the manufacturing method of dynamic random access memory according to claim 10, it is characterised in that：
The semiconductor structure further includes active area array, and the active area array includes that multiple linear types arranged in parallel are active
Area, the active area are tilted with X-direction in predetermined angle, and the projected length of the active area in the X direction is Lx, and meet 4F
<Lx<6F；
The center of the active area is arranged on bit line center line in X direction, and simultaneously in alignment between adjacent two wordline
Interval center line on；
For multiple active areas corresponding to same bit line, the center of two neighboring active area is at a distance of 4F in X direction；
For multiple active areas corresponding to not corresponding lines, the center of the two neighboring active area arranged side by side that misplaces is in the X direction
Projection interval be 2F, the center projection interval in the X direction of the two neighboring active area on same arrangement straight line is 6F.
12. the manufacturing method of dynamic random access memory according to claim 11, it is characterised in that：The preset angle
Degree is the active zone centerline and acute angle θ formed by X-direction, and meets 15 °<θ<35°.
13. the manufacturing method of dynamic random access memory according to claim 11, it is characterised in that：The bit line with
The intersection region of the active area is equipped with bit line contact portion, and the bit line is connected by bitline contact portion of institute and the active area
It connects.
14. the manufacturing method of dynamic random access memory according to claim 1, it is characterised in that：The Contact welding
In the contact bolt upper surface, equivalent deviates disk in same direction so that the contact pad is arranged in six sides；And it is described two-sided
Capacitor arrangement have it is identical with the contact pad be in six sides arrangement array of capacitors.
15. according to the manufacturing method of claim 1 to 14 any one of them dynamic random access memory, it is characterised in that：
Top electrode is connected on the top crown, the high-K dielectric layer includes zirconium oxide layer and alumina layer, and the bottom crown is at least
It is U-shaped there are one section, the corresponding section of the high-K dielectric layer and the top crown is M types.
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| CN112782558A (en) * | 2020-12-29 | 2021-05-11 | 中国电子产品可靠性与环境试验研究所（（工业和信息化部电子第五研究所）（中国赛宝实验室）） | Method for acquiring failure rate of integrated circuit |
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