CN108428691B - Contact plug and method for forming semiconductor device - Google Patents
Contact plug and method for forming semiconductor device Download PDFInfo
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- CN108428691B CN108428691B CN201810210995.2A CN201810210995A CN108428691B CN 108428691 B CN108428691 B CN 108428691B CN 201810210995 A CN201810210995 A CN 201810210995A CN 108428691 B CN108428691 B CN 108428691B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/535—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including internal interconnections, e.g. cross-under constructions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
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Abstract
According to the forming method of the contact plug and the semiconductor device, when the metal silicide blocking layer is formed, the first gap with larger size is formed on the bottom of the side wall of the protruding structure corresponding to the metal silicide blocking layer, so that the second gap with larger size can be correspondingly formed on the position of the first gap of the interlayer dielectric layer when the interlayer dielectric layer is filled subsequently, and the second gap is completely communicated with the contact hole. Therefore, residual gas or liquid and the like in the second gap can be effectively removed by combining the baking process, so that the second gap is emptied, the condition of forming a cavity is not existed in the filling process of the conductive material, the filling effect of the conductive material layer is favorably improved, the cavity is prevented from being formed in the finally formed contact plug, the semiconductor device is well contacted with the metal interconnection layer, and the normal work of the device is ensured.
Description
Technical Field
The present invention relates to the field of semiconductor manufacturing, and more particularly, to a method for forming a contact plug and a semiconductor device.
Background
In the fabrication process of an integrated circuit, in order to electrically extract elements such as a CMOS, a semiconductor device needs to be electrically connected to an upper metal interconnection line, and at present, a contact hole is formed in an Inter-Layer Dielectric (ILD) between the semiconductor device and the metal interconnection line, and a contact plug (contact) is formed by filling a conductive material such as tungsten, copper, or aluminum in the contact hole to achieve electrical connection.
However, when the contact plug is prepared by the prior art, the inventor of the present invention finds that voids are easily generated in the process of filling the conductive material, which seriously affects the connection performance between the formed contact plug and the element and the metal interconnection line, thereby causing the problem of failure of the whole semiconductor device.
Disclosure of Invention
The invention aims to provide a method for forming a contact plug, which solves the problem that the conventional forming method is easy to cause a void in the formed contact plug.
The invention provides a method for forming a contact plug, which comprises the following steps:
providing a substrate, wherein the substrate is provided with a protruding structure, and at least one side of the protruding structure is provided with a region to be led out;
forming a barrier material layer on the substrate, wherein the barrier material layer covers the side walls of the raised structures and extends to cover the surface of the substrate, so that the parts of the barrier material layer covering the side walls of the raised structures and the parts of the barrier material layer covering the surface of the substrate are connected with each other at the bottom of the raised structures;
forming a mask layer on the blocking material layer, wherein the mask layer covers the top of the protruding structure and exposes the region to be led out, and the side wall of the protruding structure is exposed in the direction parallel to the surface of the substrate;
performing an etching process on the blocking material layer to expose the region to be led out, and reserving a part of the blocking material layer covering the side wall of the protruding structure, wherein the etched blocking material layer forms a metal silicide blocking layer, and a first gap is generated in the part of the blocking material layer corresponding to the bottom of the protruding structure when the blocking material layer is etched;
forming an interlayer dielectric layer on the metal silicide barrier layer, wherein the interlayer dielectric layer covers the metal silicide barrier layer, a second gap is correspondingly formed in the position of the first gap on the interlayer dielectric layer, and a contact hole is also formed in the interlayer dielectric layer, is communicated with the second gap and exposes the region to be led out;
performing a baking process on the substrate;
and filling a conductive material into the contact hole to form the contact plug.
Optionally, the method for performing an etching process on the barrier material layer includes:
performing a dry etching process on the barrier material layer by taking the mask layer as a mask, and etching to a preset thickness to reserve part of the barrier material layer;
and removing the mask layer, performing a wet etching process on the barrier material layer, and removing all the barrier material layer on the region to be led out to expose the region to be led out so as to form the silicide barrier layer.
Optionally, the etching time of the wet etching process is prolonged to increase the size of the first gap and correspondingly increase the size of the second gap until the second gap is completely communicated with the contact hole.
Optionally, the interlayer dielectric layer is formed by using a high-density plasma chemical vapor deposition process.
Optionally, after forming the metal silicide blocking layer and before forming the interlayer dielectric layer, a metal silicide layer is formed on the region to be led out.
Optionally, the material of the metal silicide blocking layer is silicon dioxide.
Optionally, the interlayer dielectric layer is a laminated structure of a silicon nitride layer and a silicon glass layer.
Optionally, the material of the contact plug includes tungsten, aluminum, or copper.
The invention also provides a method for forming a semiconductor device, which adopts the method for forming the contact plug.
The invention provides a contact plug and a method for forming a semiconductor device, which analyze the reason that a conductive material filled in the contact plug has a cavity, and when a metal silicide blocking layer is formed, a first gap with larger size is formed on the bottom of the side wall of a protruding structure corresponding to the metal silicide blocking layer, so that a second gap with larger size can be correspondingly formed on the position of the first gap of an interlayer dielectric layer when the interlayer dielectric layer is filled subsequently, and the second gap is completely communicated with a contact hole. Therefore, in combination with the baking process, residual gas or liquid and the like in the second gap can be effectively removed (for example, when the interlayer dielectric layer is patterned, residual reagents and the like when residues such as photoresist and the like are further removed), so that the second gap is emptied, the condition of forming a cavity is not provided in the filling process of the conductive material, the filling effect of the conductive material layer is favorably improved, the cavity is prevented from being formed in the finally formed contact plug, the semiconductor device is well contacted with the metal interconnection layer, and the normal work of the device is ensured.
Drawings
FIG. 1 is a topographical view of a contact plug formed using the prior art;
FIG. 2 is a topographical view of a contact plug formed using the prior art;
FIG. 3 is a flow chart illustrating a method for forming a contact plug according to the present invention;
fig. 4 to 6 are schematic structural views illustrating a method for forming a contact plug according to an embodiment of the invention.
Detailed Description
The inventor of the present invention finds that the semiconductor device manufactured by the conventional contact plug forming method has a problem of functional failure. Specifically, the inventors found that the storage state of a part of flash memory units is not restored to the state that the part of flash memory units should be in (i.e. the storage bits in the flash memory units still keep low potential after being erased but are not restored to high potential) after the flash memory units are experimentally erased in the process of manufacturing a flash memory device, and further, the inventors performed physical failure analysis on the flash memory units with problems.
Fig. 1 is a topography of a contact plug formed by using the prior art, and referring to fig. 1, it is easy to see that the uniformity of a filling material in the right-side contact plug is very poor, and the filling material contains more voids, so that a semiconductor device is in poor contact with an upper metal interconnection line, and the electrical connection cannot meet the requirement. On the basis of this, the inventors of the present invention further investigated the cause of the void generated in the filling material in the contact plug.
Fig. 2 is a partial topography of a contact plug formed by using the prior art, and referring to fig. 2, after the inventors carefully observe the topography of the contact plug and its surrounding structures, it is found that there is a hole (circled area in fig. 2) in the interlayer dielectric layer near the bottom of the contact plug, which may cause communication with the contact hole. The inventors thereupon made an idea that the main cause of formation of voids in the contact plugs is considered to be related to the voids. Further, in combination with the prior art contact plug formation method, the inventors provide an explanation of hole-induced contact plug voiding. Firstly, the formation of the hole is caused by a wet etching process of the metal silicide barrier layer, and the wet etching is an isotropic etching method, so that certain over-etching is inevitably generated when the bottom of the barrier material layer is etched, so that the side wall close to the bottom is also etched to a certain degree, a groove (namely a first gap) is formed at the bottom, and an interlayer dielectric layer formed subsequently cannot be well attached to and filled in the groove, so that the formation of the hole (namely a second gap) is caused; secondly, in the forming process of the contact hole, namely the etching process of the interlayer dielectric layer, the hole is easily communicated with the contact hole, and then in the process of removing the photoresist, reagents such as photoresist removing liquid and the like flow into the hole; finally, when the contact hole is filled with a conductive material (usually, a metal material such as tungsten, aluminum or copper is filled), due to the high reaction temperature, reagents such as a degumming solution and the like remaining in the hole are heated and volatilized, gas is released and discharged into the contact hole, and then the filling effect of the conductive material in the contact hole is seriously affected.
Based on the above analysis, to solve the problem of voids in the contact plug, methods such as eliminating the voids, preventing the voids from communicating with the contact hole, and removing the residual reagents in the voids can be adopted, and generally speaking, the key dimension size when the contact hole is formed can be controlled, and the alignment of the overlay can be controlled, so that the contact hole is far away from the voids, and the formation rate of the interlayer dielectric layer can be increased, so as to obtain a better coverage effect and reduce the size of the voids. Based on the above, the inventors of the present invention have creatively devised a more reliable solution.
The following describes a method for forming a contact plug and a semiconductor device according to the present invention in further detail with reference to the accompanying drawings and embodiments. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
Fig. 3 is a schematic flow chart of a method for forming a contact plug according to the present invention, and fig. 4 to 6 are schematic structural views of a method for forming a contact plug according to an embodiment of the present invention, which are described below with reference to fig. 3 to 6.
In step S1, providing a substrate 1, where the substrate 1 has a protruding structure 2 thereon, and a region to be led out (not shown) is disposed on at least one side of the protruding structure 2;
specifically, referring to fig. 4, the substrate 1 is made of a semiconductor material such as silicon or silicon germanium, the protruding structure 2 may be a gate structure, and the region to be led out may be a source region or a drain region. It is understood by those skilled in the art that the formation of the contact plug in the present embodiment is not limited to the mos device, but the contact plug with the similar structure can be formed by applying the method of the present invention, and the purpose of forming the contact plug is to achieve the electrical connection between the region to be led out in the semiconductor device and the metal interconnection layer formed above the device in the subsequent process.
In step S2, forming a barrier material layer 300 on the substrate, wherein the barrier material layer 300 covers the sidewalls of the protruding structures 2 and extends to cover the surface of the substrate 1, so that the portions of the barrier material layer 300 covering the sidewalls of the protruding structures 2 and the portions of the barrier material layer 300 covering the surface of the substrate 1 are connected to each other at the bottom of the protruding structures 2;
in this embodiment, referring to fig. 4, the formation of the blocking material layer 300 is to protect regions where metal silicide is not required to be formed during the formation of the subsequent metal silicide layer, so as to prevent the metal silicide reaction from occurring in these regions, and the metal silicide blocking layer formed after the etching of the blocking material layer 300 can also play an alignment role during the formation of the subsequent metal silicide layer.
In step S3, a mask layer (not shown) is formed on the blocking material layer 300, the mask layer covers the top of the protruding structure and exposes the region to be led out, and the sidewall of the protruding structure is exposed in a direction parallel to the substrate surface;
specifically, the mask layer may be, for example, a photoresist layer. The mask layer is used as a mask for etching the barrier material layer in the next step to define a region to be contacted with the lead-out region later.
In step S4, performing an etching process on the blocking material layer 300 to expose the region to be led out, and leaving a portion of the blocking material layer 300 covering the sidewall of the protruding structure, where the etched blocking material layer forms a metal silicide blocking layer 301, and when the blocking material layer is etched, a first void 4 is generated in a portion of the blocking material layer corresponding to the bottom of the protruding structure 2;
as a preferable scheme, the method for performing the etching process on the barrier material layer 300 includes:
a first step of performing a dry etching process on the barrier material layer 300 by using the mask layer as a mask, and etching to a predetermined thickness to retain a part of the barrier material layer;
specifically, the dry Etching process performed on the barrier material layer 300 may employ a method such as Plasma Etching (PE).
And a second step of removing the mask layer and performing a wet etching process on the barrier material layer 300 to remove all the barrier material layer on the region to be led out so as to expose the region to be led out and form the metal silicide barrier layer 301.
Specifically, in the wet etching process, the adopted chemical etchant is, for example, diluted hydrofluoric acid. Since the wet etching is isotropic etching, the etching rate in each direction is uniform, and in order to ensure that the barrier material layer at the bottom is removed by etching, more etching is easily generated at the portion of the barrier material layer 300 close to the bottom of the protruding structure, thereby forming the first gap 4.
Preferably, after the metal silicide blocking layer 301 is formed and before the interlayer dielectric layer is formed, a metal silicide layer 5 is formed on the region to be led out.
Specifically, referring to fig. 5, the metal silicide layer 5 may be a metal silicide such as titanium silicide, cobalt silicide, or nickel silicide, for example. The silicide layer 5 can function to reduce the hole resistance of the contact hole and the contact resistance of the contact hole electrically connected to a region (e.g., a source region or a drain region) of the semiconductor device to be led out.
In step S5, forming an interlayer dielectric layer 6 on the metal silicide blocking layer 301, where the interlayer dielectric layer 6 covers the metal silicide blocking layer 301, and the interlayer dielectric layer 6 is correspondingly formed with a second gap 7 at the position of the first gap 4, and a contact hole is further formed in the interlayer dielectric layer 6, the contact hole is communicated with the second gap 7 and exposes the region to be led out;
preferably, the interlayer dielectric layer 6 is a stacked structure of a silicon nitride layer 601 and an undoped silicon glass layer 602. The forming method of the interlayer dielectric layer 6 comprises high-density plasma chemical vapor deposition (HDPCVD).
Specifically, referring to fig. 6, the interlayer dielectric layer 6 is an electrical insulating layer for isolating the semiconductor device from the metal interconnection layer. In this embodiment, the interlayer dielectric layer 6 is a stacked structure of a silicon nitride layer 601 and an Undoped Silicate Glass (USG)602, and it can be understood by those skilled in the art that the interlayer dielectric layer 6 in this embodiment is only an exemplary one, and the material of the interlayer dielectric layer 6 may also be silicon oxide, boron-phosphorus-silicate glass (BPSG), phosphosilicate glass (PSG), a high polymer material, a low-k material, and the like. And, High Density Plasma Chemical Vapor Deposition (HDPCVD) has a greater ability to fill high aspect ratio trenches than other chemical vapor deposition methods such as Low Pressure Chemical Vapor Deposition (LPCVD) and Plasma Enhanced Chemical Vapor Deposition (PECVD). However, the filling capability refers to the overall filling of the trench, in which process the second voids 7 are still inevitably formed when filling the first voids 4. In addition, the formation of the contact hole may adopt a dry etching process, which is not described in detail herein.
It can be understood that, in the formation process of the contact hole, a second mask layer (not shown, for example, a photoresist layer in this embodiment) needs to be formed on the interlayer dielectric layer 6, and the contact hole is etched by using the second mask layer as a mask. And after the contact hole is formed, the step of removing the second mask layer is also included, when the photoresist is removed, reagents such as photoresist removing liquid corresponding to the photoresist are needed, and in the photoresist removing process, the reagents are likely to enter the second gap, and the reagents remained in the second gap are difficult to directly remove.
In step S6, a baking process is performed on the substrate;
preferably, the etching time of the wet etching process is prolonged to increase the size of the first gap 4 and correspondingly increase the size of the second gap 7 until the second gap 7 is completely communicated with the contact hole.
In this embodiment, a baking process is performed on the substrate to volatilize the residual reagent in the contact hole and the residual reagent in the second gap 7, thereby fundamentally avoiding the condition of generating a void when the subsequent contact hole is filled with a conductive material.
It should be noted that the inventors have initially added the baking process directly to the substrate and indeed have been able to act to accelerate the evaporation of the residual reagent in the contact hole and in the second void 7. However, the inventors have found that there is a special case that the second gap 7 may not be completely connected to the contact hole due to the overlay alignment deviation and the filling rate of the interlayer dielectric layer 6, that is, there is not a complete channel but a plurality of intermittent small channels between the second gap 7 and the contact hole, so that the connection between the second gap 7 and the contact hole is in a state of lotus broken filament, which makes the reagent more easily enter the second gap 7, but it is difficult to completely volatilize the reagent in the second gap 7 when the baking process is performed.
Further, the inventors have creatively proposed an idea of further increasing the second gap 7. In general, the increase of the second gap 7 will only cause the void phenomenon in the contact plug to be further deteriorated, however, in this embodiment, the inventor proposes to extend the wet etching time of the barrier material layer to increase the second gap 7, so as to ensure that the second gap 7 is completely communicated with the contact hole, which is also easy to implement in terms of process. Further, when the baking process is performed, the reagent remaining in the second gap 7 can be completely removed, and thus the condition of generating a void in the contact plug is fundamentally eliminated.
Specifically, referring to fig. 6, in an embodiment, the etching time of the originally adopted wet etching is, for example, 300s, and after a plurality of experiments, the inventor finds that, after increasing the etching time of the wet etching to, for example, 345s or more, the second gap 7 can be ensured to be completely communicated with the contact hole, and then adds a baking process on the basis, so that the residual reagent in the second gap 7 can be effectively removed. In fact, in order to verify the feasibility of the solution, the inventor also cleaned the substrate after the contact hole is formed and before the contact plug is formed (the cleaning agent further fills the second void 7, which worsens the void condition), and the number of component failures occurred in the semiconductor device obtained by the solution is significantly reduced compared with the prior art, thereby also proving the effectiveness and feasibility of increasing the second void 7 for eliminating the contact plug void.
In step S7, the contact hole is filled with a conductive material to form the contact plug 8.
Preferably, the material of the contact plug 8 includes tungsten, aluminum or copper; and a metal diffusion barrier layer (not shown) is also formed in the contact hole before the contact plug 8 is formed and after the contact hole is formed.
Specifically, the metal diffusion barrier layer is, for example, a Ti/TiN film layer, which can prevent the filled conductive material from diffusing and entering the interlayer dielectric layer or even the substrate, and can form a good contact with the silicide layer at the bottom of the contact hole, and improve the adhesion effect of the filled conductive material; in this embodiment, the contact plug 8 is, for example, tungsten, and those skilled in the art may select a conductive material such as aluminum or copper according to the requirement, which is not limited herein. Since the residual reagent in the second gap 7 is eliminated after the baking process, the void problem of the contact plug 8 caused by the residual reagent in the second gap 7 is fundamentally avoided.
In addition, the embodiment also provides a method for forming a semiconductor device, and the method for forming the contact plug is adopted, so that the normal function of the semiconductor device can be ensured, and the yield of the prepared semiconductor device is improved.
In summary, the method for forming a contact plug and a semiconductor device provided by the present invention analyzes the cause of the occurrence of voids in the conductive material filled in the contact plug, and forms a first void with a larger size on the bottom of the side wall of the protruding structure corresponding to the metal silicide blocking layer when forming the metal silicide blocking layer, so that a second void with a larger size can be correspondingly formed on the position of the first void of the interlayer dielectric layer when subsequently filling the interlayer dielectric layer, and the second void is completely communicated with the contact hole. Therefore, by combining with the baking process, residual gas or liquid and the like in the second gap can be effectively removed (for example, when the interlayer dielectric layer is patterned, residual reagents and the like when residues such as photoresist and the like are removed), so that the second gap is emptied, the condition of forming a cavity is not existed in the filling process of the conductive material, the filling effect of the conductive material layer is favorably improved, the cavity is prevented from being formed in the finally formed contact plug, the semiconductor device is well contacted with the metal interconnection layer, and the normal work of the device is ensured.
It will be apparent to those skilled in the art that various changes and modifications may be made in the invention without departing from the spirit and scope of the invention. Thus, it is intended that these modifications and variations of the present invention be covered by the present invention.
Claims (9)
1. A method for forming a contact plug includes providing a substrate having a protrusion structure thereon, and providing a region to be led out on at least one side of the protrusion structure, the method further includes:
forming a barrier material layer on the substrate, wherein the barrier material layer covers the side walls of the raised structures and extends to cover the surface of the substrate, so that the parts of the barrier material layer covering the side walls of the raised structures and the parts of the barrier material layer covering the surface of the substrate are connected with each other at the bottom of the raised structures;
forming a mask layer on the blocking material layer, wherein the mask layer covers the top of the protruding structure and exposes the region to be led out, and the side wall of the protruding structure is exposed in the direction parallel to the surface of the substrate;
performing an etching process on the blocking material layer to expose the region to be led out, and reserving a part of the blocking material layer covering the side wall of the protruding structure, wherein the etched blocking material layer forms a metal silicide blocking layer, and a first gap is generated in the part of the blocking material layer corresponding to the bottom of the protruding structure when the blocking material layer is etched;
forming an interlayer dielectric layer on the metal silicide barrier layer, wherein the interlayer dielectric layer covers the metal silicide barrier layer, a second gap is correspondingly formed in the position of the first gap on the interlayer dielectric layer, and a contact hole is also formed in the interlayer dielectric layer, is communicated with the second gap and exposes the region to be led out;
performing a baking process on the substrate;
and filling a conductive material into the contact hole to form the contact plug.
2. The method for forming a contact plug according to claim 1, wherein the method for performing an etching process on the barrier material layer comprises:
performing a dry etching process on the barrier material layer by taking the mask layer as a mask, and etching to a preset thickness to reserve part of the barrier material layer;
and removing the mask layer, performing a wet etching process on the barrier material layer, and removing all the barrier material layer on the region to be led out to expose the region to be led out so as to form the silicide barrier layer.
3. The method of forming a contact plug according to claim 2, wherein an etching time of the wet etching process is extended to increase a size of the first void and correspondingly increase a size of the second void until the second void is completely communicated with the contact hole.
4. The method for forming a contact plug according to claim 1, wherein the interlayer dielectric layer is formed by a high density plasma chemical vapor deposition process.
5. The method for forming a contact plug according to claim 1, wherein a metal silicide layer is formed on the region to be led out after the formation of the metal silicide blocking layer and before the formation of the interlayer dielectric layer.
6. The method for forming a contact plug according to claim 1, wherein a material of the metal silicide blocking layer is silicon dioxide.
7. The method for forming a contact plug according to claim 1, wherein the interlayer dielectric layer has a stacked structure of a silicon nitride layer and a silicon glass layer.
8. The method for forming a contact plug according to claim 1, wherein a material of the contact plug comprises tungsten, aluminum, or copper.
9. A method for forming a semiconductor device, using the method for forming a contact plug according to any one of claims 1 to 8.
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| CN1716549A (en) * | 2004-05-25 | 2006-01-04 | 三星电子株式会社 | In contact hole, form the method for metal-nitride layers and the layer that so forms |
| CN102148202A (en) * | 2010-02-09 | 2011-08-10 | 精材科技股份有限公司 | Chip package and method for forming the same |
| CN104025262A (en) * | 2011-12-29 | 2014-09-03 | 英特尔公司 | Airgap interconnect with hood layer and method of forming |
| WO2016195672A1 (en) * | 2015-06-03 | 2016-12-08 | Intel Corporation | The use of noble metals in the formation of conductive connectors |
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