CN108427465A - A kind of reference circuit of ultra low temperature and voltage coefficient - Google Patents
A kind of reference circuit of ultra low temperature and voltage coefficient Download PDFInfo
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- CN108427465A CN108427465A CN201810296249.XA CN201810296249A CN108427465A CN 108427465 A CN108427465 A CN 108427465A CN 201810296249 A CN201810296249 A CN 201810296249A CN 108427465 A CN108427465 A CN 108427465A
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- pmos tube
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- nmos tube
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
- G05F1/565—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor
- G05F1/567—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor for temperature compensation
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- Control Of Electrical Variables (AREA)
Abstract
The present invention provides the reference circuit of a kind of ultra low temperature and voltage coefficient, including it is sequentially connected：Biasing circuit, band gap core module and temperature second order compensation module.The advantages of circuit of the present invention is simple and effective, and the area of cloth domain is small, at low cost, and the device count used is achieved that low-temperature coefficient, low voltage coefficient less, while without start-up circuit, quickly starting, the synthesis aspect such as high PSRR.
Description
Technical field
The present invention relates to electronic circuit technology fields, and in particular, to a kind of benchmark electricity of ultra low temperature and voltage coefficient
Road.
Background technology
In current most analog ICs, voltage reference module is required for provide the reference voltage to entire chip.Have each
Kind technology can construct reference voltage, for example with metal-oxide-semiconductor and enhanced metal-oxide-semiconductor composition reference circuit is exhausted, more be widely
Using band-gap reference circuit (Band-gap Reference), because band-gap reference circuit is not necessarily to special technique level
It realizes.In the application having, these indexs of the precision and temperature and voltage coefficient of this reference voltage be all it is vital,
Such as in high-precision ADC (Analog to Digital Converter, analog-digital converter).
Chinese patent CN201310313883.7 disclose a kind of high power supply inhibit, low process deviation bandgap voltage reference
Invention, the circuit include band gap reference core circuit, pre-regulating circuit, adaptive process adjusting circuit, biasing circuit and startup
Circuit.The circuit utilizes natural bandgap structure, realizes the first compensation phase of positive temperature coefficient part and negative temperature part, but still
Two head-down temperatures coefficient so also having.
Chinese patent CN201310301002.X discloses a kind of invention of the bandgap voltage reference with curvature compensation, leads to
Cross curvature compensation circuit generate high-order temperature characterisitic electric current, to existing single order temperature-compensation circuit generate with single order temperature without
The electric current of pass compensates, and can effectively improve the accuracy of compensation electric current, reduces the temperature drift system of output reference voltage
Number.Since the supply voltage of circuit directly acts on band gap nuclear structure so that the reference voltage of the invention has larger voltage
Coefficient.
Invention content
For the defects in the prior art, the object of the present invention is to provide a kind of benchmark of ultra low temperature and voltage coefficient electricity
Road.
According to a kind of reference circuit of ultra low temperature and voltage coefficient provided by the invention, including it is sequentially connected：Biasing
Circuit 101, band gap core module 102 and temperature second order compensation module 103；
The band gap core module 102 includes：The current source for the cascode that PMOS tube M118 and PMOS tube M119 are formed,
The drain electrode parallel resistance R120 and resistance R121 of PMOS tube M119, flow through resistance R120 and resistance R121 electric current it is equal or at than
Example, NPN pipe Y122 and NPN pipes Y123 generate the difference and absolute temperature is proportional to of the formation of different Vbe, are applied to resistance
R124, resistance R125 and resistance R126 are serially connected in the emitter of NPN pipes Y123, obtain with positive temperature coefficient voltage, with negative temperature
Coefficient Vbe phases compensate；
Keep the collector potential of NPN pipe Y122 and NPN pipes Y123 equal by an error operational amplifier, NPN pipes Y127 and NPN
The base stage of pipe Y128 is separately connected the collector of NPN pipe Y122 and NPN pipes Y123, forms the input pipe of error operational amplifier, NMOS tube
M129 and NMOS tube M130 is connected to the emitter of NPN pipe Y127 and NPN pipes Y128, forms the tail current source of error operational amplifier；
The current mirror of PMOS tube M131, PMOS tube M132, PMOS tube M133 and PMOS tube M134 compositions cascode, NMOS
The current mirror of pipe M135, NMOS tube M136, NMOS tube M137 and NMOS tube M138 compositions cascode, structure is followed with source electrode
PMOS tube M141 collectively constitutes feedback control loop；
The collector of the grid connection NPN pipe Y122 and NPN pipes Y123 of NMOS tube M142, resistance R143, resistance R144 and
Resistance R145 is sequentially connected in series the output stage that the band gap core module 102 is collectively formed in NMOS tube M142 source electrodes, PMOS tube M146
The drain electrode that NMOS tube M142 is connected with PMOS147 generates the biasing of temperature second order compensation module 103.
Preferably, the feedback control loop includes the loop compensation being made of resistance R139 and capacitance C140.
Preferably, the biasing circuit 101 includes：Bias current inputs 104 and bias current inputs 105, two poles
The PMOS tube M106 of pipe connection is connected into the gate bias for generating PMOS cascode, PMOS tube M107 and PMOS tube M108 compositions the
2 tunnels bias, and generate the gate bias for the PMOS for connecing power supply, PMOS tube M109 and PMOS tube M110 generate NMOS tube M113's jointly
Biasing, the NMOS tube M113 of diode-connected generate the gate bias of NMOS tube cascode, PMOS tube M111 and PMOS tube M112
Bias current is provided, NMOS tube M115 and NMOS tube M114 is flowed into, generates the gate bias of the NMOS tube of ground terminal.
Preferably, the temperature second order compensation module 103 includes：
PMOS tube M149, PMOS tube M150, PMOS tube M153 and PMOS tube M154 composition high temperature compensation electric currents and PMOS
The low temp compensating electric current of pipe M151, PMOS tube M152, PMOS tube M155 and PMOS tube M156 composition, two stocks are not in high temperature and low
The compensation electric current of temperature to work flows on resistance R126, is respectively formed high temperature and compensation that low temperature profile has a downwarp.
Preferably, the band gap core module 102 further includes NMOS tube M157, the drain electrode of NMOS tube M157 connects NMOS tube
The source electrode of M137, grid connect the grid of NPN pipe Y122 and NPN pipes Y123.
Compared with prior art, the present invention has following advantageous effect：
Circuit of the present invention is simple and effective, and the area of cloth domain is small, at low cost, and the device count used is achieved that low temperature less
The advantages of coefficient, low voltage coefficient, while without start-up circuit, quickly starting, the comprehensive aspect such as high PSRR.
Description of the drawings
Upon reading the detailed description of non-limiting embodiments with reference to the following drawings, other feature of the invention,
Objects and advantages will become more apparent upon：
Fig. 1 is the circuit diagram of the present invention；
Fig. 2 is the circuit temperature coefficient oscillogram of the present invention；
Fig. 3 is the circuit voltage coefficient oscillogram of the present invention.
Specific implementation mode
With reference to specific embodiment, the present invention is described in detail.Following embodiment will be helpful to the technology of this field
Personnel further understand the present invention, but the invention is not limited in any way.It should be pointed out that the ordinary skill of this field
For personnel, without departing from the inventive concept of the premise, several changes and improvements can also be made.These belong to the present invention
Protection domain.
As shown in Figure 1, the reference circuit of a kind of ultra low temperature and voltage coefficient provided by the invention, including be sequentially connected
's：Biasing circuit 101, band gap core module 102 and temperature second order compensation module 103, power supply 117, ground 116.
Biasing circuit 101 includes：Bias current inputs 104 and bias current inputs 105 input 2 bias currents
I1 and I2, the PMOS tube M106 of diode-connected are connected into the gate bias for generating PMOS cascode, PMOS tube M107 and PMOS
Pipe M108 forms the biasing of the 2nd tunnel, generates the gate bias for the PMOS for connecing power supply, PMOS tube M109 and PMOS tube M110 are generated jointly
The biasing of NMOS tube M113, the NMOS tube M113 of diode-connected generate the gate bias of NMOS tube Mcascode, PMOS tube
M111 and PMOS tube M112 provide bias current, flow into NMOS tube M115 and NMOS tube M114, generate the NMOS tube of ground terminal
Gate bias.
Band gap core module 102 includes：The current source for the cascode that PMOS tube M118 and PMOS tube M119 are formed, passes through
The structure of cascode reduces the electric current to the sensibility of supply voltage, reduces voltage coefficient.The drain electrode of PMOS tube M119
Parallel resistance R120 and resistance R121, the electric current for flowing through resistance R120 and resistance R121 is equal or proportional, NPN pipes Y122 and
The collector of NPN pipes Y123 is separately connected resistance R120 and is connected with resistance R121 and base stage, NPN pipe Y122 and NPN pipes Y1233
Working current density it is different, to generate the difference and absolute temperature is proportional to of the formation of different Vbe, be applied to resistance R124,
Resistance R125 and resistance R126 is serially connected in the emitter of NPN pipes Y123, obtains the electricity compensated with positive temperature coefficient voltage Vbe phases
Pressure.Resistance R120 and resistance R121 is usually equal 2 resistance R, for generating 2 strands of equal electric currents but it is also possible to be one
A resistance R at other ratios, so this 2 resistance R require matched design on domain.Output end 148 export Vbg be
The sum of the Vbe and this positive temperature characterisitic voltage of NPN pipes Y123, which achieves the first compensation phases of temperature.It in addition can be to electricity
Resistance R126 carries out the voltage output that Trim corrects entire band-gap reference.
In order to enable the electric current for flowing through resistance R120 and resistance R121 is equal or proportional, NPN pipes Y122 and NPN are needed
The voltage of the collector of pipe Y123 is equal.Make the collector potential phase of NPN pipe Y122 and NPN pipes Y123 by an error operational amplifier
Base stage Deng, NPN pipe Y127 and NPN pipes Y128 is separately connected the collector of NPN pipe Y122 and NPN pipes Y123, composition error fortune
The input pipe put, NMOS tube M129 and NMOS tube M130 are connected to the emitter of NPN pipe Y127 and NPN pipes Y128, form error
The tail current source of amplifier.
The current mirror of PMOS tube M131, PMOS tube M132, PMOS tube M133 and PMOS tube M134 compositions cascode, NMOS
The current mirror of pipe M135, NMOS tube M136, NMOS tube M137 and NMOS tube M138 compositions cascode, structure is followed with source electrode
PMOS tube M141 collectively constitutes feedback control loop；The loop compensation of resistance R139 and capacitance C140 compositions, this compensation form one
A dominant pole and a zero, obtain good phase margin.
The collector of the grid connection NPN pipe Y122 and NPN pipes Y123 of NMOS tube M142, resistance R143, resistance R144 and
Resistance R145 is sequentially connected in series the output stage that band gap core module 102 is collectively formed in NMOS tube M142 source electrodes, using NMOS tube M142
As output stage, the power supply rejection ratio of benchmark is increased.The drain electrode that PMOS tube M146 connects NMOS tube M142 with PMOS147 generates
The biasing of temperature second order compensation module 103.
Temperature second order compensation module 103 includes：PMOS tube M149, PMOS tube M150, PMOS tube M153 and PMOS tube M154
Form the low temperature benefit of high temperature compensation electric current and PMOS tube M151, PMOS tube M152, PMOS tube M155 and PMOS tube M156 compositions
Electric current is repaid, two stocks are not flowed in the compensation electric current of high temperature and low temperature to work on resistance R126, are respectively formed high temperature and low
The compensation that warm temperature curve has a downwarp.So that amplitude of variation very little of the temperature curve of entire voltage reference in total temperature range.
Band gap core module 102 further includes NMOS tube M157, the source electrode of the drain electrode connection NMOS tube M137 of NMOS tube M157, grid
Pole connects the grid of NPN pipe Y122 and NPN pipes Y123.NMOS tube M157 is to accelerate this band-gap reference from standby to normal work
Process.The grid of PMOS tube M141 is low when standby.Once opening work, need to charge to capacitance C140.Pass through NMOS
Pipe M157 cuts off current branch so that all electric currents all give capacitance C140 chargings on startup, accelerate the foundation of band-gap reference
Speed.
Fig. 2 is the temperature coefficient oscillogram of circuit work of the present invention.It can be seen from the figure that respectively in high temperature and low temperature
When, temperature curve is all ascendant trend by downward trend torsion so that electricity in the range of -40 degrees Celsius~120 degrees Celsius entire
Pressure, which has only changed, is less than 500uV.
Fig. 3 is the voltage coefficient oscillogram of circuit work of the present invention.It can be seen from the figure that temperature is -45, -25,0,
25, under 50,85,100,125 and 145 degrees Celsius of 9 states, from operating voltage 2.8V~5.0V, the output of band-gap reference is only
181.6uV is changed.
Specific embodiments of the present invention are described above.It is to be appreciated that the invention is not limited in above-mentioned
Particular implementation, those skilled in the art can make a variety of changes or change within the scope of the claims, this not shadow
Ring the substantive content of the present invention.In the absence of conflict, the feature in embodiments herein and embodiment can arbitrary phase
Mutually combination.
Claims (5)
1. the reference circuit of a kind of ultra low temperature and voltage coefficient, which is characterized in that including sequentially connected：Biasing circuit
(101), band gap core module (102) and temperature second order compensation module (103)；
The band gap core module (102) includes：The current source for the cascode that PMOS tube M118 and PMOS tube M119 are formed, PMOS
The drain electrode parallel resistance R120 and resistance R121 of pipe M119, the electric current for flowing through resistance R120 and resistance R121 is equal or proportional,
NPN pipes Y122 is separately connected resistance R120 with the collector of NPN pipes Y123 and is connected with resistance R121 and base stage, NPN pipes Y122
The difference and absolute temperature is proportional to that the formation of different Vbe is generated with NPN pipes Y123, are applied to resistance R124, resistance R125 and
Resistance R126 is serially connected in the emitter of NPN pipes Y123, obtain with positive temperature coefficient voltage, compensated with negative temperature coefficient Vbe phases；
Keep the collector potential of NPN pipe Y122 and NPN pipes Y123 equal by an error operational amplifier, NPN pipes Y127 and NPN pipe
The base stage of Y128 is separately connected the collector of NPN pipe Y122 and NPN pipes Y123, forms the input pipe of error operational amplifier, NMOS tube
M129 and NMOS tube M130 is connected to the emitter of NPN pipe Y127 and NPN pipes Y128, forms the tail current source of error operational amplifier；
The current mirror of PMOS tube M131, PMOS tube M132, PMOS tube M133 and PMOS tube M134 compositions cascode, NMOS tube
The current mirror of M135, NMOS tube M136, NMOS tube M137 and NMOS tube M138 compositions cascode, structure is followed with source electrode
PMOS tube M141 collectively constitutes feedback control loop；
The collector of the grid connection NPN pipe Y122 and NPN pipes Y123 of NMOS tube M142, resistance R143, resistance R144 and resistance
R145 is sequentially connected in series the output stage that the band gap core module 102 is collectively formed in NMOS tube M142 source electrodes, PMOS tube M146 and
The drain electrode of PMOSM147 connection NMOS tubes M142 generates the biasing of temperature second order compensation module 103.
2. the reference circuit of ultra low temperature according to claim 1 and voltage coefficient, which is characterized in that the feedback control loop
It include the loop compensation being made of resistance R139 and capacitance C140.
3. the reference circuit of ultra low temperature according to claim 1 and voltage coefficient, which is characterized in that the biasing circuit
101 include：The PMOS tube M106 of bias current inputs 104 and bias current inputs 105, diode-connected is connected into generation
The gate bias of PMOS cascode, PMOS tube M107 and PMOS tube M108 form the biasing of the 2nd tunnel, generate the PMOS's for connecing power supply
Gate bias, PMOS tube M109 and PMOS tube M110 generate the biasing of NMOS tube M113, the NMOS tube of diode-connected jointly
M113 generates the gate bias of NMOS tube cascode, and PMOS tube M111 and PMOS tube M112 provide bias current, flow into NMOS tube
M115 and NMOS tube M114, generates the gate bias of the NMOS tube of ground terminal.
4. the reference circuit of ultra low temperature according to claim 1 and voltage coefficient, which is characterized in that the temperature second order
Compensating module (103) includes：
PMOS tube M149, PMOS tube M150, PMOS tube M153 and PMOS tube M154 composition high temperature compensation electric currents and PMOS tube
The low temp compensating electric current of M151, PMOS tube M152, PMOS tube M155 and PMOS tube M156 compositions, two stocks are not in high temperature and low temperature
The compensation electric current to work flow on resistance R126, be respectively formed high temperature and compensation that low temperature profile has a downwarp.
5. the reference circuit of ultra low temperature according to claim 1 and voltage coefficient, which is characterized in that the band gap core mould
Block (102) further includes NMOS tube M157, the source electrode of the drain electrode connection NMOS tube M137 of NMOS tube M157, grid connection NPN pipes
The grid of Y122 and NPN pipes Y123.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810296249.XA CN108427465B (en) | 2018-04-04 | 2018-04-04 | Reference circuit with ultralow temperature and voltage coefficient |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810296249.XA CN108427465B (en) | 2018-04-04 | 2018-04-04 | Reference circuit with ultralow temperature and voltage coefficient |
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| CN108427465A true CN108427465A (en) | 2018-08-21 |
| CN108427465B CN108427465B (en) | 2019-12-06 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110377091A (en) * | 2019-08-16 | 2019-10-25 | 电子科技大学 | A kind of high-order compensation band gap a reference source |
| CN116301169A (en) * | 2023-05-23 | 2023-06-23 | 芯动微电子科技(珠海)有限公司 | Bias circuit and comparator |
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| US6215291B1 (en) * | 1999-01-21 | 2001-04-10 | National Semiconductor Incorporated | Reference voltage circuit |
| US20070030050A1 (en) * | 2005-08-08 | 2007-02-08 | Samsung Electro-Mechanics Co., Ltd. | Temperature compensated bias source circuit |
| CN101216718A (en) * | 2007-12-27 | 2008-07-09 | 电子科技大学 | Piecewise linear temperature compensating circuit and temperature compensation voltage reference source |
| CN101604175A (en) * | 2009-07-07 | 2009-12-16 | 东南大学 | High-order temperature compensation bandgap reference circuit |
| CN102183991A (en) * | 2011-03-18 | 2011-09-14 | 清华大学 | Ultra-low power consumption band gap reference source |
| CN104765405A (en) * | 2014-01-02 | 2015-07-08 | 意法半导体研发(深圳)有限公司 | Current reference circuit for temperature and process compensation |
| CN104914915A (en) * | 2015-05-08 | 2015-09-16 | 河北新华北集成电路有限公司 | High-precision negative-voltage sectional compensation band gap reference voltage source circuit |
| CN107045370A (en) * | 2017-06-20 | 2017-08-15 | 上海灿瑞科技股份有限公司 | It is a kind of that there is high-order temperature compensated band gap reference voltage source circuit |
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2018
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Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6215291B1 (en) * | 1999-01-21 | 2001-04-10 | National Semiconductor Incorporated | Reference voltage circuit |
| US20070030050A1 (en) * | 2005-08-08 | 2007-02-08 | Samsung Electro-Mechanics Co., Ltd. | Temperature compensated bias source circuit |
| CN101216718A (en) * | 2007-12-27 | 2008-07-09 | 电子科技大学 | Piecewise linear temperature compensating circuit and temperature compensation voltage reference source |
| CN101604175A (en) * | 2009-07-07 | 2009-12-16 | 东南大学 | High-order temperature compensation bandgap reference circuit |
| CN102183991A (en) * | 2011-03-18 | 2011-09-14 | 清华大学 | Ultra-low power consumption band gap reference source |
| CN104765405A (en) * | 2014-01-02 | 2015-07-08 | 意法半导体研发(深圳)有限公司 | Current reference circuit for temperature and process compensation |
| CN104914915A (en) * | 2015-05-08 | 2015-09-16 | 河北新华北集成电路有限公司 | High-precision negative-voltage sectional compensation band gap reference voltage source circuit |
| CN107045370A (en) * | 2017-06-20 | 2017-08-15 | 上海灿瑞科技股份有限公司 | It is a kind of that there is high-order temperature compensated band gap reference voltage source circuit |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110377091A (en) * | 2019-08-16 | 2019-10-25 | 电子科技大学 | A kind of high-order compensation band gap a reference source |
| CN116301169A (en) * | 2023-05-23 | 2023-06-23 | 芯动微电子科技(珠海)有限公司 | Bias circuit and comparator |
| CN116301169B (en) * | 2023-05-23 | 2023-08-15 | 芯动微电子科技(珠海)有限公司 | Bias circuit and comparator |
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| Publication number | Publication date |
|---|---|
| CN108427465B (en) | 2019-12-06 |
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