CN108418456B - Control method of double-inversion output four-level converter circuit - Google Patents
Control method of double-inversion output four-level converter circuit Download PDFInfo
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- CN108418456B CN108418456B CN201810384119.1A CN201810384119A CN108418456B CN 108418456 B CN108418456 B CN 108418456B CN 201810384119 A CN201810384119 A CN 201810384119A CN 108418456 B CN108418456 B CN 108418456B
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
- H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
- H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M7/483—Converters with outputs that each can have more than two voltages levels
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0083—Converters characterised by their input or output configuration
- H02M1/009—Converters characterised by their input or output configuration having two or more independently controlled outputs
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Abstract
The invention discloses a double inversion output four-level converter circuit, which comprises: the circuit topology structure of the switching tubes VT1-VT21, the capacitor C22, the capacitor C23 and the capacitor C24 is simple, and compared with the prior art, the total number of the switching tubes is reduced, so that the overall production cost is reduced. The invention can be used in the technical field of electric energy conversion.
Description
Technical Field
The invention relates to the technical field of electric energy conversion, in particular to a control method of a double-inversion output four-level converter circuit.
Background
Along with the continuous aggravation of the problems of energy shortage, environmental deterioration and the like, the energy conservation and emission reduction are urgent. The high-efficiency power electronic converter is an important means for realizing energy conservation and emission reduction, and the existing multilevel converter has the defects of more switch numbers, high production cost, huge volume and the like. For the circuit topology of the double-inversion four-level output, 32 or more switching tubes are needed in the prior art, so that the circuit topology of the double-inversion four-level output is huge in size and high in production cost. Thus, new topologies are to be proposed to address the problems currently faced.
Disclosure of Invention
The purpose of the invention is that: a four-level converter circuit topology with a simple structure is provided.
The invention solves the technical problems as follows: a control method of a double inversion output four-level converter circuit comprises the following steps: the switching transistors VT1-VT21, the capacitor C22, the capacitor C23 and the capacitor C24, wherein one end of the capacitor C22 is respectively connected with the collectors of the switching transistors VT13, VT14 and VT15, the other end of the capacitor C22 is respectively connected with one end of the capacitor C23, the collectors of the switching transistors VT1, VT3 and VT5 are respectively connected with the emitters of the switching transistor VT2, the collectors of the switching transistor VT2 are respectively connected with the emitters of the switching transistors VT13, the collectors of the switching transistor VT16 are respectively connected with the collectors of the switching transistors VT8 and VT19, the emitters of the switching transistor VT8 are respectively connected with the emitters of the switching transistor VT7, the collectors of the switching transistor VT7 are respectively connected with the other ends of the capacitor C23, the collectors of the switching transistors VT9 and VT11, one end of the capacitor C24 is connected with the emitters of the switching transistor VT3, the collectors of the switching transistors VT4 are respectively connected with the emitters of the switching transistor VT14, the emitters of the switching transistor VT17 are respectively connected with the collectors of the switching transistors VT10 and VT20, the emitters of the switching transistors VT10 and VT16 are respectively connected with the collectors of the switching transistors 12, the emitters of the switching transistors VT18 and the switching transistors 10 and the switching transistors 12, the emitters of the switching transistors VT7 are respectively connected with the collectors of the switching transistors 12 and the collectors of the switching transistors 12, and the switching transistors 12 and the emitters of the switching transistors V7 are respectively connected with the collectors of the switching transistors 12.
Further, the switching tubes VT1-VT21 are all connected in parallel with diodes, wherein the cathodes of the diodes are connected with the collectors of the switching tubes VT1-VT21, and the anodes of the diodes are connected with the emitters of the switching tubes VT1-VT 21.
The beneficial effects of the invention are as follows: compared with the prior art, the circuit topology structure is simple, and the total number of the switching tubes is reduced, so that the overall production cost is reduced.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings that are required to be used in the description of the embodiments will be briefly described below. It is evident that the drawings described are only some embodiments of the invention, but not all embodiments, and that other designs and drawings can be obtained from these drawings by a person skilled in the art without inventive effort.
FIG. 1 is a circuit topology of a dual inverter output four-level converter of the present invention;
FIG. 2 is a circuit topology when the output level of the output terminal A is 0V;
FIG. 3 shows that the output level of the output terminal A is Circuit topology at that time;
FIG. 4 shows that the output level of the output terminal A is Circuit topology at that time;
FIG. 5 shows that the output level of the output terminal A is Circuit topology at that time;
FIG. 6 is a circuit topology when the output level of the output terminal U is 0V;
FIG. 7 shows that the output terminal U outputs a level of Circuit topology at that time;
FIG. 8 shows that the output terminal U outputs a level of Circuit topology at that time;
FIG. 9 shows that the output terminal U outputs a level of Circuit topology at that time.
Detailed Description
The conception, specific structure, and technical effects produced by the present invention will be clearly and completely described below with reference to the embodiments and the drawings to fully understand the objects, features, and effects of the present invention. It is apparent that the described embodiments are only some embodiments of the present invention, but not all embodiments, and that other embodiments obtained by those skilled in the art without inventive effort are within the scope of the present invention based on the embodiments of the present invention. In addition, all coupling/connection relationships mentioned herein do not refer to direct connection of the components, but rather, refer to the fact that a more optimal coupling structure may be formed by adding or subtracting coupling aids depending on the particular implementation. The technical features in the invention can be interactively combined on the premise of no contradiction and conflict.
Embodiment 1, referring to fig. 1, a control method of a dual inversion output four-level converter circuit includes: the switching transistors VT1-VT21, the capacitor C22, the capacitor C23 and the capacitor C24, wherein one end of the capacitor C22 is respectively connected with the collectors of the switching transistors VT13, VT14 and VT15, the other end of the capacitor C22 is respectively connected with one end of the capacitor C23, the collectors of the switching transistors VT1, VT3 and VT5 are respectively connected with the emitters of the switching transistor VT2, the collectors of the switching transistor VT2 are respectively connected with the emitters of the switching transistors VT13, the collectors of the switching transistor VT16 are respectively connected with the collectors of the switching transistors VT8 and VT19, the emitters of the switching transistor VT8 are respectively connected with the emitters of the switching transistor VT7, the collectors of the switching transistor VT7 are respectively connected with the other ends of the capacitor C23, the collectors of the switching transistors VT9 and VT11, one end of the capacitor C24 is connected with the emitters of the switching transistor VT3, the collectors of the switching transistors VT4 are respectively connected with the emitters of the switching transistor VT14, the emitters of the switching transistor VT17 are respectively connected with the collectors of the switching transistors VT10 and VT20, the emitters of the switching transistors VT10 and VT16 are respectively connected with the collectors of the switching transistors 12, the emitters of the switching transistors VT18 and the switching transistors 10 and the switching transistors 12, the emitters of the switching transistors VT7 are respectively connected with the collectors of the switching transistors 12 and the collectors of the switching transistors 12, and the switching transistors 12 and the emitters of the switching transistors V7 are respectively connected with the collectors of the switching transistors 12.
As optimization, the switching tubes VT1-VT21 are all connected in parallel with diodes, wherein the cathodes of the diodes are connected with the collectors of the switching tubes VT1-VT21, and the anodes of the diodes are connected with the emitters of the switching tubes VT1-VT 21.
When the circuit works, one end of the capacitor C22 is connected with the positive electrode of the power supply, the other end of the capacitor C24 is connected with the negative electrode of the power supply, and the input voltage of the power supply is。
A node is led out from the collecting point of the emitter of the switch tube VT13, the collector of the switch tube VT2 and the collector of the switch tube VT16, the node is taken as an output end A of the first inverter, a node is led out from the collecting point of the emitter of the switch tube VT14, the collector of the switch tube VT4 and the collector of the switch tube VT17, the node is taken as an output end B of the first inverter, and a node is led out from the collecting point of the emitter of the switch tube VT15, the collector of the switch tube VT6 and the collector of the switch tube VT18, and the node is taken as an output end C of the first inverter; a node is led out from the collecting point of the emitter of the switching tube VT16, the collector of the switching tube VT8 and the collector of the switching tube VT19, and is used as an output end U of the second inverter; a node is led out from the collecting point of the emitter of the switching tube VT17, the collector of the switching tube VT10 and the collector of the switching tube VT20, and is used as an output end V of the second inverter; a node is led out from the junction of the emitter of the switching tube VT18, the collector of the switching tube VT12, and the collector of the switching tube VT21, and serves as the output W of the second inverter.
For the first inverter, the output terminal a is exemplified, and its output level is shown in fig. 2 to 5.
As shown in fig. 2, the switching transistors VT1, VT2, VT3, VT4, VT5, VT6, VT7, VT8, VT9, VT10, VT11, VT12, VT13, VT14, VT15, VT17, VT18, VT20, and VT22 are turned off, the switching transistors VT16 and VT19 are turned on, the voltage at the output point a is clamped at the negative electrode (ground) of the power supply by the switching transistor VT16, and the voltage at the output point a is output by the switching transistor VT19, namely, 0V.
As shown in fig. 3, the switching transistors VT1, VT2, VT3, VT4, VT5, VT6, VT9, VT10, VT11, VT12, VT13, VT14, VT15, VT17, VT18, VT19, VT20, VT21 are turned off, the switching transistors VT7, VT8, VT16 are turned on, the capacitors C22, C23, C24 are turned on for the input voltageDividing the voltage of each capacitor to be/>At this time, the voltage at the output terminal A is the voltage on the capacitor C24, i.e. the output voltage at the output terminal is/>。
As shown in fig. 4, the switching transistors VT3, VT4, VT5, VT6, VT7, VT8, VT9, VT10, VT11, VT12, VT13, VT14, VT15, VT16, VT17, VT18, VT19, VT20, VT21 are turned off, the switching transistors VT1, VT2 are turned on, the capacitor C24, the capacitor C23 is connected with the output terminal a through the switching transistor VT1, the switching transistor VT2, the capacitor C22, the capacitor C23, and the capacitor C24 are connected to the input voltageDividing the voltage of each capacitor to be/>At this time, the voltage at the output terminal A is the sum of the voltages of the capacitor C23 and the capacitor C24, i.e. the output voltage at the output terminal A is/>。
As shown in fig. 5, the switching transistors VT1, VT2, VT3, VT4, VT5, VT6, VT7, VT8, VT9, VT10, VT11, VT12, VT14, VT15, VT16, VT17, VT18, VT19, VT20, and VT21 are turned off, the switching transistor VT13 is turned on, and the input voltage is inputIs connected with the output end A through a switch tube VT13, namely the output voltage of the output end A is/>。
The output B, C of the first inverter operates in a similar manner to output a.
The relation between each output voltage of the output end B and each switch tube is as follows:
0V: the switching tubes VT1, VT2, VT3, VT4, VT5, VT6, VT7, VT8, VT9, VT10, VT11, VT12, VT13, VT14, VT15, VT16, VT18, VT19 and VT21 are closed, and the switching tubes VT17 and VT20 are opened;
: the switching transistors VT1, VT2, VT3, VT4, VT5, VT6, VT7, VT8, VT11, VT12, VT13, VT14, VT15, VT16, VT18, VT19, VT20 and VT21 are closed, and the switching transistors VT9, VT10 and VT17 are opened;
: the switching tubes VT1, VT2, VT5, VT6, VT7, VT8, VT9, VT10, VT11, VT12, VT13, VT14, VT15, VT16, VT17, VT18, VT19, VT20 and VT21 are closed, and the switching tubes VT3 and VT4 are opened;
: the switching transistors VT1, VT2, VT3, VT4, VT5, VT6, VT7, VT8, VT9, VT10, VT11, VT12, VT13, VT15, VT16, VT17, VT18, VT19, VT20, VT21 are turned off and the switching transistor VT14 is turned on.
The relation between the output voltage of the output end C and each switch tube is as follows:
0V: the switching tubes VT1, VT2, VT3, VT4, VT5, VT6, VT7, VT8, VT9, VT10, VT11, VT12, VT13, VT14, VT15, VT16, VT17, VT19 and VT20 are closed, and the switching tubes VT18 and VT21 are opened;
: the switching transistors VT1, VT2, VT3, VT4, VT5, VT6, VT7, VT8, VT9, VT10, VT13, VT14, VT15, VT16, VT17, VT19, VT20 and VT21 are closed, and the switching transistors VT11, VT12 and VT18 are opened;
: the switching tubes VT1, VT2, VT3, VT4, VT7, VT8, VT9, VT10, VT11, VT12, VT13, VT14, VT15, VT16, VT17, VT18, VT19, VT20 and VT21 are closed, and the switching tubes VT5 and VT6 are opened;
: the switching transistors VT1, VT2, VT3, VT4, VT5, VT6, VT7, VT8, VT9, VT10, VT11, VT12, VT13, VT14, VT16, VT17, VT18, VT19, VT20, VT21 are turned off and the switching transistor VT15 is turned on.
For the second inverter, the output terminal U is exemplified, and its output level is shown in fig. 6 to 9.
As shown in fig. 6, the switching transistors VT1, VT2, VT3, VT4, VT5, VT6, VT7, VT8, VT9, VT10, VT11, VT12, VT13, VT14, VT15, VT16, VT17, VT18, VT20, and VT22 are turned off, the switching transistor VT19 is turned on, and the voltage at the output terminal U point is clamped at the negative electrode (ground) of the power supply by the switching transistor VT19, that is, the voltage at the output terminal U point outputs 0V.
As shown in fig. 7, the switching transistors VT1, VT2, VT3, VT4, VT5, VT6, VT9, VT10, VT11, VT12, VT13, VT14, VT15, VT16, VT17, VT18, VT19, VT20, and VT21 are turned off, the switching transistors VT7 and VT8 are turned on, the capacitors C22, C23, and C24 are turned on for the input voltageDividing the voltage of each capacitor to be/>At this time, the voltage at the output terminal U is the voltage on the capacitor C24, i.e. the output voltage at the output terminal U is/>。
As shown in fig. 8, the switching transistors VT3, VT4, VT5, VT6, VT7, VT8, VT9, VT10, VT11, VT12, VT13, VT14, VT15, VT17, VT18, VT19, VT20, VT21 are turned off, the switching transistors VT1, VT2, VT16 are turned on, the capacitor C24, the capacitor C23 is connected to the input voltage through the switching transistors VT1, VT2, the switching transistor VT16 and the output terminal U, the capacitor C22, the capacitor C23, and the capacitor C24Dividing the voltage of each capacitor to be/>At this time, the voltage at the output terminal U is the sum of the voltages of the capacitor C23 and the capacitor C24, i.e. the output voltage at the output terminal U is/>。
As shown in fig. 9, the switching transistors VT1, VT2, VT3, VT4, VT5, VT6, VT7, VT8, VT9, VT10, VT11, VT12, VT14, VT15, VT17, VT18, VT19, VT20, and VT21 are turned off, the switching transistors VT13 and VT16 are turned on, and the input voltage is inputIs connected with the output end U through the switching tubes VT13 and VT16, namely the output voltage of the output end U is/>。
The second inverter output V, W operates in a similar manner to output U.
The relation between each output voltage of the output end V and each switch tube is as follows:
0V: the switching transistors VT1, VT2, VT3, VT4, VT5, VT6, VT7, VT8, VT9, VT10, VT11, VT12, VT13, VT14, VT15, VT16, VT17, VT18, VT19 and VT21 are closed, and the switching transistor VT20 is opened;
: the switching tubes VT1, VT2, VT3, VT4, VT5, VT6, VT7, VT8, VT11, VT12, VT13, VT14, VT15, VT16, VT17, VT18, VT19, VT20 and VT21 are closed, and the switching tubes VT9 and VT10 are opened;
: the switching transistors VT1, VT2, VT5, VT6, VT7, VT8, VT9, VT10, VT11, VT12, VT13, VT14, VT15, VT16, VT18, VT19, VT20 and VT21 are closed, and the switching transistors VT3, VT4 and VT17 are opened;
: the switching transistors VT1, VT2, VT3, VT4, VT5, VT6, VT7, VT8, VT9, VT10, VT11, VT12, VT13, VT15, VT16, VT18, VT19, VT20, VT21 are turned off, and the switching transistors VT14, VT17 are turned on.
The relation between the output voltage of the output end W and each switch tube is as follows:
0V: the switching transistors VT1, VT2, VT3, VT4, VT5, VT6, VT7, VT8, VT9, VT10, VT11, VT12, VT13, VT14, VT15, VT16, VT17, VT18, VT19 and VT20 are closed, and the switching transistor VT21 is opened;
: the switching tubes VT1, VT2, VT3, VT4, VT5, VT6, VT7, VT8, VT9, VT10, VT13, VT14, VT15, VT16, VT17, VT18, VT19, VT20 and VT21 are closed, and the switching tubes VT11 and VT12 are opened;
: the switching transistors VT1, VT2, VT3, VT4, VT7, VT8, VT9, VT10, VT11, VT12, VT13, VT14, VT15, VT16, VT17, VT19, VT20 and VT21 are closed, and the switching transistors VT5, VT6 and VT18 are opened;
: the switching transistors VT1, VT2, VT3, VT4, VT5, VT6, VT7, VT8, VT9, VT10, VT11, VT12, VT13, VT14, VT16, VT17, VT19, VT20, VT21 are turned off, and the switching transistors VT15, VT18 are turned on.
In summary, the first inverter and the second inverter created by the invention can output four levels, which are respectively: 0,，/>，. Compared with the prior art, the circuit topology structure is simple, and the total number of the switching tubes is reduced, so that the overall production cost is reduced.
While the preferred embodiment of the present application has been described in detail, the application is not limited to the embodiments, and various equivalent modifications and substitutions can be made by those skilled in the art without departing from the spirit of the application, and these modifications and substitutions are intended to be included in the scope of the present application as defined in the appended claims.
Claims (2)
1. A control method of a double inversion output four-level converter circuit, comprising: the switching tube VT1-VT21, the capacitor C22, the capacitor C23, the capacitor C24, one end of the capacitor C22 is respectively connected with the collectors of the switching tubes VT13, VT14 and VT15, the other end of the capacitor C22 is respectively connected with the collectors of the switching tubes VT1, VT3 and VT5, the emitter of the switching tube VT1 is connected with the emitter of the switching tube VT2, the collector of the switching tube VT2 is respectively connected with the emitter of the switching tube VT13, the collector of the switching tube VT16 is connected with the collectors of the switching tube VT8 and VT19, the emitter of the switching tube VT8 is respectively connected with the emitter of the switching tube VT7, the collector of the switching tube VT7 is respectively connected with the other end of the capacitor C23, the collectors of the switching tube VT9 and VT11, one end of the capacitor C24 is connected with the emitter of the switching tube VT3, the collector of the switching tube VT4 is respectively connected with the emitter of the switching tube VT14, the emitter of the switching tube VT17 is respectively connected with the collectors of the switching tube VT10 and VT20, the emitter of the switching tube VT10 and the emitter of the switching tube VT20, the emitter of the switching tube VT10 is respectively connected with the emitter of the switching tube 10 and the emitter of the switching tube 12, the emitter of the switching tube 6 and the emitter of the switching tube 11 is respectively connected with the collector of the switching tube 12, the emitter of the switching tube 6 and the emitter of the switching tube 11 is connected with the emitter of the switching tube V12, the emitter of the switching tube V3, and the emitter of the switching tube V12 is connected with the emitter of the collector of the switching tube 12, and the emitter of the switching tube 12 is connected with the emitter of the switching tube 12, and the emitter is connected with the emitter of the switching tube 12;
a node is led out from the junction point of the emitter of the switching tube VT13, the collector of the switching tube VT2 and the collector of the switching tube VT16, and is used as an output end a of the first inverter:
When the switching tubes VT1, VT2, VT3, VT4, VT5, VT6, VT7, VT8, VT9, VT10, VT11, VT12, VT13, VT14, VT15, VT17, VT18, VT20 and VT22 are closed, the switching tubes VT16 and VT19 are opened, the voltage at the point A of the output end is clamped at the negative electrode of the power supply by the switching tube VT16, namely, the voltage at the point A of the output end is output by the switching tube VT19 to be 0V;
When the switching transistors VT1, VT2, VT3, VT4, VT5, VT6, VT9, VT10, VT11, VT12, VT13, VT14, VT15, VT17, VT18, VT19, VT20, VT21 are turned off, the switching transistors VT7, VT8, VT16 are turned on, the capacitors C22, C23, C24 are turned on for the input voltage Dividing the voltage of each capacitor to be/>At this time, the voltage at the output terminal A is the voltage on the capacitor C24, i.e. the output voltage at the output terminal is/>；
When the switching tubes VT3, VT4, VT5, VT6, VT7, VT8, VT9, VT10, VT11, VT12, VT13, VT14, VT15, VT16, VT17, VT18, VT19, VT20, VT21 are cut off, the switching tubes VT1, VT2 are conducted, the capacitor C24 and the capacitor C23 are connected with the output end A through the switching tube VT1, the switching tube VT2, the capacitor C22, the capacitor C23 and the capacitor C24 are connected with the input voltageDividing the voltage of each capacitor to be/>At this time, the voltage at the output terminal A is the sum of the voltages of the capacitor C23 and the capacitor C24, i.e. the output voltage at the output terminal A is/>；
When the switching transistors VT1, VT2, VT3, VT4, VT5, VT6, VT7, VT8, VT9, VT10, VT11, VT12, VT14, VT15, VT16, VT17, VT18, VT19, VT20 and VT21 are closed, the switching transistor VT13 is opened, and the voltage is inputIs connected with the output end A through a switch tube VT13, namely the output voltage of the output end A is/>；
A node is led out from the collecting point of the emitter of the switching tube VT16, the collector of the switching tube VT8 and the collector of the switching tube VT19, and is used as an output end U of the second inverter;
When the switching tubes VT1, VT2, VT3, VT4, VT5, VT6, VT7, VT8, VT9, VT10, VT11, VT12, VT13, VT14, VT15, VT16, VT17, VT18, VT20 and VT22 are turned off, the switching tube VT19 is turned on, the voltage at the output end U point is clamped at the negative electrode of the power supply by the switching tube VT19, namely the voltage at the output end U point is output by 0V;
When the switching transistors VT1, VT2, VT3, VT4, VT5, VT6, VT9, VT10, VT11, VT12, VT13, VT14, VT15, VT16, VT17, VT18, VT19, VT20, VT21 are turned off, the switching transistors VT7 and VT8 are turned on, the capacitors C22, C23, C24 are connected to the input voltage Dividing the voltage of each capacitor to be/>At this time, the voltage at the output terminal U is the voltage on the capacitor C24, i.e. the output voltage at the output terminal U is/>；
When the switching tubes VT3, VT4, VT5, VT6, VT7, VT8, VT9, VT10, VT11, VT12, VT13, VT14, VT15, VT17, VT18, VT19, VT20, VT21 are cut off, the switching tubes VT1, VT2, VT16 are conducted, the capacitor C24, the capacitor C23 is connected with the output end U through the switching tube VT1, the switching tube VT2, the switching tube VT16 is connected with the input voltage by the capacitor C22, the capacitor C23 and the capacitor C24Dividing the voltage of each capacitor to be/>At this time, the voltage at the output terminal U is the sum of the voltages of the capacitor C23 and the capacitor C24, i.e. the output voltage at the output terminal U is/>；
When the switching tubes VT1, VT2, VT3, VT4, VT5, VT6, VT7, VT8, VT9, VT10, VT11, VT12, VT14, VT15, VT17, VT18, VT19, VT20 and VT21 are closed, the switching tubes VT13 and VT16 are opened, and the voltage is inputIs connected with the output end U through the switching tubes VT13 and VT16, namely the output voltage of the output end U is/>。
2. The control method of the double-inversion output four-level converter circuit according to claim 1, wherein: the switching tubes VT1-VT21 are all connected in parallel with diodes, wherein the cathodes of the diodes are connected with the collectors of the switching tubes VT1-VT21, and the anodes of the diodes are connected with the emitters of the switching tubes VT1-VT 21.
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| CN208094461U (en) * | 2018-04-26 | 2018-11-13 | 佛山科学技术学院 | A kind of four level shifter circuits of double inversion outputs |
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| JPH11289774A (en) * | 1998-04-03 | 1999-10-19 | Yaskawa Electric Corp | Overcurrent protector for inverter |
| CN100571012C (en) * | 2003-07-18 | 2009-12-16 | 清华大学 | Layering superposing type voltage-type multi-level circuit |
| CN102594187B (en) * | 2012-02-20 | 2014-06-25 | 阳光电源股份有限公司 | Four-level topological unit and application circuit thereof |
| CN102611342B (en) * | 2012-03-13 | 2014-10-08 | 华为技术有限公司 | three-level inverter |
| CN202679243U (en) * | 2012-05-17 | 2013-01-16 | 浙江工业大学 | BJT type self-excited Buck converter with small main switch tube driving loss |
| CN202978746U (en) * | 2012-12-21 | 2013-06-05 | 京东方科技集团股份有限公司 | Inverter and grid-connected power generation system |
| CN104242676A (en) * | 2013-06-13 | 2014-12-24 | 成都昊地科技有限责任公司 | Frequency conversion circuit used for high-voltage and high-power frequency control |
| CN103490656B (en) * | 2013-10-10 | 2015-09-09 | 哈尔滨工业大学 | Based on the carrier modulating method of four electrical level inverter topological structures of H bridge |
| CN103762874B (en) * | 2014-01-28 | 2017-01-11 | 华南理工大学 | Double-load three-phase nine-switch-block MMC inverter and control method thereof |
| EP3143687A1 (en) * | 2014-05-16 | 2017-03-22 | ABB Schweiz AG | Multi level inverter |
| CN104506061B (en) * | 2014-11-12 | 2018-02-27 | 宁波中博电器有限公司 | A kind of small no-load current inverter |
| KR20160057912A (en) * | 2014-11-14 | 2016-05-24 | 삼성중공업 주식회사 | Four level power converter |
| CN105827129B (en) * | 2015-01-04 | 2020-06-02 | 华为技术有限公司 | Circuit and power converter with multi-level topology |
| CN104883087B (en) * | 2015-05-04 | 2017-09-22 | 长安大学 | A kind of multi-electrical level inverter universal pulse width modulating method |
| CN105048842B (en) * | 2015-09-07 | 2017-10-17 | 阳光电源股份有限公司 | A kind of single-phase four electrical level inverters and its application circuit |
| CN105226980B (en) * | 2015-10-21 | 2017-12-22 | 阳光电源股份有限公司 | A kind of four electrical level inverter low voltage traversing control methods and system |
| CN105375514B (en) * | 2015-11-10 | 2018-01-02 | 苏州大学 | A kind of limited on off state prediction computational methods and system |
| CN105577012A (en) * | 2016-03-15 | 2016-05-11 | 东南大学 | Hybrid five-level current converter and control method thereof |
| CN105811835B (en) * | 2016-04-26 | 2018-08-24 | 南京航空航天大学 | One kind opening winding permanent magnet Synchromous machine drive system and its control method |
| CN105958893B (en) * | 2016-06-02 | 2018-05-15 | 南京航空航天大学 | Double-stator double-salient motor drive system based on nine switch converters of three-phase |
| CN206041848U (en) * | 2016-09-13 | 2017-03-22 | 佛山科学技术学院 | Novel topological structure of two contravariant output translators |
| CN106533217B (en) * | 2016-12-28 | 2019-03-15 | 北京天诚同创电气有限公司 | Rectifier, rectification circuit and its control method |
| CN107634672B (en) * | 2017-09-30 | 2019-09-06 | 中国矿业大学 | Four level converters of one kind and its control method |
-
2018
- 2018-04-26 CN CN201810384119.1A patent/CN108418456B/en active Active
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN208094461U (en) * | 2018-04-26 | 2018-11-13 | 佛山科学技术学院 | A kind of four level shifter circuits of double inversion outputs |
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