CN108376690A - A kind of autoregistration interconnected method for manufacturing high density mram - Google Patents
A kind of autoregistration interconnected method for manufacturing high density mram Download PDFInfo
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- CN108376690A CN108376690A CN201810049346.9A CN201810049346A CN108376690A CN 108376690 A CN108376690 A CN 108376690A CN 201810049346 A CN201810049346 A CN 201810049346A CN 108376690 A CN108376690 A CN 108376690A
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B61/00—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
- H10B61/10—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices comprising components having two electrodes, e.g. diodes or MIM elements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
Abstract
The present invention relates to a kind of autoregistration interconnected methods for manufacturing high density mram, include the following steps：Step 1: deposition bottom conductive electrode layer, MTJ element layer and metal mask layer；Step 2: preparing cylindricality MTJ element, in-situ deposition is used to protect the first dielectric cap layer of cylindricality MTJ element；Step 3: manufacture bottom conductive electrode, second dielectric cap layer of the deposition for filling cylindricality MTJ element array gap；Step 4: the second dielectric cap layer of leveling, exposes the first dielectric cap layer above cylindricality MTJ element；Step 5: etching the first, second dielectric cap layer simultaneously, the metal mask layer above exposure cylindricality MTJ element is self aligned that the second contact hole is formed above cylindricality MTJ element；Step 6: the upper conductive layer of deposition.The method of the present invention considerably increases the yield of MRAM device；One of lithography step is saved, production cost and risk are greatly reduced.
Description
Technical field
A kind of autoregistration interconnected method for manufacturing high density mram of the present invention, is related to magnetic RAM
(MRAM) or magnetic sensor etc. is related to the self-spining device manufacturing technology field of magnetic tunnel-junction (MTJ), more particularly to a kind of
Manufacture the method that the MTJ element in high density mram forms electrical contact with upper conductive layer.
Background technology
Magnetic RAM (Magnetic Random Access Memory, abbreviation MRAM), which is one kind, to be had
High-speed read-write, reliable, Flouride-resistani acid phesphatase, approaches infinitely the non-volatile of many advantages, such as erasable number repeatedly at non-volatile, low-power consumption
Property memory technology, in numerous applications provide better than legacy memory such as static RAM (SRAM), dynamic
The advantages of random access memory (DRAM) and flash memories, therefore, application prospect is considerable.
The core memory portion of MRAM is magnetic tunnel-junction (Magnetic Tunnel Junction, abbreviation MTJ) element, is led to
Normal MRAM is made of the array for the MTJ element protected with dielectric sidewall and separated between each unit.Wherein MTJ element quilt
It is manufactured into independent column (island) structure, lower section is formed with lower conductiving layer by hearth electrode or contact hole and interconnected, and top passes through
Top electrode is formed with upper conductive layer and is interconnected, central filler dielectric.It is generally acknowledged that the smaller available bigger of MTJ element characteristic size
High low resistance state difference, lower resistance states convert energy, especially perpendicular magnetic anisotropic MTJ (pMTJ), more have
Conducive to realize high density, low energy consumption storage, however, smaller characteristic size also cause more accurate manufacturing process, it is higher at
This.
The MTJ element of MRAM forms the possible way interconnected with upper conductive layer：Stripping technology, alignment process with
And flatening process.The limitation of dielectric cap layer depositing operation is larger after wherein stripping technology etches MTJ element, generally will not
It is used on integrated circuit interconnection module (BEOL)；Alignment process is additional after MTJ element characteristic size enters sub-50nm
Mask and high alignment require to substantially increase manufacturing cost, reduce product yield；Flatening process is most economical at this stage
Method, pass through chemically mechanical polishing (CMP) and remove extra dielectric or insulating materials above MTJ element, expose MTJ element
The metal layer being previously deposited realizes that MTJ element is interconnected with upper conductive layer.For high density mram, element is intensive, element characteristics ruler
Very little small, using the scheme of conventional photoetching alignment opening, cost is too high.However the scheme of CMP levelings is used to require top electrode gold
Certain height and the metal must be had and wait for must having very high removal to select between planarizing dielectric by belonging to (metal shadowing layer)
Select ratio；However metal shadowing layer height too Gao Youhui forms shadow effect in etching process, significantly limits etching rear side
The technique of wall cleaning, and the removal selection ratio planarized is not high.However etching rear wall cleaning is high-performance storage
Device and the key for ensureing yield.
Since MRAM reduces the needs of write current, the size of MTJ element constantly reduces, be continuously improved MRAM capacity,
It is increasing that the difficulty that MTJ element is contacted with the formation of upper conductive layer is also resulted in while reduction energy consumption.Therefore, it finds a kind of suitable
The MTJ element for closing high density mram device forms the method contacted with upper conductive layer, becomes a very crucial problem.
Invention content
1. goal of the invention：
It is existing to solve the purpose of the present invention is to provide a kind of autoregistration interconnected method for manufacturing high density mram
MTJ element forms the big problem of the difficulty contacted with upper conductive layer when manufacturing high density mram present in technology.
2. technical solution：
In order to solve the problems, such as to be encountered in above-mentioned background introduction, the present invention propose it is a kind of for manufacture high density mram from
It is directed at interconnected method, this method comprises the following steps：
Step 1: deposition bottom conductive electrode layer, MTJ element layer and metal mask layer；
Step 2: preparing cylindricality MTJ element, in-situ deposition is used to protect the first dielectric cap layer of cylindricality MTJ element；
Step 3: manufacture bottom conductive electrode, deposition are protected for filling second dielectric in cylindricality MTJ element array gap
Layer；
Step 4: the second dielectric cap layer of leveling, exposes the first dielectric cap layer above cylindricality MTJ element；
Wherein, first dielectric cap layer and the second dielectric cap layer use different materials, selection suitable
Levelling process, the first dielectric cap layer are leveled slower than the second dielectric cap layer.Since position is higher, cylindricality MTJ element
First dielectric cap layer of top is partly exposed after levelling process；
Step 5: the first, second dielectric cap layer is etched simultaneously, the metal mask layer above exposure cylindricality MTJ element,
It is self aligned that the second contact hole is formed above cylindricality MTJ element.
Wherein, first dielectric cap layer and the second dielectric cap layer use different materials, selection suitable
Etch process, the second dielectric cap layer are etched slower than the first dielectric cap layer.The first electricity being exposed in step 4 is situated between
Quality guarantee sheath is etched, and exposes the metal mask layer above cylindricality MTJ element；
Step 6: the upper conductive layer of deposition.
Further, when the step 2 may include preparing cylindricality MTJ element, the step of bottom conductive electrode layer is removed；
Further, the step 3 can not include the step of manufacture bottom conductive electrode, and Direct precipitation is for filling cylindricality
Second dielectric cap layer in MTJ element array gap；
Further, may include the second of cylindricality MTJ element side before step 5 after the step 4
The step of third mask is formed on dielectric cap layer；
Preferably, the material of metal mask layer is preferably by tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), tungsten
(W) or ruthenium (Ru) composition single layer or multiple material form lamination, such as physical vapour deposition (PVD) (PVD), plasma may be used
Enhance the depositing technics appropriate such as chemical vapor deposition (PECVD) to form metal mask layer.
Preferably, first dielectric cap layer can preferentially use plasma reinforced chemical vapour deposition (PECVD),
The suitable technique deposition of nitride of physical vapour deposition (PVD) (PVD) or electron beam evaporation plating (EBeam) etc, silicon nitride (Si3N4) or
Aluminium oxide (Al2O3) etc any dielectric substance appropriate composition.
Preferably, second dielectric cap layer can preferentially use plasma reinforced chemical vapour deposition
(PECVD), the suitable technique deposited oxide of physical vapour deposition (PVD) (PVD) or electron beam evaporation plating (EBeam) etc, silica,
Silicon oxynitride (SiON), tantalum oxide (Ta2O5) or hafnium oxide (HfO2) etc any dielectric substance appropriate composition.
Preferably, in the above-mentioned methods, the step of the second dielectric cap layer of the leveling may include using chemical machinery
It is well known any suitable in the semi-conductor industry of polishing (CMP), electrochemical mechanical polishing (ECMP) or ion grinding etc
Flatening process, or such as reactive ion etching (RIE) etc any other removal technique appropriate, to remove part second
Dielectric cap layer, partly to expose the first dielectric cap layer above cylindricality MTJ element.
Preferably, in the above-mentioned methods, the step of the first dielectric cap layer of the etching may include dry etching, it is anti-
Any suitable removal technique for answering ion etching, wet etching etc, to remove the first dielectric cap layer exposed,
Contact hole is formed on cylindricality MTJ element to autoregistration.
3. advantage and effect：
The present invention is allowed to compared with prior art, have the following advantages that and actively due to technical solution more than use
Effect：
(1) present invention needs the process characteristic of in-situ deposition dielectric cap layer using MTJ element, using in-situ deposition
Second dielectric cap layer of the first dielectric cap layer and filling inter-electrode gap selects the side of different dielectric substances
Case, while the method for obtaining larger flatening process window and autoregistration removal MTJ element upper dielectric protective layer.
(2) provided by the invention to form the method that MTJ element is contacted with the formation of upper conductive layer in MRAM device, particularly will
Flatening process is divided into the completion of two steps with MTJ element upper dielectric protective layer removal technique, is wanted to MTJ element top-level metallic thickness
It asks relatively low, considerably increases the yield of MRAM device.
(3) provided by the invention to form the method that MTJ element is contacted with the formation of upper conductive layer in MRAM device, particularly adopt
It, to save one of photoetching, is produced into so greatly reducing with self aligned scheme without carrying out necessary lithography step
Sheet and risk.
Description of the drawings
Fig. 1~6 schematically illustrate the according to embodiments of the present invention one MTJ members for being used for realizing MRAM device with sectional view
Part forms the method contacted with upper conductive layer.
Fig. 7~9 schematically illustrate the according to embodiments of the present invention two MTJ members for being used for realizing MRAM device with sectional view
Part forms the method contacted with upper conductive layer.
Figure 10~12 schematically illustrate according to embodiments of the present invention three MTJ for being used for realizing MRAM device with sectional view
Element forms the method contacted by upper conductive layer with lower section such as silicon-based transistor.
Figure 13~14 are schematically demonstrated with scanning electron microscope (SEM) photo and realize MRAM device according to the present invention
MTJ element array forms the feasibility of the method contacted with upper conductive layer.
Figure 15 is the method for the present invention flow diagram.
Figure label is as follows：
10, dielectric region 12, contact hole 14', bottom conductive electrode layer
14, bottom conductive electrode 16 ', MTJ element layer 16, cylindricality MTJ element
18, metal mask layer 20, the first dielectric cap layer 22, the second dielectric cap layer
24, the second mask 26, chemical etching process 28, the second contact hole
30, upper conductive layer 32, third contact hole 34, third mask
36, the 4th contact hole
Specific implementation mode
The following detailed description of the present invention is only exemplary, and attached drawing is schematic diagram.Each functional layer being directed to
Or the non-actual size of thickness and width in region, attached drawing are all made of very simplified form and use non-accurate ratio, only
For purpose that is convenient, lucidly aiding in illustrating case study on implementation of the present invention.And the present invention is not construed as being limited only to
The example embodiment herein proposed, but all changes originally fallen into invention scope, equivalent and replaceable should be covered
Object.
Embodiment one：
With reference to attached drawing, Fig. 1-6 exemplary plots give the MTJ that MTJ element array in MRAM device is manufactured according to the present invention
Element forms a kind of method contacted with upper conductive layer.Fig. 1 is the section that MTJ element array film is formed on dielectric region 10
Figure.Dielectric region 10 can be by any dielectric substance appropriate of such as silica (SiO2), aluminium oxide (Al2O3) etc
Composition.Contact hole 12 can include such as aluminium (Al), aluminium alloy, copper (Cu), copper alloy, tungsten (W), titanium (Ti), tantalum (Ta) etc
Any conductive material appropriate, and can include such as tantalum nitride (TaN), titanium nitride (TiN) or titanium tungsten (TiW) etc
Barrier material.Contact hole 12 is only marked in figure, there be multilayer Metal and contact hole and bottom in 12 lower section of contact hole
Transistor；Although not marking, contact hole 12 is typically via contact hole or metallic conduction lamination (in conventional CMOS structure
Plain conductor) it is interconnected with the formation of such as silicon-based semiconductor transistor, these transistors constitute control and the reading circuit of MRAM.
In the embodiment of the embodiment of the present invention one, bottom conductive electrode layer 14 ' is deposited on dielectric region 10 and contact hole
12 tops, and be electrically connected with contact hole formation, bottom conductive electrode layer 14 ' includes such as adhesion layer, bottom electrode layer, buffer layer, crystalline substance
Multiple layers such as seed layer or a combination, bottom conductive electrode layer 14 ' is preferably by tantalum (Ta), tantalum nitride (TaN), titanium (Ti), nitridation
The single layer of the materials such as titanium (TiN), tungsten (W), ruthenium (Ru) composition or the lamination of multiple material composition, may be used such as physical vapor
The depositing technics appropriate such as (PVD), plasma reinforced chemical vapour deposition (PECVD) is deposited to form bottom conductive electrode layer 14 '.
MTJ element layer 16 ' is deposited on the top of bottom conductive electrode layer 14 ', and MTJ element layer 16 ' includes such as inverse ferric magnetosphere, SAF layer, ferromagnetic
Multiple layers such as reference layer, medium tunnel layer, ferromagnetic free layer, metal cladding or one combination, MTJ element layer 16 ' preferably by
Cobalt (Co), iron (Fe), nickel (Ni), the ferro-cobalt nickel alloy of different component, the ferro-cobalt boron alloy of different component, magnesia (MgO), tantalum
(Ta), such as physical vapour deposition (PVD) (PVD), original may be used in the suitable lamination of the materials such as ruthenium (Ru), platinum (Pt), tungsten (W) composition
Sublayer deposits any thin film deposition processes appropriate such as (ALD), molecular beam epitaxy (MBE), pulsed laser deposition (PLD) to be formed
MTJ element layer 16 '.
With reference to figure 2, metal mask layer 18 is deposited on above MTJ element layer.The material of metal mask layer is preferably by tantalum
(Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), tungsten (W), the single layer of ruthenium (Ru) composition or multiple material form lamination,
The depositing technics appropriate such as physical vapour deposition (PVD) (PVD), plasma reinforced chemical vapour deposition (PECVD) may be used
Form metal mask layer.18 thickness of metal mask layer can be slightly larger than MTJ element layer 16, in embodiment one, metal mask layer
18 thickness can be 1nm~500nm.Using standardized graphical technology, metal mask layer 18 is formed, deep UV lithography may be used
(DUV), photoetching process appropriate and such as reactive ion etching such as electron beam exposure (EBL), extreme ultraviolet (EUV)
(RIE), the appropriate etching technics of inductively coupled plasma etching (ICP), chemical attack etc forms metal shadowing layer 18.
It is remaining using the suitable degumming process removal of such as oxygen plasma, chemical cleaning etc and after forming metal mask layer 18
Photoresist.Metal mask layer 18 is independent column (island) structure, and minimum dimension is determined by cylindricality MTJ element design size
Fixed, in the present embodiment, the minimum dimension of metal mask layer 18 (is divided into cylinder, cylindroid, the minimum dimension of cylinder is that circle is straight
Diameter, cylindroid minimum dimension are that ellipse short shaft is long) can be 5nm~400nm.By etching technics by metal mask layer 18
Shape is transmitted on MTJ element layer 16, and such as ion beam etching (IBE), inductively coupled plasma etching may be used
(ICP), one or more etching technics appropriate such as reactive ion etching (RIE) form independent column MTJ element 16；It carves
Erosion requirement can include to stop at certain layer top in MTJ element layer 16 ', stop in bottom conductive electrode layer 14 ' in certain layer
Just, one or more etchings requirements such as 10 top of dielectric region are stopped at；In embodiment one, using being parked in bottom conductive electrode layer
14 ' tops also include that side wall cleaning, damaged layer removal and construction recovery after MTJ element layer pattern etc. are appropriate herein
Operation is to obtain best column MTJ element performance；It also include in-situ deposition the after cylindricality MTJ element 16 is graphical with reference to figure 2
The step of one dielectric cap layer 20, this step preferentially use plasma reinforced chemical vapour deposition (PECVD), physical vapor heavy
Long-pending (PVD's), electron beam evaporation plating (EBeam) etc suitably technique deposition of nitride, silicon nitride (Si3N4) etc is any appropriate
Dielectric substance composition.In the present embodiment, the thickness of the first dielectric cap layer 20 can be 10~100nm.
With reference to figure 3, cylindricality MTJ element 16 is located at the side of contact hole 12, and corresponding application may include that field is convertible
(Field-like), Quantum geometrical phase (SOT) is convertible etc. needs the element knot far from contact hole by cylindricality MTJ element 16
Structure；Using standardized graphical technology, bottom conductive electrode 14 is formed below MTJ, and it is appropriate that deep UV lithography (DUV) etc. may be used
Photoetching process and such as reactive ion etching (RIE), inductively coupled plasma etching (ICP), chemical attack etc
Appropriate etching technics forms bottom conductive electrode 14.It is clear using such as oxygen plasma, chemistry and after forming bottom conductive electrode 14
The suitable degumming process washed etc removes remaining photoresist.It also include deposit second after forming bottom conductive electrode 14 with reference to figure 3
The step of dielectric cap layer 22, this step preferentially use plasma reinforced chemical vapour deposition (PECVD), physical vapour deposition (PVD)
(PVD), any dielectric appropriate of the suitable technique deposited oxide of electron beam evaporation plating (EBeam) etc, silica etc
Material forms.In the present embodiment, the thickness of the second dielectric cap layer 22 can be 50~500nm.
With reference to figure 4, since the second dielectric cap layer 22 is formed using the material for being not used in the first dielectric cap layer 20,
Cause, when the first dielectric cap layer 20 and the second dielectric cap layer 22 are subjected to leveling, to select suitable levelling process, the
Two dielectric cap layers 22 are leveled than the first dielectric cap layer 20 faster.For example, in the present embodiment, the first dielectric is protected
Sheath can include PEN, and the second dielectric cap layer can include tetraethyl orthosilicate (TEOS).By levelling process
Afterwards, the second mask 24 is formed.Preferred levelling process can include chemically mechanical polishing (CMP), electrochemical mechanical polishing
(ECMP) or ion grinding etc semi-conductor industry in well known any suitable levelling process, or such as reactive ion carve
Any other removal technique appropriate for losing (RIE) etc, to remove the second dielectric cap layer of part 22, partly to expose
First dielectric cap layer 20 above cylindricality MTJ element.
With reference to figure 5, since the second dielectric cap layer 22 is formed using the material for being not used in the first dielectric cap layer 20,
Cause when the first dielectric cap layer 20 and the second dielectric cap layer 22 are subjected to chemical etching, selects suitable etching work
Skill, the first dielectric cap layer 20 are etched than the second dielectric cap layer 22 faster, and the first dielectric cap layer 20 is carved
Erosion is faster than metal mask layer 18.For example, in the present embodiment, the first dielectric cap layer can include the nitrogen of PECVD depositions
SiClx, and the second dielectric cap layer can include the silica of PECVD depositions.The formation of second mask 24 causes the first electricity to be situated between
Quality guarantee sheath 20 etch after form the second contact hole 28, and expose the top of metal mask layer 18, side wall a part.So as to
It can be electrically connected with conductive layer foundation of the subsequent deposition on metal mask layer 18 in metal mask layer 18.Preferred chemical etching
Technique 26 can include dry etching, reactive ion etching, wet etching.
With reference to Fig. 6, in the present embodiment, the second contact hole 28 is being formed and metal mask 18 is at least at least partially exposed it
Afterwards, upper conductive layer 30 can be deposited on metal mask layer 18 and the second dielectric cap layer 22.Upper conductive layer 30 can wrap
Any conduction material appropriate containing such as aluminium (Al), aluminium alloy, copper (Cu), copper alloy, tungsten (W), titanium (Ti), tantalum (Ta) etc
Material, and can include the barrier material of such as tantalum nitride (TaN), titanium nitride (TiN) or titanium tungsten (TiW) etc.Upper conductive layer
30 can establish between cylindricality MTJ element or between cylindricality MTJ element and such as silicon-based transistor and be electrically connected.
Embodiment two：
With reference to figure 7, in the second embodiment of the present invention, cylindricality MTJ element 16 is located at the surface of contact hole 12, corresponding
Using may include spin transfer torque (STT), heat auxiliary (Thermal-assist), regulating and controlling voltage (VCMA) etc. need by
MTJ element is placed on the component structure right over contact hole, and high density mram device is realized to reduce cellar area；In this implementation
In example, when the figure of metal mask layer 18 is transmitted to MTJ element layer and metal layer, using etch-stop on dielectric region 10
Side also includes the operations appropriate such as side wall cleaning, damaged layer removal and construction recovery after cylindricality MTJ element is graphical herein
To obtain best MTJ element performance；Also include that cylindricality MTJ element graphically protect by the first dielectric of rear in-situ deposition with reference to figure 7
The step of sheath 20, this step preferentially use plasma reinforced chemical vapour deposition (PECVD), physical vapour deposition (PVD) (PVD), electricity
Any dielectric material appropriate of (EBeam) etc suitable technique deposition of nitride, silicon nitride (Si3N4) etc is deposited in beamlet
Material composition.In the present embodiment, the thickness of the first dielectric cap layer 20 can be 10nm~100nm.Also include heavy with reference to figure 7
Product the first dielectric cap layer 20 after, deposit the second dielectric cap layer 22 the step of, this step preferentially use plasma enhance
The suitable technique deposit oxidation of chemical vapor deposition (PECVD), physical vapour deposition (PVD) (PVD), electron beam evaporation plating (EBeam) etc
Any dielectric substance composition appropriate of object, silica etc.In the present embodiment, the thickness of the second dielectric cap layer 22
Can be 50~500nm.
With reference to figure 8, since the second dielectric cap layer 22 is formed using the material for being not used in the first dielectric cap layer 20,
Cause, when the first dielectric cap layer 20 and the second dielectric cap layer 22 are subjected to leveling, to select suitable levelling process, the
Two dielectric cap layers 22 are leveled than the first dielectric cap layer 20 faster.For example, in the present embodiment, the first dielectric is protected
Sheath can include the silicon nitride (Si3N4) of PECVD depositions, and the second dielectric cap layer can include the oxygen of PECVD depositions
SiClx (SiO2).After levelling process, the second mask 24 is formed.Preferred levelling process can include chemically mechanical polishing
(CMP), electrochemical mechanical polishing (ECMP) or ion grinding etc semi-conductor industry in well known any suitable leveling
Technique, or such as reactive ion etching (RIE) etc any other removal technique appropriate, to remove the second dielectric of part
Protective layer 22, partly to expose the first dielectric cap layer 20 above cylindricality MTJ element.
With reference to figure 9, since the second dielectric cap layer 22 is using the material composition for being not used in the first dielectric cap layer 20.
Cause when the first dielectric cap layer 20 and the second dielectric cap layer 22 are subjected to chemical etching, selects suitable etching work
Skill, the first dielectric cap layer 20 are etched than the second dielectric cap layer 22 faster, and the first dielectric cap layer 20 is carved
Erosion is faster than metal mask layer 18.For example, in embodiment, the first dielectric cap layer can include the nitridation of PECVD depositions
Silicon (Si3N4), and the second dielectric cap layer can include the silica (SiO2) of PECVD depositions.The formation of second mask 24
The second contact hole 28 is formed after causing the first dielectric cap layer 20 to etch, and exposes the top of metal mask 18, side wall
A part.So as to be electrically connected with conductive layer foundation of the subsequent deposition on metal mask layer 18 in metal mask layer 18.It is excellent
The chemical etching process of choosing can include dry etching, reactive ion etching, wet etching.
Embodiment three：
It is given with reference to 10~12 exemplary plot of figure and is used for realizing that MTJ element passes through upper conduction in MRAM device according to the present invention
Layer forms a kind of method of electrical contact with third contact hole 32.Although not marking, third contact hole 32 is typically via contact
Hole or metallic conduction lamination are formed with such as silicon-based semiconductor transistor to be interconnected.These transistors constitute the control and reading of MRAM
Sense circuit.With reference to figure 11, in the present embodiment, it is leveled and the first dielectric cap layer forming the second dielectric cap layer 22
After 20 are at least at least partially exposed, using standardized graphical technology, third mask 34 is formed above third contact hole 32, it can be with
Using the photoetching processes appropriate such as deep UV lithography (DUV) and such as reactive ion etching (RIE), inductively coupled plasma
Etching (ICP), chemical attack etc appropriate etching technics form third mask 34, preferably third mask 34 stops at the
One dielectric cap layer, 20 top.And after forming third mask 34, using the suitable of such as oxygen plasma, chemical cleaning etc
Degumming process removes remaining photoresist.With reference to figure 12, in the present embodiment, the second contact hole 28 and the 4th contact hole 36 are same
When prepare complete.
It is given with reference to 13~14 electromicroscopic photograph of figure and is used for realizing that MTJ element array is formed in MRAM device according to the present invention
The technique photo of contact hole, clearly demonstrate the present invention on the MTJ element of high density mram device autoregistration formed
The feasibility of contact hole.
It is understood that although above-mentioned each embodiment has been described in the manufacture with reference to MTJ element, the present invention
It is not limited to these embodiments.It is understood that the method for the present invention can be used to and such as giant magnetoresistance (GMR)
Any independent island (column) element appropriate of element, regulating and controlling voltage magnetic anisotropy (VCMA) element etc and upper conductive layer
Form contact.
Claims (10)
1. a kind of autoregistration interconnected method for manufacturing high density mram, it is characterised in that：This method comprises the following steps：
Step 1: deposition bottom conductive electrode layer, MTJ element layer and metal mask layer；
Step 2: preparing cylindricality MTJ element, in-situ deposition is used to protect the first dielectric cap layer of cylindricality MTJ element；
Step 3: manufacture bottom conductive electrode, second dielectric cap layer of the deposition for filling cylindricality MTJ element array gap；
Step 4: the second dielectric cap layer of leveling, exposes the first dielectric cap layer above cylindricality MTJ element；
Step 5: etch the first, second dielectric cap layer simultaneously, the metal mask layer above exposure cylindricality MTJ element, from right
Accurate forms the second contact hole above cylindricality MTJ element；
Step 6: the upper conductive layer of deposition.
2. a kind of autoregistration interconnected method for manufacturing high density mram according to claim 1, it is characterised in that：Institute
It states step 2 to can further include when preparing cylindricality MTJ element, the step of bottom conductive electrode layer is removed.
3. a kind of autoregistration interconnected method for manufacturing high density mram according to claim 1, it is characterised in that：Institute
The step of step 3 can not include manufacture bottom conductive electrode is stated, Direct precipitation is used to fill the of cylindricality MTJ element array gap
Two dielectric cap layers.
4. a kind of autoregistration interconnected method for manufacturing high density mram according to claim 1, it is characterised in that：
After the step 4, before step 5, further comprise being formed on the second dielectric cap layer of cylindricality MTJ element side
The step of third mask.
5. a kind of autoregistration interconnected method for manufacturing high density mram according to claim 1 or 2 or 3 or 4, special
Sign is：First dielectric cap layer and the second dielectric cap layer uses different materials.
6. a kind of autoregistration interconnected method for manufacturing high density mram according to claim 1 or 2 or 3 or 4, special
Sign is：The list that the material of metal mask layer is preferably made of tantalum Ta, tantalum nitride TaN, titanium Ti, titanium nitride TiN, tungsten W or ruthenium Ru
Layer or multiple material form lamination, are covered using physical vapour deposition (PVD) or plasma reinforced chemical vapour deposition technique to form metal
Film layer.
7. a kind of autoregistration interconnected method for manufacturing high density mram according to claim 1 or 2 or 3 or 4, special
Sign is：First dielectric cap layer is preferentially to use plasma reinforced chemical vapour deposition, physical vapour deposition (PVD) or electricity
Beamlet evaporation process deposition of nitride, silicon nitride Si3N4Or aluminium oxide Al2O3Dielectric substance composition.
8. a kind of autoregistration interconnected method for manufacturing high density mram according to claim 1 or 2 or 3 or 4, special
Sign is：Second dielectric cap layer preferentially uses plasma reinforced chemical vapour deposition, physical vapour deposition (PVD) or electricity
Beamlet evaporation process deposited oxide, silica, silicon oxynitride SiON, tantalum oxide Ta2O5Or hafnium oxide HfO2Dielectric substance
Composition.
9. a kind of autoregistration interconnected method for manufacturing high density mram according to claim 1 or 2 or 3 or 4, special
Sign is：The step of the second dielectric cap layer of the leveling include with chemically mechanical polishing, electrochemical mechanical polishing or from
Son grinding semi-conductor industry in flatening process, or such as reactive ion etching other removal techniques, to remove part
Second dielectric cap layer, partly to expose the first dielectric cap layer above cylindricality MTJ element.
10. a kind of autoregistration interconnected method for manufacturing high density mram according to claim 1 or 2 or 3 or 4,
It is characterized in that：The step of the first dielectric cap layer of the etching includes that dry etching, reactive ion etching, wet etching are gone
Except technique, the first dielectric cap layer being exposed through is removed, forms contact hole on cylindricality MTJ element to autoregistration.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810049346.9A CN108376690B (en) | 2018-01-18 | 2018-01-18 | Self-aligned interconnection method for manufacturing high-density MRAM |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810049346.9A CN108376690B (en) | 2018-01-18 | 2018-01-18 | Self-aligned interconnection method for manufacturing high-density MRAM |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN108376690A true CN108376690A (en) | 2018-08-07 |
| CN108376690B CN108376690B (en) | 2020-12-29 |
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| CN111162164A (en) * | 2018-11-08 | 2020-05-15 | 江苏鲁汶仪器有限公司 | Semiconductor device manufacturing method |
| WO2021053455A1 (en) * | 2019-09-16 | 2021-03-25 | International Business Machines Corporation | Encapsulation topography-assisted self-aligned mram top contact |
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| CN1820375A (en) * | 2003-06-24 | 2006-08-16 | 国际商业机器公司 | Self-aligned conductive lines for FET-based magnetic random access memory devices and method of forming it |
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| CN106058042A (en) * | 2010-01-15 | 2016-10-26 | 高通股份有限公司 | Magnetic tunnel junction (MTJ) on planarized electrode |
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| US20050221511A1 (en) * | 2004-04-01 | 2005-10-06 | Headway Technologies, Inc. | MRAM arrays with reduced bit line resistance and method to make the same |
| CN106058042A (en) * | 2010-01-15 | 2016-10-26 | 高通股份有限公司 | Magnetic tunnel junction (MTJ) on planarized electrode |
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| CN111162164A (en) * | 2018-11-08 | 2020-05-15 | 江苏鲁汶仪器有限公司 | Semiconductor device manufacturing method |
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| WO2021053455A1 (en) * | 2019-09-16 | 2021-03-25 | International Business Machines Corporation | Encapsulation topography-assisted self-aligned mram top contact |
| US11195993B2 (en) | 2019-09-16 | 2021-12-07 | International Business Machines Corporation | Encapsulation topography-assisted self-aligned MRAM top contact |
| GB2601100A (en) * | 2019-09-16 | 2022-05-18 | Ibm | Encapsulation topography-assisted self-aligned MRAM top contact |
| GB2601100B (en) * | 2019-09-16 | 2022-08-31 | Ibm | Encapsulation topography-assisted self-aligned MRAM top contact |
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