CN108369954A - Tunneling field-effect transistor and preparation method thereof - Google Patents
Tunneling field-effect transistor and preparation method thereof Download PDFInfo
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- 230000005641 tunneling Effects 0.000 title claims abstract description 71
- 238000002360 preparation method Methods 0.000 title abstract description 5
- 238000002353 field-effect transistor method Methods 0.000 title abstract description 4
- 239000002019 doping agent Substances 0.000 claims abstract description 131
- 239000000758 substrate Substances 0.000 claims abstract description 107
- 230000005669 field effect Effects 0.000 claims abstract description 64
- 238000000034 method Methods 0.000 claims description 31
- 239000000463 material Substances 0.000 claims description 27
- 238000004519 manufacturing process Methods 0.000 claims description 17
- 238000000059 patterning Methods 0.000 claims description 11
- 238000005530 etching Methods 0.000 claims description 8
- 238000010586 diagram Methods 0.000 description 19
- 229910052710 silicon Inorganic materials 0.000 description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 9
- 239000010703 silicon Substances 0.000 description 9
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 8
- 238000000231 atomic layer deposition Methods 0.000 description 6
- 238000005452 bending Methods 0.000 description 6
- -1 boron ion Chemical class 0.000 description 6
- 238000005229 chemical vapour deposition Methods 0.000 description 6
- 238000001451 molecular beam epitaxy Methods 0.000 description 6
- 239000004065 semiconductor Substances 0.000 description 6
- 238000009826 distribution Methods 0.000 description 4
- 229910001439 antimony ion Inorganic materials 0.000 description 3
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 229910052796 boron Inorganic materials 0.000 description 3
- 150000001875 compounds Chemical class 0.000 description 3
- 229910052732 germanium Inorganic materials 0.000 description 3
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 3
- 239000012212 insulator Substances 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000011065 in-situ storage Methods 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 239000012495 reaction gas Substances 0.000 description 2
- 229910000449 hafnium oxide Inorganic materials 0.000 description 1
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 1
- 238000010348 incorporation Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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Abstract
A kind of tunneling field-effect transistor and preparation method thereof, which includes substrate (10)；The source region (20) being set on substrate (10) and drain region (30), region between source region (20) and drain region (30) is raceway groove (40), pouch-type area (50) are formed between source region (20) and raceway groove (40), source region (20) and pouch-type area (50) include first kind dopant, and drain region (30) include the second class dopant；Grid stack layer (60), grid stack layer (60) are set to source region (20), on pouch-type area (50) and raceway groove (40)；Side wall (70), side wall (70) are set to the both sides of grid stack layer (60).The tunneling field-effect transistor can reduce the subthreshold swing of tunneling field-effect transistor.
Description
The present invention relates to technical field of semiconductors more particularly to a kind of tunneling field-effect transistor and preparation method thereof.
With metal-oxide semiconductor fieldeffect transistor (Metal-Oxide-Semiconductor Field-Effect Transistor, MOSFET) the continuous diminution of size, the power problems and reliability problem of device become an important factor for restricting integrated circuit development.In order to reduce the power consumption of integrated circuit, tunneling field-effect transistor (Tunnel Field-Effect Transistor, TFET extensive research) has been obtained, in TFET, carrier is in the mechanism injection channel of inter-band tunneling, subthreshold swing more smaller than MOSFET may be implemented, and (subthreshold swing refers to transistor under sub-threshold status, and drain current changes the variable quantity of required grid voltage when an order of magnitude.Subthreshold swing is smaller, and drain current is faster with grid voltage variation, and the switching characteristic of transistor is better.), so that the supply voltage of transistor reduces, and then it is substantially reduced the power consumption of transistor.
In online tunnelling TFET, there is biggish overlapping region between grid and source region, when applying certain voltage on grid, inter-band tunneling (referred to as threaded list is worn) occurs since this tunnelling is apart from very little perpendicular to the direction of grid in source region area, thus threaded list wears TFET that lesser subthreshold swing and biggish tunnelling current may be implemented.
However, since the doping concentration in channel is smaller, the energy band bending bigger than grid source overlay region can be generated under certain grid bias, therefore energy band will occur between source region and channel under lesser grid voltage and overlap, and generate inter-band tunneling (referred to as point tunnelling).Although putting, tunnelling current is smaller, and the cut-in voltage for putting tunnelling is smaller, and the tunnelling current that will lead to TFET in sub-threshold region changes slowly with grid voltage, and subthreshold swing is caused to increase.
Summary of the invention
The embodiment of the invention discloses a kind of tunneling field-effect transistors and preparation method thereof, can reduce the subthreshold swing of tunneling field-effect transistor.
First aspect of the embodiment of the present invention discloses a kind of tunneling field-effect transistor, comprising:
Substrate；
The source region being set on the substrate and drain region, region between the source region and the drain region is channel, pouch-type area is formed between the source region and the channel, the source region and the pouch-type area include first kind dopant, and the drain region includes the second class dopant；
Grid stack layer, the grid stack layer are set on the source region and the pouch-type area and the channel；
Side wall, the side wall are set to the two sides of the grid stack layer.
The embodiment of the present invention can reduce the subthreshold swing of tunneling field-effect transistor to delay the generation of the point tunnelling in tunneling field-effect transistor by forming pouch-type area (pocket) between source region and channel.
Optionally, the tunneling field-effect transistor further include:
Epitaxial layer, the epitaxial layer are set on the source region, the pouch-type area, the channel and the drain region；
The grid stack layer is set on the epitaxial layer.
The bending of energy band in the overlay region of grid source can be increased using epitaxial layer, to reduce subthreshold swing, increase tunnelling current.
Optionally, the grid stack layer includes gate dielectric layer and gate regions, and the gate dielectric layer is set on the epitaxial layer, and the gate regions are set on the gate dielectric layer.
Gate dielectric layer and gate regions are set on epitaxial layer, and grid bias changes the energy band bending degree in epitaxial layer through gate dielectric layer, and then influences the size of tunnelling current.
Wherein, the tunneling field-effect transistor further include:
Electrode, the electrode are correspondingly connected with the source region, the drain region and the gate regions, to form source electrode, drain electrode and grid.
Optionally, the first doping concentration of the first kind dopant that the source region includes is greater than the second doping concentration of the first kind dopant that the pouch-type area includes.
When the doping concentration of source region is greater than the doping concentration in pouch-type area, the tunnelling between source region and channel can be inhibited, since the doping concentration in pouch-type area is smaller, tunnelling can occur to avoid between pouch-type area and channel.
Optionally, the first kind dopant is p-type dopant, and the second class dopant is N-type dopant；Alternatively,
The first kind dopant is N-type dopant, and the second class dopant is p-type dopant.
The production method that second aspect of the embodiment of the present invention discloses a kind of tunneling field-effect transistor, comprising:
Substrate is provided；
Side over the substrate forms source region；
Pouch-type area is formed close to the side of the source region over the substrate；
The other side over the substrate forms drain region, wherein the region between the source region and the drain region is channel；
The source region and the pouch-type area include first kind dopant, and the drain region includes the second class dopant；
Grid stack layer is formed on the source region, the pouch-type area and the channel；
Side wall is formed in the two sides of the grid stack layer；
Advanced low-k materials are filled in the grid stack layer and the lateral wall circumference.
The embodiment of the present invention is used to delay the generation of the point tunnelling in tunneling field-effect transistor, can reduce the subthreshold swing of tunneling field-effect transistor by forming pouch-type area, pouch-type area (pocket) between source region and channel.
Optionally, after " other side over the substrate the forms drain region " step, and before " forming grid stack layer on the source region, the pouch-type area and the channel " step, the method also includes:
Epitaxial layer is formed on the source region, the pouch-type area, the channel and the drain region；
The grid stack layer is formed on said epitaxial layer there.
The bending of energy band in the overlay region of grid source can be increased using epitaxial layer, to reduce subthreshold swing, increase tunnelling current.
Optionally, the grid stack layer includes gate dielectric layer and gate regions, and " forming grid stack layer on said epitaxial layer there " step includes:
The gate dielectric layer is formed on said epitaxial layer there, the gate regions is formed on the gate dielectric layer, and pass through the region where grid stack layer described in lithographic definition.
Wherein, the method also includes:
The corresponding source region, the drain region and the gate regions are respectively formed source electrode, drain electrode and grid, and the source electrode, the drain electrode and the grid are connect with the source region, the drain region and the gate regions respectively.
Optionally, described " side formed source region " the over the substrate step includes:
A surface over the substrate forms the first mask layer；
First mask layer is patterned, the side of first mask layer, the first mask layer after being patterned are removed, so that the substrate exposes the first predeterminable area；
The doping of first kind dopant is carried out according to the first doping concentration in first predeterminable area, to form the source region.
Optionally, described " side formed source region " the over the substrate step includes:
A surface over the substrate forms the first mask layer；
First mask layer is patterned, the side of first mask layer, the first mask layer after being patterned are removed, so that the substrate exposes the first predeterminable area；
The substrate is performed etching in first predeterminable area, forms the first etch areas；
In the material that the first etch areas epitaxial growth includes the first kind dopant, to form the source region.
Optionally, described " forming pouch-type area close to the side of the source region over the substrate " step includes:
It carries out the first kind dopant according to the second doping concentration in the region of first mask layer of first predeterminable area after the patterning to adulterate, to form the pouch-type area.
Optionally, described " other side formed drain region " the over the substrate step includes:
The first mask layer after removing the patterning, one surface over the substrate form the second mask layer；
Second mask layer is patterned, the side of second mask layer far from the source region, the second mask layer after being patterned are removed, so that the substrate exposes the second predeterminable area, second predeterminable area is not overlapped with first predeterminable area；
The doping of the second class dopant is carried out in second predeterminable area, to form the drain region.
Optionally, described " other side formed drain region " the over the substrate step includes:
The first mask layer after removing the patterning, one surface over the substrate form the second mask layer；
Second mask layer is patterned, the side of second mask layer far from the source region, the second mask layer after being patterned are removed, so that the substrate exposes the second predeterminable area, second predeterminable area is not overlapped with first predeterminable area；
Perform etching the substrate in second predeterminable area, forms the second etch areas；
In the material that the second etch areas epitaxial growth includes the second class dopant, to form the drain region.
Optionally, described " forming epitaxial layer on the source region, the pouch-type area, the channel and the drain region " step includes:
The second mask layer after removing the patterning removes the oxide layer on one surface on the substrate, forms the epitaxial layer on the source region, the pouch-type area, the channel and the drain region.
Optionally, the first concentration of the first kind dopant that the source region includes is greater than the second concentration of the first kind dopant that the pouch-type area includes.
When the doping concentration of source region is greater than the doping concentration in pouch-type area, the tunnelling between source region and channel can be inhibited, since the doping concentration in pouch-type area is smaller, tunnel can occur to avoid between pouch-type area and channel
It wears.
Optionally, the first kind dopant is p-type dopant, and the second class dopant is N-type dopant；Alternatively,
The first kind dopant is N-type dopant, and the second class dopant is p-type dopant.
In the embodiment of the present invention, by forming pouch-type area between source region and channel, causes the tunneling path length of a tunnelling to increase, to reduce a tunnelling current, and then can reduce the subthreshold swing of tunneling field-effect transistor.
To describe the technical solutions in the embodiments of the present invention more clearly, the drawings to be used in the embodiments are briefly described below, apparently, drawings in the following description are only some embodiments of the invention, for those of ordinary skill in the art, without creative efforts, it is also possible to obtain other drawings based on these drawings.
Fig. 1 is a kind of cross-sectional view of tunneling field-effect transistor disclosed by the embodiments of the present invention；
Fig. 2 is the energy band distribution schematic diagram in a kind of tunneling field-effect transistor disclosed by the embodiments of the present invention；
Fig. 3 is the cross-sectional view of another tunneling field-effect transistor disclosed by the embodiments of the present invention；
Fig. 4 is a kind of flow diagram of the production method of tunneling field-effect transistor disclosed by the embodiments of the present invention；
Fig. 5 is that the schematic diagram of substrate is provided in a kind of process of the production method of tunneling field-effect transistor disclosed by the embodiments of the present invention；
Fig. 6 is the schematic diagram that source region is formed in a kind of process of the production method of tunneling field-effect transistor disclosed by the embodiments of the present invention；
Fig. 7 is the schematic diagram that pouch-type area is formed in a kind of process of the production method of tunneling field-effect transistor disclosed by the embodiments of the present invention；
Fig. 8 is the schematic diagram that drain region is formed in a kind of process of the production method of tunneling field-effect transistor disclosed by the embodiments of the present invention；
Fig. 9 is shape in a kind of process of the production method of tunneling field-effect transistor disclosed by the embodiments of the present invention
At grid stack layer and the schematic diagram of side wall；
Figure 10 is the schematic diagram that advanced low-k materials are filled in a kind of process of the production method of tunneling field-effect transistor disclosed by the embodiments of the present invention；
Figure 11 is that source electrode, grid and the schematic diagram of drain electrode are formed in a kind of process of the production method of tunneling field-effect transistor disclosed by the embodiments of the present invention；
Figure 12 is the flow diagram of the production method of another tunneling field-effect transistor disclosed by the embodiments of the present invention；
Figure 13 is the schematic diagram of formation epitaxial layer in the process of the production method of another tunneling field-effect transistor disclosed by the embodiments of the present invention；
Figure 14 is the schematic diagram of formation grid stack layer and side wall in the process of the production method of another tunneling field-effect transistor disclosed by the embodiments of the present invention；
Figure 15 is the schematic diagram of filling advanced low-k materials in the process of the production method of another tunneling field-effect transistor disclosed by the embodiments of the present invention；
Figure 16 is formation source electrode, grid and the schematic diagram of drain electrode in the process of the production method of another tunneling field-effect transistor disclosed by the embodiments of the present invention.
Following will be combined with the drawings in the embodiments of the present invention, and technical scheme in the embodiment of the invention is clearly and completely described, it is clear that the described embodiment is only a part of the embodiment of the present invention, instead of all the embodiments.Based on the embodiments of the present invention, every other embodiment obtained by those of ordinary skill in the art without making creative efforts, shall fall within the protection scope of the present invention.
Referring to Fig. 1, Fig. 1 is a kind of cross-sectional view of tunneling field-effect transistor disclosed by the embodiments of the present invention.Tunneling field-effect transistor 1 includes substrate 10, source region 20, drain region 30, channel 40, pouch-type area 50, grid stack layer 60 and side wall 70, wherein, source region 20, drain region 30, channel 40, pouch-type area 50, grid stack layer 60 and side wall 70 are secured directly or indirectly on substrate 10.Source region 20 and drain region 30 are set on substrate 10, and the region between source region 20 and drain region 30 is channel 40, and pouch-type area 50 is formed between source region 20 and channel 40, and source region 20 and pouch-type area 50 include first kind dopant, and drain region 30 includes the second class dopant；
Grid stack layer 60 is set on source region 20, pouch-type area 50 and channel 40；Side wall 70 is set to the two sides of grid stack layer 60.
In the embodiment of the present invention, substrate 10 can be silicon (Si) substrate.In other embodiments, any one in substrate 10 or germanium (Ge) or the silicon (Silicon on Insulator, SOI) on SiGe, Jia Shendeng IV race or iii-v or the binary or ternary compound semiconductor of group IV-VI, insulating substrate or the SiGe in insulating substrate.
Pouch-type area (pocket) 50 is used to delay the generation of the point tunnelling in tunneling field-effect transistor (Tunnel Field-Effect Transistor, TFET), can reduce the subthreshold swing of TFFT.In general, the volume in pouch-type area 50 is much smaller than the volume of source region 20.
The working principle in pouch-type area 50 is illustrated below in conjunction with Fig. 2.Please refer to Fig. 2, Fig. 2 is the energy band distribution schematic diagram in a kind of tunneling field-effect transistor disclosed by the embodiments of the present invention, energy band distribution schematic diagram when solid line in Fig. 2 is no pouch-type area 50, in the source region (Source) of tunneling field-effect transistor, channel (Channel) and drain region (Drain)；Dotted line in Fig. 2 is when having pouch-type area 50, the energy band distribution schematic diagram in the source region (Source) of tunneling field-effect transistor, channel (Channel) and drain region (Drain).In Fig. 2, abscissa is position (position), ordinate is energy (Energy), and Ec is conduction band energy, and Ev is Valence-band, as can be seen from Figure 2, after increasing pouch-type area 50, the energy band in channel by the position of source area, which is bent, to be reduced, and the tunneling path length of a tunnelling is caused to increase (d2 > d1), to reduce a tunnelling current, and then it can reduce the subthreshold swing of tunneling field-effect transistor.
In one embodiment, the material of channel 40 is identical as the material of substrate 10.
In one embodiment, source region 20 can be formed by following manner: forming the first mask layer (hard mask) on a surface on substrate 10, the first predeterminable area not covered by the first mask layer is exposed on a surface of substrate 10.Mask layer has the function of that the surface region for protecting its substrate covered is not doped; therefore; when being doped to the surface of the substrate of setting mask layer; it will not be doped by surface and the surface part below for the substrate that mask layer covers, and be not doped due to there is no protection then by the surface for the substrate that mask layer covers.First kind dopant is mixed according to the first doping concentration in above-mentioned first predeterminable area, source region 20 can be formed.
In one embodiment, on the basis of forming source region 20, pouch-type area 50 can be formed by following manner: in the first predeterminable area close to the region of the first mask layer according to the incorporation first kind dopant doping of the second doping concentration, to form pouch-type area 50.
In one embodiment, on the basis of forming pouch-type area 50, drain region 30 can be formed by following manner: form the second mask layer on a surface on substrate 10, expose the second predeterminable area not covered by the second mask layer on a surface of substrate 10, wherein, second predeterminable area is not overlapped with the first predeterminable area, the doping of the second class dopant is carried out in the second predeterminable area, to form drain region 30.
Wherein, grid stack layer 60 may include gate dielectric layer 601 and gate regions 602, and gate dielectric layer 601 is set on source region 20, pouch-type area 50 and channel 40, and gate regions 602 are set on gate dielectric layer 601.Gate dielectric layer 601 may include the dielectric of the high dielectric constants such as silica and hafnium oxide.Side wall 70 can be used for for being isolated with source region 20, drain region 30 gate regions 602.
In one embodiment, the first doping concentration of the first kind dopant that source region 20 includes is greater than the second doping concentration of the first kind dopant that pouch-type area 50 includes.When the doping concentration of source region 20 is greater than the doping concentration in pouch-type area 50, the tunnelling between source region 20 and channel 40 can be inhibited, since the doping concentration in pouch-type area 50 is smaller, tunnelling can occur to avoid between pouch-type area 50 and channel 40.
Tunneling field-effect transistor further includes electrode, and electrode is correspondingly connected with source region 20, drain region 30 and gate regions 602, to form source electrode 80, drain electrode 90 and grid 100.There is biggish overlapping area between grid 100 and source region 20, applies certain bias on grid 100, inter-band tunneling can occur perpendicular to grid direction in source region 20.Wherein, advanced low-k materials 110 are filled with around source electrode 80 and drain electrode 90.
Optionally, first kind dopant is p-type dopant, and the second class dopant is N-type dopant；Alternatively,
First kind dopant is N-type dopant, and the second class dopant is p-type dopant.
Wherein, p-type dopant may include boron ion, BF2At least one of；N-type dopant may include at least one of phosphonium ion, arsenic ion, antimony ion.When first kind dopant is p-type dopant, and the second class dopant is N-type dopant, i.e., source region 20 is p-type doping, and drain region 30 is n-type doping, and tunneling field-effect transistor 1 is N-type tunneling field-effect transistor (NTFFT) at this time；When first kind dopant is N-type dopant, and the second class dopant is p-type dopant, i.e., source region 20 is n-type doping, and drain region 30 is mixed for p-type
Miscellaneous, tunneling field-effect transistor 1 is p-type tunneling field-effect transistor (PTFFT) at this time.For NTFFT, the voltage signal that drain region 30 loads when working is forward bias voltage, and the voltage signal that source region 20 loads when working is negative sense bias voltage.For PTFFT, the voltage signal that drain region 30 loads when working is negative sense bias voltage, and the voltage signal that source region 20 loads when working is forward bias voltage.
In the embodiment of the present invention, by forming pouch-type area 50 between source region 20 and channel 40, causes the tunneling path length of a tunnelling to increase, to reduce a tunnelling current, and then can reduce the subthreshold swing for wearing field effect transistor.
Please refer to Fig. 3, Fig. 3 is the cross-sectional view of another tunneling field-effect transistor disclosed by the embodiments of the present invention, Fig. 3 is advanced optimized on the basis of Fig. 1, as shown in Figure 3, tunneling field-effect transistor 1 includes substrate 10, source region 20, drain region 30, channel 40, pouch-type area 50, grid stack layer 60, side wall 70 and epitaxial layer 120, wherein, source region 20, drain region 30, channel 40, pouch-type area 50, grid stack layer 60, side wall 70 and epitaxial layer 120 are secured directly or indirectly on substrate 10.Source region 20 and drain region 30 are set on substrate 10, and the region between source region 20 and drain region 30 is channel 40, and pouch-type area 50 is formed between source region 20 and channel 40, and source region 20 and pouch-type area 50 include first kind dopant, and drain region 30 includes the second class dopant；Epitaxial layer 120 is set on source region 20, pouch-type area 50, channel 40 and drain region 30；Grid stack layer 60 is set on epitaxial layer 120；Side wall 70 is set to the two sides of grid stack layer 60.
In the embodiment of the present invention, substrate 10 can be silicon (Si) substrate.In other embodiments, any one in substrate 10 or germanium (Ge) or the silicon (Silicon on Insulator, SOI) on SiGe, Jia Shendeng IV race or iii-v or the binary or ternary compound semiconductor of group IV-VI, insulating substrate or the SiGe in insulating substrate.Side wall 70 can be used for protecting grid stack layer 60.
Pouch-type area (pocket) 50 is for delaying tunneling field-effect transistor (Tunnel Field-Effect Transistor, TFET the generation of the point tunnelling in) can reduce the subthreshold swing of TFFT (much smaller than 60mV/dec).The working principle in pouch-type area 50 refers to the description of above-mentioned Fig. 2.
Epitaxial layer 120 can use chemical vapor deposition (Chemical Vapor Deposition, CVD), atomic layer deposition (Atomic layer deposition, ALD), molecular beam epitaxy (Molecular Beam
Epitaxy, MBE) etc. formed, epitaxial layer 120 can be undope either mixed with the second class dopant (with drain region 30 mix type dopant it is identical).The bending of energy band in the overlay region of grid source can be increased using epitaxial layer, to reduce subthreshold swing, increase tunnelling current.
Wherein, grid stack layer 60 may include gate dielectric layer 601 and gate regions 602, and gate dielectric layer 601 is set on epitaxial layer 120, and gate regions 602 are set on gate dielectric layer 601.
Tunneling field-effect transistor further includes electrode, and electrode is correspondingly connected with source region 20, drain region 30 and gate regions 602, to form source electrode 80, drain electrode 90 and grid 100.There is biggish overlapping area between grid 100 and source region 20, applies certain bias on grid 100, inter-band tunneling can occur between source region 20 and epitaxial layer 120.Wherein, advanced low-k materials 110 are filled with around source electrode 80 and drain electrode 90.
In one embodiment, the first doping concentration of the first kind dopant that source region 20 includes is greater than the second doping concentration of the first kind dopant that pouch-type area 50 includes.When the doping concentration of source region 20 is greater than the doping concentration in pouch-type area 50, the tunnelling between source region 20 and channel 40 can be inhibited, since the doping concentration in pouch-type area 50 is smaller, tunnelling can occur to avoid between pouch-type area 50 and channel 40.
Optionally, first kind dopant is p-type dopant, and the second class dopant is N-type dopant；Alternatively,
First kind dopant is N-type dopant, and the second class dopant is p-type dopant.
Wherein, p-type dopant may include boron ion BF2At least one of；N-type dopant may include at least one of phosphonium ion, arsenic ion, antimony ion.
The forming method of source region 20, drain region 30 and pouch-type area 50 in Fig. 3 is identical as Fig. 1, and details are not described herein again.
In the embodiment of the present invention, by forming pouch-type area 50 between source region 20 and channel 40, causes the tunneling path length of a tunnelling to increase, to reduce a tunnelling current, and then can reduce the subthreshold swing of tunneling field-effect transistor.
Referring to Fig. 4, Fig. 4 is a kind of flow diagram of the production method of tunneling field-effect transistor disclosed by the embodiments of the present invention, as shown in figure 4, this method comprises the following steps.
401, substrate 10 is provided.
As shown in figure 5, substrate 10 can be silicon (Si) substrate.In other embodiments, any one in substrate 10 or germanium (Ge) or the silicon (Silicon on Insulator, SOI) on SiGe, Jia Shendeng IV race or iii-v or the binary or ternary compound semiconductor of group IV-VI, insulating substrate or the SiGe in insulating substrate.
402, the side on substrate 10 forms source region 20.
As shown in fig. 6, can be doped by way of ion implanting, for example, the side on substrate 10 forms the mode of source region 20 specifically: a surface on substrate 10 forms the first mask layer；The first mask layer is patterned, the side of the first mask layer, the first mask layer (a in Fig. 6) after being patterned are removed, so that substrate 10 exposes the first predeterminable area；The doping of first kind dopant is carried out to form source region 20 according to the first doping concentration in the first predeterminable area.It can use the position that lithographic definition goes out the first predeterminable area, it is convenient that first predeterminable area is doped, to form source region 20.
Source region can also be formed by way of etching, for example, on substrate 10 a surface forms the first mask layer；The first mask layer is patterned, the side of the first mask layer, the first mask layer (a in Fig. 6) after being patterned are removed, so that substrate 10 exposes the first predeterminable area；Substrate 10 is performed etching in the first predeterminable area, form the first etch areas, the first etch areas epitaxial growth include first kind dopant material (wherein, the material of source region can be identical with substrate, can also be different, such as, the material of substrate is Si, the material of source region can be Si, be also possible to SiGe), to form source region 20.Doping in situ is carried out while epitaxial growth, for example, first kind dopant is then added in reaction gas when carrying out epitaxial growth with chemical vapor deposition, forms source region.It can use the position that lithographic definition goes out the first predeterminable area, it is convenient that first predeterminable area is doped, to form source region 20.
403, pouch-type area 50 is formed by the side of source area 20 on substrate 10.
As shown in Figure 7, the mode in pouch-type area 50 is formed by the side of source area 20 on substrate 10 specifically: after executing step 402, the doping of first kind dopant is carried out according to the second doping concentration in the region of first mask layer (a in Fig. 7) of first predeterminable area after patterning, to form pouch-type area.As shown in fig. 7, first kind dopant can be injected in the intersection of source region 20 and channel 40 using certain inclination angle, to form pouch-type area.
404, the other side on substrate 10 forms drain region 30, and the region between source region 20 and drain region 30 is channel 40；Wherein, source region 20 and pouch-type area 50 include first kind dopant, and drain region 30 includes the second class dopant.
As shown in Figure 8, drain region can be doped by way of ion implanting, for example, the other side on substrate 10 forms the mode in drain region 30 specifically: after executing step 403, the first mask layer after removing patterning, a surface on substrate 10 form the second mask layer；The second mask layer is patterned, side of second mask layer far from source region, the second mask layer (b in Fig. 8) after being patterned are removed, so that substrate 10 exposes the second predeterminable area, the second predeterminable area is not overlapped with the first predeterminable area；The doping of the second class dopant is carried out in the second predeterminable area, to form drain region 30.It can use the position that lithographic definition goes out the second predeterminable area, it is convenient that second predeterminable area is doped, to form drain region 30.
Drain region can also be formed by way of etching, for example, the other side on substrate 10 forms the mode in drain region 30 specifically: after executing step 403, remove the first mask layer after patterning, a surface on substrate 10 forms the second mask layer；The second mask layer is patterned, side of second mask layer far from source region, the second mask layer (b in Fig. 8) after being patterned are removed, so that substrate 10 exposes the second predeterminable area, the second predeterminable area is not overlapped with the first predeterminable area；Perform etching substrate 10 in the second predeterminable area, forms the second etch areas；It include the material (wherein, the material of source region can be identical with substrate, can also be different, for example, the material of substrate is Si, the material of source region can be Si, be also possible to SiGe) of the second class dopant to form drain region 30 in the second etch areas epitaxial growth.Doping in situ is carried out while epitaxial growth, for example, the second class dopant is then added in reaction gas when carrying out epitaxial growth with chemical vapor deposition, forms drain region.It can use the position that lithographic definition goes out the second predeterminable area, it is convenient that second predeterminable area is doped, to form drain region 30.
Wherein, the first doping concentration of the first kind dopant that source region 20 includes is greater than the second doping concentration of the first kind dopant that pouch-type area 50 includes.When the doping concentration of source region 20 is greater than the doping concentration in pouch-type area 50, the tunnelling between source region 20 and channel 40 can be inhibited, simultaneously because the doping concentration in pouch-type area 50 is smaller, tunnelling can occur to avoid between pouch-type area 50 and channel 40.
Wherein, first kind dopant is p-type dopant, and the second class dopant is N-type dopant；Alternatively,
First kind dopant is N-type dopant, and the second class dopant is p-type dopant.
For example, source region 20 and pouch-type area 50 mix p-type dopant, drain region 30 mixes N-type dopant；Alternatively, source region 20 and pouch-type area 50 mix N-type dopant, drain region 30 mixes p-type dopant.
P-type dopant may include boron ion, BF2At least one；N-type dopant may include at least one of phosphonium ion, arsenic ion, antimony ion.
405, grid stack layer 60 is formed on source region 20, pouch-type area 50 and channel 40.
Grid stack layer 60 is formed as shown in figure 9, can deposit on source region 20, pouch-type area 50 and channel 40.Wherein, grid stack layer 60 includes gate dielectric layer 601 and gate regions 602.Specifically, can be sequentially depositing gate dielectric layer 601 and gate regions 602 on source region 20, pouch-type area 50 and channel 40, gate regions 602 are set on gate dielectric layer 601, and the position where grid stack layer is then defined using the method for photoetching.
406, side wall 70 is formed in the two sides of grid stack layer 60.
As shown in figure 9, forming side wall 70 in the two sides of grid stack layer 60, side wall 70 can be used for for being isolated with source region 20, drain region 30 gate regions 602.
407, advanced low-k materials 110 are filled around grid stack layer 60 and side wall 90.
Optionally, after executing step 408, following steps can also be performed:
Corresponding source region 20, drain region 30 and gate regions 602 are respectively formed source electrode 80, drain electrode 90 and grid 100, and source electrode 80, drain electrode 90 and grid 100 are connect with source region 20, drain region 30 and gate regions 602 respectively.
As shown in figure 11, the first perforation of corresponding source region 20 can be opened up on advanced low-k materials 110, source electrode 80 passes through the first perforation and connects source region 20；Second perforation in corresponding drain region 30 is opened up on advanced low-k materials 110, drain electrode 90 passes through the second perforation and connects drain region 30；Grid 100 is formed on gate regions 602.
Figure 12 is please referred to, Figure 12 is the flow diagram of the production method of another tunneling field-effect transistor disclosed by the embodiments of the present invention, and as shown in figure 12, this method comprises the following steps.
1201, substrate 10 is provided.
1202, the side on substrate 10 forms source region 20.
1203, pouch-type area 50 is formed by the side of source area 20 on substrate 10.
1204, the other side on substrate 10 forms drain region 30, and the region between source region 20 and drain region 30 is channel 40；Wherein, source region 20 and pouch-type area 50 include first kind dopant, and drain region 30 includes the second class dopant.
1205, epitaxial layer 120 is formed on source region 20, pouch-type area 50, channel 40 and drain region 30.
As shown in figure 13, after source region 20, drain region 30, channel 40 and pouch-type area 50 all make, epitaxial layer 120 can be formed on source region 20, pouch-type area 50, channel 40 and drain region 30.Before executing step 406, thin oxide layer may be will form on the surface of source region 20, pouch-type area 50 and drain region 30, if foring thin oxide layer, need first to remove thin oxide layer, then form epitaxial layer 120.
Epitaxial layer 120 can use chemical vapor deposition (Chemical Vapor Deposition, CVD), atomic layer deposition (Atomic layer deposition, ALD), molecular beam epitaxy (Molecular Beam Epitaxy,) etc. MBE formed, the material of epitaxial layer 120 can be substrate of the substrate to undope either mixed with the second class dopant (identical as the type dopant that drain region 30 mixes).The bending of energy band in the overlay region of grid source can be increased using epitaxial layer, to reduce subthreshold swing, increase tunnelling current.
1206, grid stack layer 60 is formed on epitaxial layer 120.
1207, side wall 70 is formed in the two sides of grid stack layer 60.
As shown in figure 14, grid stack layer 60 can be formed on epitaxial layer 120, wherein grid stack layer 60 includes gate dielectric layer 601 and gate regions 602.Specifically, can be sequentially depositing gate dielectric layer 601 and gate regions 602 on epitaxial layer 120, gate regions 602 are set on gate dielectric layer 601, then go out grid stack layer overlay area using lithographic definition.As shown in figure 14, side wall 70 is formed in the two sides of grid stack layer 60, side wall 70 can be used for protecting grid stack layer 60.
1208, advanced low-k materials 110 are filled around grid stack layer 60 and side wall 70.
Optionally, after executing step 1208, following steps can also be performed:
Corresponding source region 20, drain region 30 and gate regions 602 are respectively formed source electrode 80, drain electrode 90 and grid 100, and source electrode 80, drain electrode 90 and grid 100 are connect with source region 20, drain region 30 and gate regions 602 respectively.
As shown in figure 16, the first perforation of corresponding source region 20 can be opened up on advanced low-k materials 110, source electrode 80 passes through the first perforation and connects source region 20；Corresponding drain region 30 is opened up on advanced low-k materials 110
Second perforation, drain electrode 90 pass through the second perforation and connect drain region 30；Grid 100 is formed on gate regions 602.
Step 1201 to step 1204 in Figure 12, which may refer to step 401 described in Fig. 4 to step 404, step 1207 and step 1208, may refer to step 406 described in Fig. 4 and step 407, and details are not described herein again.
The above disclosure is only the preferred embodiments of the present invention, and of course, the scope of rights of the present invention cannot be limited by this, therefore protection scope of the present invention should be subject to the protection scope in claims.
Claims (18)
- A kind of tunneling field-effect transistor characterized by comprisingSubstrate；The source region being set on the substrate and drain region, region between the source region and the drain region is channel, pouch-type area is formed between the source region and the channel, the source region and the pouch-type area include first kind dopant, and the drain region includes the second class dopant；Grid stack layer, the grid stack layer are set on the source region, the pouch-type area and the channel；Side wall, the side wall are set to the two sides of the grid stack layer.
- Tunneling field-effect transistor according to claim 1, which is characterized in that the tunneling field-effect transistor further include:Epitaxial layer, the epitaxial layer are set on the source region, the pouch-type area, the channel and the drain region；The grid stack layer is set on the epitaxial layer.
- Tunneling field-effect transistor according to claim 2, which is characterized in that the grid stack layer includes gate dielectric layer and gate regions, and the gate dielectric layer is set on the epitaxial layer, and the gate regions are set on the gate dielectric layer.
- Tunneling field-effect transistor according to claim 3, which is characterized in that the tunneling field-effect transistor further include:Electrode, the electrode are correspondingly connected with the source region, the drain region and the gate regions, to form source electrode, drain electrode and grid.
- Tunneling field-effect transistor according to claim 1-4, which is characterized in thatFirst doping concentration of the first kind dopant that the source region includes is greater than the pouch-type area Second doping concentration of first kind dopant.
- Tunneling field-effect transistor according to claim 1-5, which is characterized in thatThe first kind dopant is p-type dopant, and the second class dopant is N-type dopant；Alternatively,The first kind dopant is N-type dopant, and the second class dopant is p-type dopant.
- A kind of production method of tunneling field-effect transistor characterized by comprisingSubstrate is provided；Side over the substrate forms source region；Pouch-type area is formed close to the side of the source region over the substrate；The other side over the substrate forms drain region, wherein the region between the source region and the drain region is channel；The source region and the pouch-type area include first kind dopant, and the drain region includes the second class dopant；Grid stack layer is formed on the source region, the pouch-type area and the channel；Side wall is formed in the two sides of the grid stack layer；Advanced low-k materials are filled in the grid stack layer and the lateral wall circumference.
- According to the method for claim 7, it is characterized in that, after " other side over the substrate the forms drain region " step, and before " forming grid stack layer on the source region, the pouch-type area and the channel " step, the method also includes:Epitaxial layer is formed on the source region, the pouch-type area, the channel and the drain region；The grid stack layer is formed on said epitaxial layer there.
- According to the method described in claim 8, " forming grid stack layer on said epitaxial layer there " step includes: it is characterized in that, the grid stack layer includes gate dielectric layer and gate regionsThe gate dielectric layer is formed on said epitaxial layer there, the gate regions is formed on the gate dielectric layer, and pass through the region where grid stack layer described in lithographic definition.
- According to the method described in claim 9, it is characterized in that, the method also includes:The corresponding source region, the drain region and the gate regions are respectively formed source electrode, drain electrode and grid, and the source electrode, the drain electrode and the grid are connect with the source region, the drain region and the gate regions respectively.
- According to the described in any item methods of claim 8-10, which is characterized in that " side formed source region " the over the substrate step includes:A surface over the substrate forms the first mask layer；First mask layer is patterned, the side of first mask layer, the first mask layer after being patterned are removed, so that the substrate exposes the first predeterminable area；The doping of first kind dopant is carried out according to the first doping concentration in first predeterminable area, to form the source region.
- According to the described in any item methods of claim 8-10, which is characterized in that " side formed source region " the over the substrate step includes:A surface over the substrate forms the first mask layer；First mask layer is patterned, the side of first mask layer, the first mask layer after being patterned are removed, so that the substrate exposes the first predeterminable area；The substrate is performed etching in first predeterminable area, forms the first etch areas；In the material that the first etch areas epitaxial growth includes the first kind dopant, to form the source region.
- Method according to claim 11 or 12, which is characterized in that it is described " over the substrate Pouch-type area is formed close to the side of the source region " step includes:It carries out the first kind dopant according to the second doping concentration in the region of first mask layer of first predeterminable area after the patterning to adulterate, to form the pouch-type area.
- According to the method for claim 13, which is characterized in that " other side formed drain region " the over the substrate step includes:The first mask layer after removing the patterning, one surface over the substrate form the second mask layer；Second mask layer is patterned, the side of second mask layer far from the source region, the second mask layer after being patterned are removed, so that the substrate exposes the second predeterminable area, second predeterminable area is not overlapped with first predeterminable area；The doping of the second class dopant is carried out in second predeterminable area, to form the drain region.
- According to the method for claim 13, which is characterized in that " other side formed drain region " the over the substrate step includes:The first mask layer after removing the patterning, one surface over the substrate form the second mask layer；Second mask layer is patterned, the side of second mask layer far from the source region, the second mask layer after being patterned are removed, so that the substrate exposes the second predeterminable area, second predeterminable area is not overlapped with first predeterminable area；Perform etching the substrate in second predeterminable area, forms the second etch areas；In the material that the second etch areas epitaxial growth includes the second class dopant, to form the drain region.
- Method according to claim 14 or 15, which is characterized in that " forming epitaxial layer on the source region, the pouch-type area, the channel and the drain region " step includes:The second mask layer after removing the patterning removes the oxide layer on one surface on the substrate, forms the epitaxial layer on the source region, the pouch-type area, the channel and the drain region.
- According to the described in any item methods of claim 7-16, which is characterized in that the first concentration of the first kind dopant that the source region includes is greater than the second concentration of the first kind dopant that the pouch-type area includes.
- According to the described in any item methods of claim 7-17, which is characterized in thatThe first kind dopant is p-type dopant, and the second class dopant is N-type dopant；Alternatively,The first kind dopant is N-type dopant, and the second class dopant is p-type dopant.
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| CN102544104A (en) * | 2012-01-12 | 2012-07-04 | 清华大学 | High-voltage resistant tunneling transistor and preparation method thereof |
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| US20150243769A1 (en) * | 2014-02-24 | 2015-08-27 | Kabushiki Kaisha Toshiba | Semiconductor device and manufacturing method thereof |
| US20150364582A1 (en) * | 2014-06-16 | 2015-12-17 | Kabushiki Kaisha Toshiba | Semiconductor device |
| US20160079415A1 (en) * | 2014-09-11 | 2016-03-17 | Kabushiki Kaisha Toshiba | Semiconductor device and manufacturing method thereof |
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| CN102623495A (en) * | 2012-04-09 | 2012-08-01 | 北京大学 | Tunneling field effect transistor with multi-doping pocket structure and manufacturing method for tunneling field effect transistor |
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