CN108352422A - 倾斜光电探测器单元 - Google Patents
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Abstract
在所描述实例中,一种光电探测器单元(100)包含具有半导体表面层(110)的衬底(105),和所述半导体表面层(110)中的沟槽(115)。所述沟槽(115)具有包含第一倾斜侧壁(115a)和第二倾斜侧壁(115b)的倾斜侧壁。pn结、PIN结构或光电晶体管包含有源p区和有源n区(122),其形成包含沿所述第一倾斜侧壁(115a)提供第一光电探测器元件(120a)的第一结和沿所述第二倾斜侧壁(115b)提供第二光电探测器元件(120b)的与所述第一结间隔开的第二结的结。至少p型阳极触点(110a)和至少n型阴极触点(122a、122b)与所述第一光电探测器元件(120a)和第二光电探测器元件(120b)的所述有源p区和有源n区(122)接触。所述倾斜侧壁(115a、115b)提供外部暴露或光学透明表面,用于将入射光传递到所述第一光电探测器元件(120a)和第二光电探测器元件(120b)以探测入射光。
Description
技术领域
本发明涉及包含用于入射光束的角度探测的光电探测器。
背景技术
光电二极管是将光转换成电流的光探测半导体装置。光电二极管通常包括pn结或PIN结构,其包括插在p型半导体区与n型半导体区之间的未掺杂的本征半导体区。电流是在当具有至少半导体的带隙能量的光子被吸收在光电二极管中时通过光子照射产生的。当此类充足能量的光子撞击光电二极管时,价带电子被激发到导带从而在价带中的其位置留下空穴,由此形成电子-空穴对。
为探测所关注的入射光束的角度和方向,导引透镜通常与数个单独的光电二极管一起使用。常规的光电二极管具有平坦的接收表面,有时其上具有抗反射(AR)涂层。一个已知的布置具有多个光电二极管芯片,其中各光电二极管芯片放置成探测不同光子的角度范围。在这个布置中,为了所探测角度的准确度,各个单独的光电二极管需要彼此准确地对准。
发明内容
所描述实例包含具有倾斜侧壁结构的基于沟槽的集成光电探测器单元,所述倾斜侧壁结构对准单元中的各个光电探测器元件,使得与用于探测入射光光束的角度和方向的常规解决方案一样,不需要对准光电探测器元件的对准步骤。所描述的倾斜光电探测器单元是具有单个合并结构的集成光电探测器单元,因为各个细胞中的光电探测器元件均在同一沟槽中形成。
在所描述实例中,光电探测器单元包含具有半导体表面层的衬底和在半导体表面层中形成的沟槽。沟槽具有包含第一倾斜侧壁和第二倾斜侧壁的倾斜侧壁。pn结、PIN结构或光电晶体管包含有源p区和有源n区,所述有源n区形成包含沿第一倾斜侧壁提供第一光电探测器元件的第一结和沿第二倾斜侧壁提供第二光电探测器元件的与第一结间隔开的第二结的结。至少p型阳极触点和至少n型阴极触点分别与第一光电探测器元件和第二光电探测器元件的有源p区和有源n区接触。倾斜侧壁提供外部暴露或光学透明表面,用于将入射光传递到第一光电探测器元件和第二光电探测器元件以探测入射光。
附图说明
图1A描绘根据实例实施例的具有顶部表面光电探测器触点的实例倾斜光电探测器单元。
图1B描绘根据实例实施例的在倾斜侧壁上具有光电探测器触点的实例倾斜光电探测器单元。
图1C描绘根据实例实施例的在包括双极光电晶体管元件的倾斜侧壁上具有光电探测器触点的实例倾斜光电探测器单元。
图2是根据实例实施例的展示形成倾斜光电探测器单元的实例方法中的步骤的流程图。
图3A和3B展示用于形成所描述的倾斜光电二极管单元或此类单元的阵列的基于LOCOS的方法中的数个步骤之后的横截面绘图。
图4A和4B展示用于形成所描述的倾斜光电二极管单元或此类单元的阵列的基于湿式硅蚀刻的方法中的数个步骤之后的横截面绘图。
图5A、5B和5C展示所描述的倾斜光电二极管单元的阵列的顶部透视图。
图6A和6B是展示归一化光生电流与入射角的模拟,其中图6A证明宽范围角度覆盖,例如±45°,具有关于左侧光电探测器和右侧光电探测器的单独PD电流与磁通角曲线,和关于所描述倾斜光电探测器单元的总的PD电流与磁通角,而图6b证明所描述的倾斜光电探测器元件在例如±45°的角度覆盖范围上为角度探测提供高灵敏度。
图7描绘用于不会涉及角度监测的所描述的倾斜光电探测器单元的光电探测器应用中的增强方向性效率的机构。
具体实施方式
所述附图未必按比例绘制。一些所说明的动作或事件可与其它动作或事件以不同次序和/或同时发生。此外,实施根据本说明书的方法可能不需要一些说明的动作或事件。
图1A描绘根据实例实施例的具有穿过表面介电层(例如,氧化硅)121的顶部侧面平坦表面光电探测器触点的实例倾斜光电探测器单元100。光电探测器单元100通常用于例如通过使用实施光通角对比光电探测器电流的存储曲线(或关系)(参看下文所描述的图6A)的计算装置来确定所接收入射光的入射角(θ)。
光电探测器单元100包含具有半导体表面层110的衬底105。在本文中所描述的实施例中,衬底105和半导体表面层110两者均为p型。块状衬底材料可提供衬底105和半导体表面层110两者,或衬底105可包括其上具有外延层以提供半导体表面层110的块状衬底材料。沟槽115是在半导体表面层110中形成。沟槽可通过湿式蚀刻且在一些应用中通过干式蚀刻(例如深度反应性离子蚀刻(DRIE))形成。实例衬底材料包含可被湿式碱性(基于氢氧化物)刻面蚀刻的硅和可被DRIE蚀刻的砷化镓(GaAs)。
沟槽115具有包含第一倾斜侧壁115a和第二倾斜侧壁115b的倾斜侧壁。1条轴线的探测器的沟槽中具有2个倾斜侧壁,且对于2条轴线的探测器,沟槽115具有4个倾斜侧壁。如本文中所使用,“倾斜侧壁”是指相对于半导体表面层110的顶部处的表面法线呈15到75度倾斜的侧壁。侧壁通常相对于表面法线呈30到60度倾斜。
pn结、PIN结构或光电晶体管包含有源p区和有源n区122,所述有源p区可通过半导体表面层110提供,所述有源n区122形成包含沿第一倾斜侧壁115a提供第一光电探测器元件120a且沿第二倾斜侧壁115b提供第二光电探测器元件120b的至少pn结。有源n区122包含沟槽115的底部处的间隙,使得第一光电探测器元件120a和第二光电探测器元件120b彼此间隔开使得能够独立地操作为单独的光电探测器元件。可以实施具有光致抗蚀剂掩模图案或用于扩散掺杂工艺的硬掩模图案的离子植入以排除沟槽115底部的掺杂。光电探测器元件120a、120b各自将来自所接收的足够高能光子的能量转换成电流。
本文中所描述的掺杂区例如有源n区122(或有源p区,如果半导体表面层110不用作有源p区)可通过离子植入或通常还通过扩散掺杂方法来形成。关于扩散掺杂,起泡器可使用力气泡通过基于液体的掺杂源,例如用于形成n型区的POCl3扩散或用于形成p型区的三溴硼(BBr3)扩散。
p型阳极触点110a与半导体表面层110接触,且第一n型阴极触点122a与第一光电探测器元件的有源n区122接触,且第二n型阴极触点122b与第二光电探测器元件的有源n区122接触。p型阳极触点110a和n型阴极触点122a和122b可包括金属触点或硅化物触点。半导体表面层110(或其它p型区)和有源n区122的顺序可与所展示的顺序相反。就在PIN结构而言,本征半导体层插在有源p区与有源n区之间。图1B描绘根据实例实施例的具有第一光电探测器元件120a'和第二光电探测器元件120b'的实例倾斜光电探测器单元150,其中光电探测器触点122a'和122b'在倾斜侧壁115a、115b上。
就在光电晶体管而言,提供第三掺杂区以形成双极晶体管。图1C展示根据实例实施例的在包括双极光电晶体管元件170a和170b的倾斜侧壁上具有光电探测器触点的实例光电探测器单元180。光电晶体管元件170a和170b包含发射极173、基极172和由半导体表面层110提供的集电极。光电晶体管元件170a包含发射极触点173a和基极触点172a,同时光电晶体管元件170b包含发射极触点173b和基极触点172b。光电晶体管元件170a和光电晶体管元件170b共用集电极触点160a。在操作中,将由基极集电极(base-collector)结中接收的光子产生的电子植入到基极172中,且此光电二极管电流通过晶体管的电流增量β(或hfe)扩增。如果发射极173左侧不连接(浮动),那么光电晶体管元件各自操作为光电二极管。
展示倾斜侧壁具有作为有源n区122的外部暴露表面。尽管未在图1A至1C中展示,但一或多个光学透明表面层可在有源n区122上。此类层可包含用于将入射光传递到第一光电探测器元件和第二光电探测器元件以探测入射光的抗反射(AR)层和例如氧化硅、氮化硅或氮氧化硅等钝化层中的一或多种。
图2是根据实例实施例的展示形成至少一个倾斜光电探测器单元的实例方法200中的步骤的流程图。步骤201包括蚀刻以在衬底上具有平坦顶部表面的半导体表面层中形成至少一个沟槽,其中所述沟槽具有相对于半导体表面层的顶部的表面法线的倾斜侧壁。如上文所描述,倾斜侧壁不是竖直壁,通常相对于表面法线倾斜30到60度。尽管可以使用其它角度,但角度探测的最大灵敏度是30到60度以外的角度。如上文所描述,蚀刻可包括湿式蚀刻,例如在硅情况下的氢氧化物蚀刻,或干式蚀刻,例如DRIE。
步骤202包括形成包含有源p区(例如图1A中的半导体表面层110)和有源n区122的pn结、PIN结构或光电晶体管,所述有源n区122形成包含沿第一侧壁提供第一光电探测器元件的第一结和沿第二侧壁提供第二光电探测器元件的与第一结间隔开的第二结。步骤202可包括离子植入或扩散掺杂,例如用于n型掺杂的POCl3或用于p型掺杂的BBr3。有源p区(如果形成为扩散区域)和有源n区122通常均小于1μm深。步骤202掺杂通常在蚀刻之后以形成沟槽(步骤201),但对于LOCOS处理(参看下文所描述的图3A和3B),掺杂可在LOCOS氧化物生长之前或之后执行。
步骤203包括形成与第一光电探测器元件120a和第二光电探测器元件120b接触的有源p区(例如,半导体表面层110)和有源n区122的至少p型阳极触点和至少n型阴极触点。各个触点可以是平坦的(如上文所描述的图1A中所展示)或侧壁触点(如上文所描述的图1B中所展示),且通常穿过有源p区(例如,半导体表面层110)上和有源n区122上的介电层121形成。
图3A和3B展示用于形成所描述的倾斜光电二极管单元或此类单元的阵列的基于LOCOS的方法中的数个步骤之后的横截面绘图。图3A展示包括在衬底105上的半导体表面层110中形成的LOCOS氧化物的LOCOS区310。为执行LOCOS,不希望被氧化的区域涂覆有不允许氧气在高温(热氧化是在900℃与1200℃之间的温度下执行)下扩散的材料,例如氮化硅掩模层。图3B展示在图3A中展示的LOCOS区310的典型湿式(例如,基于HF的蚀刻剂)蚀刻之后产生的具有倾斜侧壁的沟槽330。在这种状况下,侧壁的角度通常为30度到60度。此LOCOS工艺的适当沟槽深度为约0.1μm到约1μm。
给定IC工艺中的现有植入(例如,用于MOS或BiMOS IC的阈值调整)可用于倾斜光电二极管单元,使得不添加掩模来实施光电二极管单元。植入可在LOCOS区310生长之前执行,使得其在LOCOS形成之后位于LOCOS区310下面,或如在去除LOCOS区310之后使用专用光电二极管掩模的植入或扩散掺杂工艺所产生的掺杂区355所展示。可形成第二掺杂区(未图示)以产生pn结或PIN结构,或如上文所描述的半导体表面层110可用作另一掺杂区。
图4A和4B展示用于形成所描述的倾斜光电二极管单元或此类单元的阵列的基于湿式硅蚀刻的方法中的数个步骤之后的横截面绘图。图4A展示衬底105上半导体表面层110上的图案化的蚀刻掩模材料(例如光致抗蚀剂或硬质掩模材料)410。在此实施例中,半导体表面层110包括硅。
图4B展示使用例如作为氢氧化物蚀刻剂的KOH(氢氧化钾)或TMAH(四甲基氢氧化铵)或包括乙二胺、邻苯二酚、吡嗪和水的EDP(乙二胺焦儿茶酚(ethylenediamenepyrocatecol))等湿式硅蚀刻剂蚀刻半导体表面层110的结晶硅之后所产生的V形凹槽中的沟槽430。基于此湿式硅蚀刻方法的适当沟槽深度通常为约5μm到约100μm。
沟槽430具有相对于半导体表面层110的顶部表面的表面法线的倾斜侧壁,所述倾斜侧壁包含第一倾斜侧壁和第二倾斜侧壁。碱性化学物质(例如,KOH)具有沿晶体取向优选地蚀刻硅的能力,这使得有可能形成利用其它微机械加工技术难以产生的几何形状(例如所展示的V形凹槽)。蚀刻速率取决于硅晶体平面的取向,其中由于这些取向处的原子(且因此硅(原子)密度)的排列,<100>和<110>的晶体取向不同于<111>,从而蚀刻不同。举例来说,硅<100>沿<111>晶体平面以相对于如图4B中所展示的<100>平面的所展示的54.74°角各向异性地蚀刻。在此实施例中,沟槽430与半导体表面层110的顶部表面的表面法线所成的角度是30.4°。
图5A、5B和5C展示所描述的倾斜光电二极管单元的阵列的顶部透视图。阵列中的每个光电探测器单元可通过改变p区和n区中的一个或两个的掺杂剂浓度而具有本质上相同的光谱响应度或不同的光谱响应度。通过使用不同光掩模和不同植入条件,例如利用一个植入物为一个区域使用掩模A打开光致抗蚀剂,且接着利用掩模B打开另一区用于再植入另一区。举例来说,对于LOCOS工艺,技术人员可使用LOCOS掩模LA且对一个侧壁区域使用LOCOS工艺,且接着对另一侧壁区侧壁使用另一LOCOS掩模LB。尽管未展示,但所描述的倾斜光电二极管单元可使用与结的p区上的任何位置和n区或其上的任何位置中的合适的互连件(例如,金属层)接触的贯通氧化物(或其它介电)连接在一起(并行地连接),尽管通常使用例如图1A中所展示的平坦表面触点。
图5A展示包括在衬底105上形成的展示为100a、100b、100c、100d和100e的五(5)个集成的倾斜光电二极管单元的实例光电探测器阵列500。阵列500配置成用于1条轴线(x轴)的角度探测。展示各单元的有源p区的触点和包含其各自的第一和第二光电探测器元件的各单元的有源n区的触点连接在一起(并行地连接)。展示包括合适的互连件(例如,金属层)的阳极总线522将结的所有p区连接在一起,且展示包括合适的互连件(例如,金属层)的阴极总线523将结的所有n区连接在一起。
图5B展示包括二十五(25)个集成的倾斜光电二极管单元的实例2D光电探测器阵列540,其中倾斜光电二极管单元100f1和100f5被识别为在衬底105上形成。图5C展示包括配置为同心环的三(3)个集成的倾斜光电二极管单元的实例光电探测器阵列560,所述同心环各自具有对应于上文所描述的光电探测器元件之间的间隔的间隙(例如上文所描述的图1A到1C中所展示的沟槽的底部处的有源n区122中的间隙),其在衬底105上展示为100g1、100g2和100g3。光电二极管单元100g1、100g2和100g3各自包含展示为各自具有4个元件的多个光电探测器元件。光电检测器阵列560的布局由此允许2条轴线的角度探测。
所描述的倾斜光电探测器适用于广泛多种光束角度监测器应用中,包含作为如上文所描述的角度传感器,或作为光学拾波器(光碟)、运动传感器或相控阵列光子传感器。所描述的倾斜光电探测器可与CMOS电路一起在IC上形成,例如使用包含双极CMOSDMOS(BCD)或双极工艺的类似工艺。
所描述的pn结倾斜光电探测器单元是使用硅<100>衬底根据关于图4A和4B所描述的工艺使用KOH到1μm的常见沟槽深度且使用离子植入来形成。图6A和6B是使用2V反向偏压的模拟,作为证明宽范围角度覆盖相对于表面法线为±45°的实例,具有关于左侧光电探测器(展示为PD(L))和右侧光电探测器(展示为PD(R))的单独PD电流与磁通角曲线,和关于所描述倾斜光电探测器单元的总的PD电流与光通角。图6B是从图6A中获得的一条曲线,其中y轴现在为德耳塔(Δ)PD电流,其更清晰地证明所描述倾斜光电探测器元件(例如,PD(L))在角度覆盖范围±45°内为角度探测提供了高灵敏度(ΔPD电流>大-100%到+100%)。
图7描绘用于不会涉及角度监测的所描述的倾斜光电探测器单元的光电探测器应用中的增强方向性效率的机构。展示通过从另一倾斜侧壁发出的反射辐射(且由此未探测到)的一个倾斜侧壁提供的重新探测来增强的光子转化效率。可以忽略中心载子的产生,这是因为不存在电场不会促使电流产生,因此所产生的载子在此处简单重组。
在所描述的实施例中可能进行修改,且其它实施例在权利要求的范围内是可能的。
Claims (16)
1.一种形成光电探测器单元的方法,所述方法包括:
蚀刻以在衬底上具有平坦顶部表面的半导体表面层中形成至少一个沟槽,所述沟槽具有相对于所述顶部表面的表面法线的倾斜侧壁,其包含第一倾斜侧壁和第二倾斜侧壁;
形成包含有源p区和有源n区的pn结、PIN结构或光电晶体管,所述有源n区形成包含沿所述第一倾斜侧壁提供第一光电探测器元件的第一结和沿所述第二倾斜侧壁提供第二光电探测器元件的与所述第一结间隔开的第二结;及
形成与所述第一光电探测器元件和所述第二光电探测器元件的所述有源p区和所述有源n区接触的至少p型阳极触点和至少n型阴极触点;
其中所述第一倾斜侧壁和所述第二倾斜侧壁提供外部暴露或光学透明表面,用于将入射光传递到所述第一光电探测器元件和所述第二光电探测器元件以探测所述入射光。
2.根据权利要求1所述的方法,其中所述衬底包括硅<100>。
3.根据权利要求2所述的方法,其中所述蚀刻包括基于湿式氢氧化硅的蚀刻,且其中所述倾斜侧壁相对于所述平坦顶部表面的表面法线呈30到60度倾斜。
4.根据权利要求2所述的方法,其进一步包括形成LOCOS氧化物的局部氧化硅LOCOS工艺,其中所述蚀刻包括湿式蚀刻所述LOCOS氧化物以形成所述沟槽。
5.根据权利要求1所述的方法,其中所述蚀刻形成多个所述沟槽且所述形成形成多个所述pn结、所述PIN结构或所述光电晶体管。
6.根据权利要求1所述的方法,其中所述多个所述pn结、所述PIN结构或所述光电晶体管以二维2D阵列布置。
7.根据权利要求1所述的方法,其中所述多个所述pn结、所述PIN结构或所述光电晶体管共同提供多个不同的光谱响应度。
8.根据权利要求1所述的方法,其中所述第一光电探测器元件和所述第二光电探测器元件配置成用于提供2条轴线的角度探测的同心环。
9.根据权利要求1所述的方法,其中所述半导体表面层提供所述有源p区或所述有源n区。
10.一种光电探测器单元,其包括:
衬底,具有半导体表面层;
沟槽,位于所述半导体表面中,所述沟槽具有包含第一倾斜侧壁和第二倾斜侧壁的倾斜侧壁;
pn结、PIN结构或光电晶体管,其包含有源p区和有源n区,所述有源n区形成包含沿所述第一倾斜侧壁提供第一光电探测器元件的第一结和沿所述第二倾斜侧壁提供第二光电探测器元件的第二结的结;及
至少p型阳极触点和至少n型阴极触点,其与所述第一光电探测器元件和所述第二光电探测器元件的所述有源p区和所述有源n区接触;
其中所述倾斜侧壁提供外部暴露或光学透明表面,用于将入射光传递到所述第一光电探测器元件和所述第二光电探测器元件以探测所述入射光。
11.根据权利要求10所述的光电探测器单元,其中所述衬底包括硅<100>。
12.根据权利要求10所述的光电探测器单元,其中所述倾斜侧壁相对于所述平坦顶部表面的表面法线呈30到60度倾斜。
13.根据权利要求10所述的光电探测器单元,其中所述多个所述pn结、所述PIN结构或所述光电晶体管以二维2D阵列布置。
14.根据权利要求13所述的光电探测器单元,其中所述多个所述pn结、所述PIN结构或所述光电晶体管共同提供多个不同的光谱响应度。
15.根据权利要求10所述的光电探测器单元,其中所述半导体表面层提供所述有源p区或所述有源n区。
16.根据权利要求10所述的光电探测器单元,其中所述第一光电探测器元件和所述第二光电探测器元件配置成用于提供2条轴线的角度探测的同心环。
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