CN108346647B - Test structure for optimizing laser trimming and laser trimming method - Google Patents
Test structure for optimizing laser trimming and laser trimming method Download PDFInfo
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- CN108346647B CN108346647B CN201710050816.9A CN201710050816A CN108346647B CN 108346647 B CN108346647 B CN 108346647B CN 201710050816 A CN201710050816 A CN 201710050816A CN 108346647 B CN108346647 B CN 108346647B
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- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
- H01L22/22—Connection or disconnection of sub-entities or redundant parts of a device in response to a measurement
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
- H01L21/76892—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances modifying the pattern
- H01L21/76894—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances modifying the pattern using a laser, e.g. laser cutting, laser direct writing, laser repair
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- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
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- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
- H01L23/5256—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive
- H01L23/5258—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive the change of state resulting from the use of an external beam, e.g. laser beam or ion beam
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Abstract
The invention provides a test structure for optimizing laser trimming and a laser trimming method, comprising the following steps: a test and configuration code calculation storage module which sends test signals and generates corresponding pre-configuration codes and configuration codes according to the values of the fed back performance parameters; in the trimming stage, each laser fuse module is blown or reserved according to the configuration code so as to trim the value of the corresponding performance parameter; receiving all pre-configured codes in a test stage and receiving a conversion interface of a fuse value in a trimming stage; and an internal circuit. According to the invention, the configuration codes of all chips on the wafer are obtained on the testing machine and then are moved to the repairing and adjusting machine, and the repairing and adjusting of all performance parameters can be completed only by performing laser repairing and adjusting once without frequent power on and off, so that the testing time is greatly saved, and the testing cost and the production cost are further reduced.
Description
Technical Field
The invention relates to the field of electronic circuit testing, in particular to a test structure for optimizing laser trimming and a laser trimming method.
Background
In the original laser trimming and testing method, the basic steps are that the performance parameters needing to be trimmed are tested, corresponding configuration codes which can trim the performance parameters to be within the specification range are obtained through the test results, and the configuration codes are used for determining whether the laser trimming fuse wires corresponding to the performance parameters are fused or reserved.
As shown in fig. 1, the conventional laser trimming and testing structure includes: a tester 101 and a chip to be tested 102, wherein the chip to be tested 102 includes an internal circuit 103, a conversion interface 104 and a laser fuse 105. The testing machine 101 is a chip external module and is used for sending a test signal TM to the internal circuit 103, so as to control the chip 102 to enter a test mode, obtain a value FB of a performance parameter to be repaired through testing the chip 102, and calculate a corresponding configuration code LF capable of being repaired within a specification range according to the value FB of the performance parameter. The laser fuse 105 receives the configuration code LF, blows or retains the laser fuse according to the configuration code LF, and the conversion interface 104 converts the blowing and retaining of the laser fuse 105 into the on/off of the internal switch, so as to change the values of the performance parameters of the internal circuit 103, such as voltage, current, frequency, delay time, and the like, thereby achieving the purpose of correcting the performance parameters to be within the specification range.
As shown in fig. 2, the wafer includes chips to be tested, and the first chip 11 to the sixteenth chip 116 represent a part of the chips on the wafer, in which in practical cases, the number of the chips on the wafer is much greater than 16.
Assume that the performance parameters of the chip that need to be adjusted to the specification range are the first to thirteenth performance parameters, such as power reference voltage, reference current, delay time, maximum switching frequency, minimum switching frequency, maximum on-time, and so on. As shown in fig. 3, the configuration code LF is composed of a first configuration code LF1 to a thirteenth configuration code LF13, and the first configuration code LF1 to the thirteenth configuration code LF13 respectively represent configuration codes of the first test performance parameter to the thirteenth performance parameter. If one or more performance parameters in the thirteen performance parameters have a relationship that the latter modified performance parameter needs the former modified performance parameter as a variable. As shown in fig. 4, for example, the first performance parameter is a variable of the second performance parameter index, the first performance parameter and the second performance parameter are a variable of the third performance parameter, and the second performance parameter and the twelfth performance parameter are a variable of the thirteenth performance parameter. For example, if the first performance parameter is the reference voltage vref, the second performance parameter is the reference current Iref, and the third performance parameter is the delay time Tdelay, then there must be:
wherein, R is a resistor, C1 is a capacitor, and it can be seen that when Iref needs to be modified, the value of Vref is first modified to the specification range to obtain the correct configuration code of Iref, and similarly, when Tdelay needs to be modified, the values of Vref and Iref are first modified to the specification range to obtain the correct configuration code of Tdelay. However, the existing laser trimming process cannot perform two steps of testing parameters and laser trimming at the same machine at the same time, so that the configuration code determination and the laser trimming of each performance parameter need to undergo a process of testing, storing the configuration code, turning off a power supply, trimming the laser, and retesting and verifying.
As shown in fig. 5, first, on a test machine, a first chip 11 is powered on, the first chip 11 is tested to obtain a first configuration code LF1 of the first chip 11, the first chip 11 is powered off, a second chip 12 is powered on, the second chip 12 is tested to obtain a first configuration code LF1 of the second chip 12, the second chip 12 is powered off, a third chip 13 is powered on, and so on, so as to obtain a first configuration code LF1 of each chip on a wafer; then turning off the power supply, moving the wafer from the test machine to the trimming machine, blowing or reserving the first laser fuse by using the first configuration code LF1 of each chip to finish the trimming of the first performance parameters of all the chips, then turning off the power supply, moving the wafer from the trimming machine to the test machine, testing the first performance parameters to ensure that the trimming is successful, and then testing the second performance parameters; and in the same way, testing the third to twelfth performance parameters to obtain the configuration codes, trimming until a thirteenth configuration code LF13 is obtained, switching off the power supply, switching the wafer to the trimming machine, performing laser trimming according to the thirteenth configuration code LF13, switching off the power supply after trimming is finished, and switching back to the testing machine to test the thirteenth performance parameter, so as to finish the whole laser trimming process. Therefore, the time required for testing is hours, and how many times the testing machine and the laser trimming machine need to be switched to each other when the performance parameters with the mutual variables need to be trimmed.
In summary, in the conventional laser trimming technology, if there are many performance parameters to be trimmed and there is a variable relationship between them, multiple chip starts and power cuts are required. Each chip needs to consume tens of milliseconds, and the testing time of the chip is generally within hundreds of milliseconds; in addition, switching between the testing machine and the repairing machine frequently takes tens of minutes, and in short, such a testing method needs a lot of testing time, and the increase of the testing time means the increase of the testing cost, and the increase of the testing cost means the increase of the chip production cost.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a test structure and a laser trimming method for optimizing laser trimming, which are used to solve the problems of long overall test time of a wafer, high production cost, and the like in the prior art.
To achieve the above and other related objects, the present invention provides a test structure for optimizing laser trimming, comprising at least:
the test and configuration code calculation and storage module, the laser fuse module, the conversion interface and the internal circuit;
the test and configuration code calculation and storage module is connected with the internal circuit, the laser fuse module and the conversion interface, and is used for sending a test signal to the internal circuit, generating a corresponding pre-configuration code and a configuration code according to a value of a performance parameter fed back by the internal circuit, and respectively sending the pre-configuration code and the configuration code to the conversion interface and the laser fuse module;
the laser fuse modules are connected to the output ends of the test and configuration code calculation storage modules, and in the trimming stage, the laser fuse modules are blown or reserved according to the configuration codes so as to trim the values of the corresponding performance parameters;
the conversion interface is connected with the output ends of the test and configuration code calculation storage module and the laser fuse module, and receives all the pre-configuration codes stored in the test and configuration code calculation storage module in a test stage so as to obtain the pre-configuration codes of the performance parameters of the current test; in the trimming stage, receiving a fuse value at the output end of the laser fuse module so as to change the value of the performance parameter;
the internal circuit is connected with the output end of the conversion interface, and the performance parameters are tested and modified according to the configuration information provided by the conversion interface.
Preferably, the laser fuse module, the conversion interface and the internal circuit are located on the same test chip.
Preferably, the laser fuse module comprises a pull-up tube and a laser fuse, one end of the pull-up tube is connected with a power supply, the other end of the pull-up tube is connected with the laser fuse, the other end of the laser fuse is grounded, and a connection node of the pull-up tube and the laser fuse is used as an output end.
More preferably, the conversion interface includes a first switch, a second switch and a trigger, an input end of the first switch is connected to the laser fuse module, and an output end of the first switch is connected to a data input end of the trigger; the input end of the second switch is connected with the output end of the test and configuration code calculation storage module, and the output end of the second switch is connected with the data input end of the trigger; the flip-flop is used to read and latch the fuse value or the pre-configured code.
In order to achieve the above and other related objects, the present invention further provides a laser trimming method, which at least includes:
in the testing stage, all the pre-configuration codes of the chip are obtained through multiple tests, and the nth pre-configuration code is generated on the basis of the first (n-1) pre-configuration codes; sequentially acquiring all pre-configured codes of each chip on a wafer;
in the trimming stage, assigning the pre-configuration code of each chip to the configuration code of the corresponding chip, and blowing or reserving the laser fuse according to the configuration code to change the value of the performance parameter of each chip so as to finish laser trimming;
wherein n is a natural number greater than 0.
Preferably, the method of obtaining all pre-configured codes of a chip further comprises: testing a first performance parameter of a chip to obtain a value of the first performance parameter, and obtaining a first pre-configuration code according to the value of the first performance parameter; carrying out simulation trimming on the first performance parameter by using the first preconfigured code, and then testing a second performance parameter of the chip to obtain a second preconfigured code; carrying out simulation trimming on the first performance parameter and the second performance parameter by using the first preconfigured code and the second preconfigured code, and then testing a third performance parameter of the chip to obtain a third preconfigured code; and so on, all the pre-configured codes are obtained.
More preferably, the test order of each performance parameter is sorted by the correlation degree, and the correlation degrees are tested from low to high in sequence.
Preferably, the testing stage is completed on a testing machine, the repairing stage is completed on a repairing machine, and the machine is switched to be powered off when the testing and repairing are performed.
As described above, the test structure and the laser trimming method for optimizing laser trimming of the present invention have the following beneficial effects:
according to the test structure and the laser trimming method for optimizing the laser trimming, the configuration codes of all chips on the wafer are obtained on the test machine and then are moved to the trimming machine, the trimming of all performance parameters can be completed only by performing the laser trimming once, frequent power on and power off is not needed, the test time is greatly saved, and the test cost and the production cost are further reduced.
Drawings
Fig. 1 is a schematic diagram of a laser trimming and testing structure in the prior art.
Fig. 2 is a schematic diagram of a wafer in the prior art.
Fig. 3 is a diagram illustrating configuration codes in the prior art.
Fig. 4 is a diagram illustrating a relationship between performance parameters.
Fig. 5 is a schematic flow chart of a test trimming method in the prior art.
Fig. 6 is a schematic diagram of a test structure for optimizing laser trimming according to the present invention.
Fig. 7 is a schematic structural diagram of a test structure for optimizing laser trimming according to the present invention.
Fig. 8 is a schematic flow chart of laser trimming according to the present invention.
Description of the element reference numerals
101 testing machine
102 chip to be tested
103 internal circuit
104 conversion interface
105 laser fuse
11-116 first to sixteenth chips
21 test and configuration code calculation storage module
22 laser fuse module
221 upward pulling pipe
222 laser fuse
23 conversion interface
231 first switch
232 second switch
233 trigger
24 internal circuit
241 laser fuse switch tube
242 first point
243 second position
S1-S2
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 6 to 8. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.
As shown in fig. 6, the present invention provides a test structure for optimizing laser trimming, which at least includes:
a test and configuration code calculation memory block 21, a laser fuse block 22, a conversion interface 23, and an internal circuit 24.
As shown in fig. 6, the test and configuration code calculation and storage module 21 is connected to the internal circuit 24, the laser fuse module 22 and the conversion interface 23, and configured to send a test signal TM to the internal circuit 24, generate a corresponding pre-configuration code VLF and a corresponding configuration code LF according to a value FB of a performance parameter fed back by the internal circuit 24, and send the pre-configuration code VLF and the configuration code LF to the conversion interface 23 and the laser fuse module 22, respectively.
Specifically, the test and configuration code calculation storage module 21 generates a corresponding pre-configuration code VLF according to the value FB of the performance parameter fed back by the test, and stores the pre-configuration code VLF in the test and configuration code calculation storage module 21. When the next test is needed, all the obtained preconfigured codes VLF are sent to the conversion interface 23, the corresponding performance parameters in the internal circuit 24 are preconfigured through the preconfigured codes, the internal circuit 24 simulates the effect after trimming, and during the test, the performance parameters of the current test are performed on the basis of the performance parameters trimmed and tested before.
As shown in fig. 6, the laser fuse module 22 is connected to the output of the test and configuration code calculation memory module 21. In the testing stage, the testing and configuration code calculation storage module 21 does not send a signal to the laser fuse module 22; in the trimming stage, the test and configuration code calculation and storage module 21 sends a configuration code LF to the laser fuse module 22, and the laser fuse module 22 blows or retains each laser fuse module 22 according to the configuration code LF, so as to trim the value of the corresponding performance parameter according to the final configuration code LF.
Specifically, as shown in fig. 7, the laser fuse module 22 includes a pull-up tube 221 and a laser fuse 222. In this embodiment, the pull-up tube 221 is a PMOS, and has a source end connected to a power voltage, a drain end connected to the laser fuse 222, and a gate end connected to the control signal PB. One end of the laser fuse 222 is connected to the upper pull tube 221, and the other end is grounded, and the laser fuse 222 is blown or reserved under the control of the configuration code LF. The connection node of the pull-up tube 221 and the laser fuse 222 serves as an output terminal.
As shown in fig. 6, the conversion interface 23 is connected to the output terminals of the test and configuration code calculation memory module 21 and the laser fuse module 22. In the testing stage, the conversion interface 23 receives all the pre-configuration codes vlf (i) stored in the testing and configuration code calculation storage module 21, where i is 1 … n-1, and then obtains the pre-configuration codes vlf (n) of the performance parameters of the current test; in the trimming stage, the fuse value at the output end of the laser fuse module 22 is received, and the value of the performance parameter is changed.
Specifically, as shown in fig. 7, the conversion interface 23 includes a first switch 231, a second switch 232, and a flip-flop 233. In the present embodiment, the first switch 231 and the second switch 232 are transmission gates, and their control signals are a chip enable signal POR and an inverse signal PORB thereof, respectively. The input end of the first switch 231 is connected to the laser fuse module 22, the output end of the first switch 231 is connected to the data input end of the trigger 233, and the first switch 231 is turned on in the trimming stage. The input end of the second switch 232 is connected to the output end of the test and configuration code calculation storage module 21, the output end of the second switch 232 is connected to the data input end of the trigger 233, and in the test stage, the second switch 232 is turned on. The flip-flop 233 is configured to read and latch the fuse value or the preconfigured code, in this embodiment, the flip-flop 233 is a D flip-flop, and includes a data input terminal D, a clock signal terminal clk, a reset terminal CLR, and an output terminal Q; the data input terminal D is connected to the output terminals of the first switch 231 and the second switch 232, the clock signal terminal CLK is connected to the read clock CLK, the reset terminal CLR is connected to the reset signal CLR, and the output terminal Q is connected to the internal circuit 24.
As shown in fig. 6, the internal circuit 24 is connected to the output end of the conversion interface 23, and performs performance parameter testing and trimming according to the configuration information provided by the conversion interface 23.
Specifically, as shown in fig. 7, the internal circuit 24 includes a laser fuse switch tube 241, a first point location 242, and a second point location 243. In this embodiment, the laser fuse switch tube 241 is an NMOS, and has a drain terminal connected to the first point 242, a source terminal connected to the second point 243, and a gate terminal connected to the output terminal of the conversion interface 23. In an actual circuit, the internal circuit 24 includes more than 3 devices, and only some devices related to testing and trimming are schematically shown in this embodiment, which is not limited to this embodiment.
Before the chip is started, the chip start signal POR is low, the output of the laser fuse module 22 is read into the flip-flop 233, and after the clock CLK is read, the fuse value is converted into the on and off of the laser fuse switch tube 241, so that whether the first point location 242 and the second point location 243 are connected or disconnected is determined, the connection relationship of the internal circuit is changed, and the purpose of adjusting the relevant performance parameters to be within the specification range is achieved. After the chip is started, the chip start signal POR is high, the inverse signal PORB is low, and the preconfigured code VLF is read by the laser fuse switch tube 241 through the flip-flop 233, so that the purpose of simulating the actual laser trimming effect through the preconfigured code VLF can be achieved.
As shown in fig. 6, in the present embodiment, the laser fuse module 22, the conversion interface 23 and the internal circuit 24 are located on the same test chip.
As shown in fig. 6 to 8, the present invention further provides a laser trimming method, which is implemented by the test structure for optimizing laser trimming. In practical use, the circuit structure is not limited.
The laser trimming method at least comprises the following steps:
step S1: in the testing stage, all the pre-configuration codes of the chip are obtained through multiple tests, and the nth pre-configuration code is generated on the basis of the first (n-1) pre-configuration codes; all the pre-configured codes of each chip on the wafer are acquired in sequence. In the testing stage, the wafer to be tested is positioned on the testing machine.
Specifically, as shown in fig. 8, a first chip is powered on, all preconfigured codes VLF of the first chip are obtained through testing, and then the first chip is powered off; powering on a second chip, acquiring all the pre-configured codes VLF of the second chip through testing, and powering down the second chip; and analogizing in turn, all the pre-configured codes VLF of each chip are obtained.
More specifically, as shown in fig. 8, the method for obtaining all preconfigured codes of a chip further includes: testing a first performance parameter of the chip by the test and configuration code calculation and storage module 21 to obtain a fed back value FB of the first performance parameter, and obtaining a first preconfigured code VLF1 by the test and configuration code calculation and storage module 21 according to the fed back value FB of the first performance parameter; the test and configuration code calculation and storage module 21 inputs the first preconfigured code VLF1 into the internal circuit 24, performs simulated trimming on the first performance parameter by using the first preconfigured code VLF1, simulates the trimmed effect of the laser fuse of the first performance parameter, and then tests the second performance parameter of the chip to obtain a second preconfigured code VLF 2; simulating and trimming the first performance parameter and the second performance parameter by using the first preconfigured code VLF1 and the second preconfigured code VLF2, simulating the trimmed effect of the laser fuse of the first performance parameter and the second performance parameter, and testing a third performance parameter of the chip to obtain a third preconfigured code VLF 3; and so on, all the pre-configured codes of the chip are obtained.
The test sequence of each performance parameter is sorted by the correlation degree, and the correlation degrees are tested from low to high in sequence. When the latter performance parameter is a variable of the former performance parameter, the latter performance parameter is tested and simulated and modified, and the former performance parameter is tested and simulated and modified on the basis of the simulated and modified later performance parameter.
In the present invention, when the nth performance parameter is tested sequentially, all the pre-configuration codes vlf (i) obtained by the previous test are output to the conversion interface 23 (including all the variables of the nth performance parameter), i-1 … n-1, the effect after the laser trimming is performed on the real configuration code is simulated, and then the configuration code vlf (n) of the performance parameter of the current test is obtained through the test and the calculation. Wherein n is a natural number greater than 0.
Step S2: and in the trimming stage, assigning the pre-configuration code of each chip to the configuration code of the corresponding chip, and blowing or reserving the laser fuse according to the configuration code so as to change the value of the performance parameter of each chip and further finish the laser trimming.
Specifically, after the test stage is completed, the power is cut off, and the wafer is moved to a trimming machine. Each pre-configuration code VLF is used as a final configuration code LF, and the laser fuse module 22 blows or reserves each laser fuse, so as to modify each performance parameter in the internal circuit 24, thereby achieving the purpose of modifying the relevant performance parameter to be within the specification range.
Therefore, the test structure and the laser trimming method for optimizing the laser trimming of the invention move to the trimming machine after the configuration codes of all chips on the wafer are obtained on the test machine, and the trimming of all performance parameters can be completed only by performing the laser trimming once without frequently powering on and powering off, thereby greatly saving the test time and further reducing the test cost and the production cost.
In summary, the present invention provides a test structure and a laser trimming method for optimizing laser trimming, including: the test and configuration code calculation storage module is used for sending a test signal and generating a corresponding pre-configuration code and a configuration code according to the value of the fed back performance parameter; in the trimming stage, each laser fuse module is blown or reserved according to the configuration code so as to trim the value of the corresponding performance parameter; receiving all pre-configured codes in a test stage and receiving a conversion interface of a fuse value in a trimming stage; and an internal circuit. According to the test structure and the laser trimming method for optimizing the laser trimming, the configuration codes of all chips on the wafer are obtained on the test machine and then are moved to the trimming machine, the trimming of all performance parameters can be completed only by performing the laser trimming once, frequent power on and power off is not needed, the test time is greatly saved, and the test cost and the production cost are further reduced. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (8)
1. A test structure for optimizing laser trimming, characterized in that the test structure for optimizing laser trimming comprises at least:
the test and configuration code calculation and storage module, the laser fuse module, the conversion interface and the internal circuit;
the test and configuration code calculation and storage module is connected with the internal circuit, the laser fuse module and the conversion interface, and is used for sending a test signal to the internal circuit, generating a corresponding pre-configuration code and a configuration code according to a value of a performance parameter fed back by the internal circuit, and respectively sending the pre-configuration code and the configuration code to the conversion interface and the laser fuse module;
the laser fuse modules are connected to the output ends of the test and configuration code calculation storage modules, and in the trimming stage, the laser fuse modules are blown or reserved according to the configuration codes so as to trim the values of the corresponding performance parameters;
the conversion interface is connected with the output ends of the test and configuration code calculation storage module and the laser fuse module, and receives all the pre-configuration codes stored in the test and configuration code calculation storage module in a test stage so as to obtain the pre-configuration codes of the performance parameters of the current test; in the trimming stage, receiving a fuse value at the output end of the laser fuse module so as to change the value of the performance parameter;
the internal circuit is connected with the output end of the conversion interface, and the performance parameters are tested and modified according to the configuration information provided by the conversion interface.
2. The test structure for optimizing laser trimming of claim 1, wherein: the laser fuse module, the conversion interface and the internal circuit are located on the same test chip.
3. The test structure for optimizing laser trimming of claim 1, wherein: the laser fuse module comprises an upper pull tube and a laser fuse, one end of the upper pull tube is connected with a power supply, the other end of the upper pull tube is connected with the laser fuse, the other end of the laser fuse is grounded, and a connection node of the upper pull tube and the laser fuse serves as an output end.
4. The test structure for optimizing laser trimming of claim 1 or 3, wherein: the conversion interface comprises a first switch, a second switch and a trigger, wherein the input end of the first switch is connected with the laser fuse module, and the output end of the first switch is connected with the data input end of the trigger; the input end of the second switch is connected with the output end of the test and configuration code calculation storage module, and the output end of the second switch is connected with the data input end of the trigger; the flip-flop is used to read and latch the fuse value or the pre-configured code.
5. A laser trimming method is characterized by at least comprising the following steps:
in the testing stage, all the pre-configuration codes of the chip are obtained through multiple tests, and the nth pre-configuration code is generated on the basis of the first (n-1) pre-configuration codes; sequentially acquiring all pre-configured codes of each chip on a wafer;
in the trimming stage, assigning the pre-configuration code of each chip to the configuration code of the corresponding chip, and blowing or reserving the laser fuse according to the configuration code to change the value of the performance parameter of each chip so as to finish laser trimming;
wherein n is a natural number greater than 0.
6. The laser trimming method according to claim 5, wherein: the method for acquiring all pre-configured codes of a chip further comprises the following steps: testing a first performance parameter of a chip to obtain a value of the first performance parameter, and obtaining a first pre-configuration code according to the value of the first performance parameter; carrying out simulation trimming on the first performance parameter by using the first preconfigured code, and then testing a second performance parameter of the chip to obtain a second preconfigured code; carrying out simulation trimming on the first performance parameter and the second performance parameter by using the first preconfigured code and the second preconfigured code, and then testing a third performance parameter of the chip to obtain a third preconfigured code; and so on, all the pre-configured codes are obtained.
7. The laser trimming method according to claim 6, wherein: the test sequence of each performance parameter is sorted by the correlation degree, and the correlation degrees are tested from low to high in sequence.
8. The laser trimming method according to claim 5, wherein: and completing the testing stage on a testing machine, and completing the trimming stage on a trimming machine after the machine is switched in a power-off mode.
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