CN108346647A - A kind of test structure and laser trimming method for optimizing laser trimming - Google Patents
A kind of test structure and laser trimming method for optimizing laser trimming Download PDFInfo
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- CN108346647A CN108346647A CN201710050816.9A CN201710050816A CN108346647A CN 108346647 A CN108346647 A CN 108346647A CN 201710050816 A CN201710050816 A CN 201710050816A CN 108346647 A CN108346647 A CN 108346647A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
- H01L22/22—Connection or disconnection of sub-entities or redundant parts of a device in response to a measurement
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
- H01L21/76892—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances modifying the pattern
- H01L21/76894—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances modifying the pattern using a laser, e.g. laser cutting, laser direct writing, laser repair
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
- H01L23/5256—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive
- H01L23/5258—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive the change of state resulting from the use of an external beam, e.g. laser beam or ion beam
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Abstract
The present invention provides a kind of test structure and laser trimming method for optimizing laser trimming, including：It sends test signal and the corresponding test for being pre-configured code and configuration code and configuration code calculating memory module is generated according to the value of the performance parameter of feedback；The stage is being trimmed, each laser fuse module is blown or retained according to configuration code, the laser fuse module trimmed with the value to respective performances parameter；All pre-configuration codes are received in test phase, the translation interface of fuse values is received in the stage that trims；And internal circuit.The present invention, which obtains to move to after the configuration code of all chips on wafer on tester table, trims board, only a laser trimming, which need to be carried out, can complete trimming for all properties parameter, without frequent power-on and power-off, the testing time is greatlyd save, and then reduce testing cost and production cost.
Description
Technical field
The present invention relates to electronic circuit test field, more particularly to a kind of test structure for optimizing laser trimming and
Laser trimming method.
Background technology
In original laser trimming and test method, basic step is that first test needs the performance parameter trimmed,
It obtains that the corresponding configuration code in specification limit performance parameter can be trimmed by the result of test, then this is determined with configuration code
The corresponding laser trimming fuse of performance parameter is fusing or retains.
As shown in Figure 1, existing laser trimming and test structure include：Test machine 101 and chip to be tested 102,
In, the chip 102 to be tested includes internal circuit 103, translation interface 104 and laser fuse 105.The test machine 101 is
Chip exterior module, effect are to send test signal TM to the internal circuit 103, enter test mould to control chip 102
Formula is calculated by testing the value FB for the performance parameter that the chip 102 learns that needs trim according to the value FB of performance parameter
The corresponding configuration code LF in specification limit can be trimmed.The laser fuse 105 receives the configuration code LF, is matched according to described
It sets yard LF laser fuse is blown or retained, the translation interface 104 turns blowing and retaining for the laser fuse 105
Change the conducting shutdown of internal switch, and then the performances such as voltage and current, frequency, delay time for changing the internal circuit 103 into
The value of parameter, to achieve the purpose that performance parameter is adapted in specification limit.
It is illustrated in figure 2 wafer where needing chip to be tested, the first chip 11 is represented to the 16th chip 116 on wafer
A part for chip, in actual conditions, the chip number on wafer is far longer than 16.
Assuming that it is the performance of first performance parameter~the 13rd that each needs of chip, which trim performance parameter in specification limit,
Parameter, such as power reference voltage, reference current, delay time, maximum switching frequency, minimal switching frequency, when maximum is connected
Between etc..As shown in figure 3, configuration code LF is made of the first configuration code LF13 of configuration code LF1~the 13rd, the first configuration code LF1
~the ten three configuration code LF13 indicates the configuration code of the performance parameter of the first test performance parameter~the 13rd respectively.If 13
There is the performance parameters that the latter trims, and front one to be needed to trim between one or several performance parameters in performance parameter
Good performance parameter is the relationship of variable.As shown in figure 4, such as first performance parameter is the variable of the second performance parameter index,
First performance parameter and the second performance parameter are the variable of third performance parameter, the second performance parameter and the 12nd performance jointly
Parameter is the variable of the 13rd performance parameter jointly.For example, first performance parameter is reference voltage vref, the second performance ginseng
Number is reference current Iref, and third performance parameter is delay time Tdelay, then certainly existing：
Wherein, R is resistance, and C1 is capacitance, it is seen then that when needing to trim Iref, the value of Vref is first had to trim
Regulating scope could obtain the correct configuration code of Iref, similarly, when needing to trim Tdelay, first have to a Vref and
The value of Iref trims regulating scope, could obtain the correct configuration code of Tdelay.And existing laser trimming technique can not
It is carried out at the same time test parameter and laser trimming the two steps in the same board, then the configuration code of each performance parameter is true
Fixed and laser trimming is required for experience to test, storage configuration code, power cutoff, laser trimming, a flow of re-test verification.
As shown in figure 5, first on tester table, the first chip 11 powers on, and tests first chip 11 and obtains institute
The first configuration code LF1 of the first chip 11 is stated, first chip 11 powers off, and the second chip 12 powers on, to second chip
12 tests obtain the first configuration code LF1 of second chip 12, and second chip 12 powers off, and third chip 13 powers on, according to
It is secondary to analogize, obtain the first configuration code LF1 of each chip on wafer；It is then powered off power supply, wafer is moved to from tester table
Board is trimmed, first laser fuse is blown or retained using the first configuration code LF1 of each chip, completes all chips
Trimming for first performance parameter, is then powered off power supply, wafer is moved to tester table from trimming on board, carries out first performance ginseng
Several test, it is ensured that this trims success, then carries out the test of the second performance parameter；The rest may be inferred, carries out third performance parameter
To the test of the 12nd performance parameter, configuration code is obtained, is trimmed, until after obtaining the 13rd configuration code LF13, power cutoff will
Wafer, which shifts to, trims board, carries out laser trimming according to the 13rd configuration code LF13, trims and finish power cutoff, gain test machine
Platform carries out the test of the 13rd performance parameter, so far completes entire laser trimming process.As it can be seen that needing to carry out how many has each other
The performance parameter of variable trims, it is necessary to the switching of how many times tester table and laser trimming board is carried out, and this is needed
The time of test is in hours.
In conclusion in existing laser trimming technology, the performance parameter trimmed if necessary is relatively more, between each other again
There is variable relation, then needs to carry out multiple chip startup and power-off.It is required for expending the time of several ms grade per chips, and
The general chip testing time is all in hundreds of milliseconds；In addition, continually being toggled between board in tester table and trimming, again
The time of consuming dozens of minutes is needed, such test method needs to expend a large amount of testing time in a word, and the testing time
Increasing means that the increase of testing cost, the increase of testing cost also mean that the increase of chip production cost.
Invention content
In view of the foregoing deficiencies of prior art, the purpose of the present invention is to provide a kind of for optimizing laser trimming
Test structure and laser trimming method, for solving, wafer overall test time is very long in the prior art, production cost is high etc. asks
Topic.
In order to achieve the above objects and other related objects, the present invention provides a kind of test knot for optimizing laser trimming
Structure, the test structure for optimizing laser trimming include at least：
Test and configuration code calculate memory module, laser fuse module, translation interface and internal circuit；
The test and configuration code calculate memory module and connect the internal circuit, the laser fuse module and described
Translation interface, for sending test signal, and the value of the performance parameter according to internal circuit feedback to the internal circuit
Corresponding pre-configuration code and configuration code are generated, and the pre-configuration code and the configuration code are separately sent to the translation interface
And the laser fuse module；
The laser fuse module is connected to the test and configuration code calculates the output end of memory module, is trimming rank
Section, is blown or is retained to each laser fuse module according to the configuration code, trimmed with the value to respective performances parameter；
The translation interface is connected to the test and configuration code calculates the defeated of memory module and the laser fuse module
Outlet receives the test and configuration code calculates all pre-configuration codes stored in memory module, and then obtain in test phase
The pre-configuration code for the performance parameter currently tested；The stage is being trimmed, the fuse values of the laser fuse module output end are received, into
And change the value of performance parameter；
The internal circuit connects the output end of the translation interface, according to the translation interface provide configuration information into
It the test of row performance parameter and trims.
Preferably, the laser fuse module, the translation interface and the internal circuit are located in same test chip.
Preferably, the laser fuse module includes upper trombone slide and laser fuse, upper trombone slide one end connection power supply, another
One end connects the laser fuse, the other end ground connection of the laser fuse, the connection of the upper trombone slide and the laser fuse
Node is as output end.
It is highly preferred that the translation interface includes first switch, second switch and trigger, the input of the first switch
End connects the laser fuse module, and the output end of the first switch connects the data input pin of the trigger；Described
The input terminal of two switches connects the test and configuration code calculates the output end of memory module, and the output end of the second switch connects
Connect the data input pin of the trigger；The trigger is for reading and latching the fuse values or the pre-configuration code.
In order to achieve the above objects and other related objects, the present invention also provides a kind of laser trimming method, the laser is repaiied
Tune method includes at least：
In test phase, all pre-configuration codes of chip are obtained by repeatedly testing, n-th of pre-configuration code is at preceding (n-1)
It is generated on the basis of a pre-configuration code；All pre-configuration codes of each chip on wafer are obtained successively；
The stage is being trimmed, the pre-configuration code of each chip is being assigned to the configuration code of corresponding chip, according to the configuration code pair
Laser fuse is blown or is retained, and to change the value of the performance parameter of each chip, and then completes laser trimming；
Wherein, n is the natural number more than 0.
Preferably, all methods for being pre-configured code of a chip are obtained to further comprise：To the first performance parameter of chip into
Row test, obtains the value of the first performance parameter, the first pre-configuration code is worth to according to the first performance parameter；
Simulation is carried out to the first performance parameter to trim, then the second performance parameter of chip is surveyed with the first pre-configuration code
Examination, obtains the second pre-configuration code；With described first be pre-configured code and described second be pre-configured code to the first performance parameter and
Second performance parameter carries out simulation and trims, then tests the third performance parameter of chip, obtains third and is pre-configured code；
The rest may be inferred, obtains all pre-configuration codes.
It is highly preferred that the testing sequence of each performance parameter, with relevancy ranking, the degree of correlation is tested successively from low to high.
Preferably, the test phase is completed on tester table, described to trim the stage and completed on trimming board, is executed
It tests and trims needs and power off switching board.
As described above, the test structure and laser trimming method for optimizing laser trimming of the present invention, has with following
Beneficial effect：
The test structure for being used to optimize laser trimming and laser trimming method of the present invention obtains wafer on tester table
It is moved to after the configuration code of upper all chips and trims board, only need to carry out a laser trimming can complete repairing for all properties parameter
It adjusts, is not necessarily to frequent power-on and power-off, greatly save the testing time, and then reduce testing cost and production cost.
Description of the drawings
Fig. 1 is shown as laser trimming in the prior art and the schematic diagram of test structure.
Fig. 2 is shown as wafer schematic diagram in the prior art.
Fig. 3 is shown as configuration code schematic diagram in the prior art.
Fig. 4 is shown as a kind of relation schematic diagram between performance parameter.
Fig. 5 is shown as the flow diagram of test method for repairing and regulating in the prior art.
Fig. 6 is shown as the schematic diagram of the test structure for optimizing laser trimming of the present invention.
Fig. 7 is shown as the concrete structure schematic diagram of the test structure for optimizing laser trimming of the present invention.
Fig. 8 is shown as the flow diagram of the laser trimming of the present invention.
Component label instructions
101 test machines
102 chips to be tested
103 internal circuits
104 translation interfaces
105 laser fuses
11~116 the first~the 16th chips
21 tests and configuration code calculate memory module
22 laser fuse modules
Trombone slide on 221
222 laser fuses
23 translation interfaces
231 first switches
232 second switches
233 triggers
24 internal circuits
241 laser fuse switching tubes
242 first points
243 second points
S1~S2 steps
Specific implementation mode
Illustrate that embodiments of the present invention, those skilled in the art can be by this specification below by way of specific specific example
Disclosed content understands other advantages and effect of the present invention easily.The present invention can also pass through in addition different specific realities
The mode of applying is embodied or practiced, the various details in this specification can also be based on different viewpoints with application, without departing from
Various modifications or alterations are carried out under the spirit of the present invention.
Please refer to Fig. 6~Fig. 8.It should be noted that the diagram provided in the present embodiment only illustrates this in a schematic way
The basic conception of invention, package count when only display is with related component in the present invention rather than according to actual implementation in schema then
Mesh, shape and size are drawn, when actual implementation kenel, quantity and the ratio of each component can be a kind of random change, and its
Assembly layout kenel may also be increasingly complex.
As shown in fig. 6, the present invention provides a kind of test structure for optimizing laser trimming, it is described to be repaiied for optimizing laser
The test structure of tune includes at least：
Test and configuration code calculate memory module 21, laser fuse module 22, translation interface 23 and internal circuit 24.
As shown in fig. 6, the test and configuration code calculate, memory module 21 connects the internal circuit 24, the laser melts
Silk module 22 and the translation interface 23, for sending test signal TM to the internal circuit 24, and according to the inside
The value FB for the performance parameter that circuit 24 is fed back generate it is corresponding be pre-configured code VLF and configuration code LF, and by the pre-configuration code VLF
And the configuration code LF is separately sent to the translation interface 23 and the laser fuse module 22.
Specifically, the test and configuration code calculate memory module 21 and are generated according to the value FB of the performance parameter of test feedback
It is corresponding to be pre-configured code VLF, and pre-configuration code VLF is stored in the test and configuration code calculating memory module 21.When
When needing to be tested next time, obtained all pre-configuration code VLF are sent to the translation interface 23, by each
It is pre-configured code to be pre-configured the respective performances parameter in the internal circuit 24, after the simulation of the internal circuit 24 trims
Effect is being tested, then the performance parameter currently tested has been carried out on the basis of the performance parameter tested before has trimmed
's.
As shown in fig. 6, the laser fuse module 22 is connected to the test and configuration code calculates the defeated of memory module 21
Outlet.In test phase, the test and configuration code calculate memory module 21 and do not send signal to the laser fuse module 22；
In the stage that trims, the test and configuration code calculate memory module 21 and send configuration code LF, institute to the laser fuse module 22
Laser fuse module 22 is stated each laser fuse module 22 is blown or retained according to the configuration code LF, final with basis
Configuration code LF trims the value of respective performances parameter.
Specifically, as shown in fig. 7, the laser fuse module 22 includes upper trombone slide 221 and laser fuse 222.On described
221 one end of trombone slide connects power supply, the other end connects the laser fuse 222, and in the present embodiment, the upper trombone slide 221 is
PMOS, source connects supply voltage, drain terminal connects the laser fuse 222, grid end connection control signal PB.The laser is molten
It is molten to be blown or are retained the laser by the control of the configuration code LF for the upper trombone slide 221 of one end connection of silk 222, other end ground connection
Silk 222.The link node of the upper trombone slide 221 and the laser fuse 222 is as output end.
As shown in fig. 6, the translation interface 23 be connected to it is described test and configuration code calculate memory module 21 and it is described swash
The output end of light fuse module 22.In test phase, the translation interface 23 receives the test and configuration code calculates storage mould
The pre-configuration code of all pre-configuration code VLF (i) stored in block 21, i=1 ... n-1, and then the performance parameter currently tested
VLF(n)；The stage is being trimmed, is receiving the fuse values of 22 output end of laser fuse module, and then change the value of performance parameter.
Specifically, as shown in fig. 7, the translation interface 23 includes first switch 231, second switch 232 and trigger
233.In the present embodiment, the first switch 231 and the second switch 232 are transmission gate, and control signal is respectively core
Piece enabling signal POR and its inverted signal PORB.The input terminal of the first switch 231 connects the laser fuse module 22, institute
The output end for stating first switch 231 connects the data input pin of the trigger 233, trims the stage, and the first switch 231 is beaten
It opens.The input terminal of the second switch 232 connect it is described test and configuration code calculate memory module 21 output end, described second
The output end of switch 232 connects the data input pin of the trigger 233, test phase, and the second switch 232 is opened.Institute
Trigger 233 is stated for reading and latching the fuse values or the pre-configuration code, in the present embodiment, the trigger 233
For d type flip flop, including data input pin D, clock signal terminal clk, reset terminal CLR and output end Q；Data input pin D connections institute
The output end of first switch 231 and the second switch 232 is stated, clock CLK, reset terminal CLR are read in clock signal terminal clk connections
Connect reset signal CLR, the output end Q connections internal circuit 24.
As shown in fig. 6, the internal circuit 24 connects the output end of the translation interface 23, according to the translation interface 23
The configuration information of offer carries out the test of performance parameter and trims.
Specifically, as shown in fig. 7, the internal circuit 24 includes laser fuse switching tube 241, the first point 242 and the
Two points 243.Implement from this, the laser fuse switching tube 241 is NMOS, drain terminal connect first point 242,
Source connects second point 243, grid end connects the output end of the translation interface 23.In actual circuit, the inside
The device that circuit 24 includes is far above this 3, only symbolically shows in the present embodiment and tests and trim related part
Device is not limited to this embodiment.
Before chip start completion, chip start signal POR is low, and institute is read in the output of the laser fuse module 22
It states trigger 233 and the fuse values is converted to conducting and the pass of laser fuse switching tube 241 after reading clock CLK comes
It is disconnected, to determine that the first point 242 and the second point 243 are the connection relations for connecting also to be off, and then changing internal circuit,
Correlation performance parameters are achieved the purpose that trim in specification limit.After chip start completion, chip start signal POR is
Height, inverted signal PORB are low, are pre-configured code VLF and are read by the laser fuse switching tube 241 by the trigger 233
It arrives, can achieve the purpose that simulating practical laser by the pre-configuration code VLF trims effect.
As shown in fig. 6, in the present embodiment, the laser fuse module 22, the translation interface 23 and the internal electricity
Road 24 is located in same test chip.
As shown in Figure 6 to 8, the present invention also provides a kind of laser trimming methods, in the present embodiment, are used for by above-mentioned
The test structure for optimizing laser trimming is realized.In actual use, circuit structure is unlimited.
The laser trimming method includes at least：
Step S1：In test phase, all pre-configuration codes of chip are obtained by repeatedly testing, n-th of pre-configuration code exists
Before generate on the basis of (n-1) a pre-configuration code；All pre-configuration codes of each chip on wafer are obtained successively.Test phase waits for
Test wafer is located on tester table.
Specifically, as shown in figure 8, the first chip powers on, all pre-configuration codes of first chip are obtained by testing
VLF, then will be electric under first chip；Second chip powers on, and all pre-configurations of second chip are obtained by testing
Code VLF, then will be electric under second chip；And so on, obtain all pre-configuration code VLF of each chip.
More specifically, further comprising as shown in figure 8, obtaining all methods for being pre-configured code of a chip：By the survey
Examination and configuration code calculate memory module 21 and test the first performance parameter of chip, the first performance ginseng fed back
Several value FB, the test and configuration code calculate memory module 21 and obtain the according to the value FB of the first performance parameter of feedback
One is pre-configured code VLF1；The test and configuration code calculating memory module 21 are input to the first pre-configuration code VLF1 described
In internal circuit 24, it is pre-configured code VLF1 with described first simulation is carried out to the first performance parameter and trim, simulation described the
Then the effect that the laser fuse of one performance parameter has trimmed tests the second performance parameter of chip, obtains second
It is pre-configured code VLF2；With described first be pre-configured code VLF1 and described second be pre-configured code VLF2 to the first performance parameter and
Second performance parameter carries out simulation and trims, and simulates the laser fuse of the first performance parameter and second performance parameter
The effect trimmed, then the third performance parameter of chip is tested, it obtains third and is pre-configured code VLF3；The rest may be inferred,
Obtain all pre-configuration codes of the chip.
The testing sequence of each performance parameter is tested successively from low to high with relevancy ranking, the degree of correlation.I.e. latter property is joined
When number is the variable of previous performance parameter, test first is carried out to latter property parameter and simulation trims, in the latter property parameter
Simulation carries out test to the previous performance parameter on the basis of trimming and simulation trims.
In the present invention, when sequential testing is to n-th of performance parameter, all pre-configuration code VLF for testing before
(i), i=1 ... n-1 outputs are described arrives translation interface 23 (all variables for including n-th of performance parameter), simulates true configuration
Code makees the effect after laser trimming, then the configuration code VLF (n) by the performance parameter currently tested tested, be calculated.Its
In, n is the natural number more than 0.
Step S2：The stage is being trimmed, the pre-configuration code of each chip is assigned to the configuration code of corresponding chip, is matched according to described
It sets code laser fuse is blown or retained, to change the value of the performance parameter of each chip, and then completes laser trimming.
Specifically, after the completion of the test phase, wafer is moved to and trims board by power-off.Using each pre-configuration code VLF as
Final configuration code LF is blown or is retained to each laser fuse by the laser fuse module 22, and then to described interior
Each performance parameter in portion's circuit 24 is trimmed, to achieve the purpose that correlation performance parameters to trim in specification limit.
Therefore, the test structure for being used to optimize laser trimming of the invention and laser trimming method obtain on tester table
It is moved to after the configuration code of all chips on wafer and trims board, only need to carry out a laser trimming can complete all properties parameter
Trim, be not necessarily to frequent power-on and power-off, greatly save the testing time, and then reduce testing cost and production cost.
In conclusion the present invention provides a kind of test structure and laser trimming method for optimizing laser trimming, including：
Test signal is sent, and corresponding test and the configuration code for being pre-configured code and configuration code is generated according to the value of the performance parameter of feedback
Calculate memory module；The stage is being trimmed, each laser fuse module is blown or retained according to the configuration code, with to corresponding
The laser fuse module that the value of performance parameter is trimmed；All pre-configuration codes are received in test phase, are received in the stage that trims
The translation interface of fuse values；And internal circuit.Test structure and the laser trimming side for optimizing laser trimming of the present invention
Method, which obtains to move to after the configuration code of all chips on wafer on tester table, trims board, only need to carry out a laser trimming just
Trimming for all properties parameter can be completed, frequent power-on and power-off are not necessarily to, greatlys save the testing time, and then reduce testing cost and life
Produce cost.So the present invention effectively overcomes various shortcoming in the prior art and has high industrial utilization.
The above-described embodiments merely illustrate the principles and effects of the present invention, and is not intended to limit the present invention.It is any ripe
The personage for knowing this technology can all carry out modifications and changes to above-described embodiment without violating the spirit and scope of the present invention.Cause
This, institute is complete without departing from the spirit and technical ideas disclosed in the present invention by those of ordinary skill in the art such as
At all equivalent modifications or change, should by the present invention claim be covered.
Claims (8)
1. a kind of test structure for optimizing laser trimming, which is characterized in that the test knot for optimizing laser trimming
Structure includes at least：
Test and configuration code calculate memory module, laser fuse module, translation interface and internal circuit；
The test and configuration code calculate memory module and connect the internal circuit, the laser fuse module and the conversion
Interface for sending test signal to the internal circuit, and is generated according to the value of the performance parameter of internal circuit feedback
It is corresponding to be pre-configured code and configuration code, and the pre-configuration code and the configuration code are separately sent to the translation interface and institute
State laser fuse module；
The laser fuse module is connected to the test and configuration code calculates the output end of memory module, in the stage that trims, root
Each laser fuse module is blown or retained according to the configuration code, is trimmed with the value to respective performances parameter；
The translation interface is connected to the test and configuration code calculates the output end of memory module and the laser fuse module,
In test phase, receives the test and configuration code calculates all pre-configuration codes stored in memory module, and then obtain current
The pre-configuration code of the performance parameter of test；The stage is being trimmed, the fuse values of the laser fuse module output end, Jin Ergai are received
Become the value of performance parameter；
The internal circuit connects the output end of the translation interface, the configuration information progressive provided according to the translation interface
Can parameter test and trim.
2. the test structure according to claim 1 for optimizing laser trimming, it is characterised in that：The laser fuse mould
Block, the translation interface and the internal circuit are located in same test chip.
3. the test structure according to claim 1 for optimizing laser trimming, it is characterised in that：The laser fuse mould
Block includes upper trombone slide and laser fuse, and upper trombone slide one end connection power supply, the other end connect the laser fuse, the laser
The other end of fuse is grounded, and the link node of the upper trombone slide and the laser fuse is as output end.
4. the test structure according to claim 1 or 3 for optimizing laser trimming, it is characterised in that：The conversion connects
Mouth includes first switch, second switch and trigger, and the input terminal of the first switch connects the laser fuse module, described
The output end of first switch connects the data input pin of the trigger；The second switch input terminal connection it is described test and
Configuration code calculates the output end of memory module, and the output end of the second switch connects the data input pin of the trigger；Institute
Trigger is stated for reading and latching the fuse values or the pre-configuration code.
5. a kind of laser trimming method, which is characterized in that the laser trimming method includes at least：
In test phase, all pre-configuration codes of chip are obtained by repeatedly testing, n-th of pre-configuration code is a pre- at preceding (n-1)
It is generated on the basis of configuration code；All pre-configuration codes of each chip on wafer are obtained successively；
The stage is being trimmed, the pre-configuration code of each chip is being assigned to the configuration code of corresponding chip, according to the configuration code to laser
Fuse is blown or is retained, and to change the value of the performance parameter of each chip, and then completes laser trimming；
Wherein, n is the natural number more than 0.
6. laser trimming method according to claim 5, it is characterised in that：Obtain all methods for being pre-configured code of a chip
Further comprise：The first performance parameter of chip is tested, the value of the first performance parameter is obtained, according to described first
Performance parameter is worth to the first pre-configuration code；Simulation is carried out with the first pre-configuration code to the first performance parameter to repair
It adjusts, then the second performance parameter of chip is tested, obtain the second pre-configuration code；It is pre-configured code and described the with described first
Two pre-configuration codes carry out simulation to the first performance parameter and second performance parameter and trim, then to the third performance of chip
Parameter is tested, and is obtained third and is pre-configured code；The rest may be inferred, obtains all pre-configuration codes.
7. laser trimming method according to claim 6, it is characterised in that：The testing sequence of each performance parameter is with the degree of correlation
Sequence, the degree of correlation are tested successively from low to high.
8. laser trimming method according to claim 5, it is characterised in that：The test phase is complete on tester table
At, it is described to trim the stage and completed on trimming board, test, which is executed, with needs are trimmed powers off switching board.
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| US20030011417A1 (en) * | 2001-07-14 | 2003-01-16 | Chung Hoe-Ju | Delay time controlling circuit and method for controlling delay time |
| CN101131874A (en) * | 2006-08-22 | 2008-02-27 | 富士通株式会社 | Semiconductor integrated circuit and test method thereof |
| CN101510520A (en) * | 2009-03-18 | 2009-08-19 | 上海华岭集成电路技术有限责任公司 | Test method for asynchronously repairing and adjusting silicon wafer with anti-interference |
| CN105281747A (en) * | 2014-05-29 | 2016-01-27 | 中国科学院沈阳自动化研究所 | Fuse trimming and adjusting circuit capable of outputting trimming and adjusting result and control method thereof |
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2017
- 2017-01-23 CN CN201710050816.9A patent/CN108346647B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030011417A1 (en) * | 2001-07-14 | 2003-01-16 | Chung Hoe-Ju | Delay time controlling circuit and method for controlling delay time |
| CN101131874A (en) * | 2006-08-22 | 2008-02-27 | 富士通株式会社 | Semiconductor integrated circuit and test method thereof |
| CN101510520A (en) * | 2009-03-18 | 2009-08-19 | 上海华岭集成电路技术有限责任公司 | Test method for asynchronously repairing and adjusting silicon wafer with anti-interference |
| CN105281747A (en) * | 2014-05-29 | 2016-01-27 | 中国科学院沈阳自动化研究所 | Fuse trimming and adjusting circuit capable of outputting trimming and adjusting result and control method thereof |
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