CN108336223B - Memory device, preparation method of memory device and electronic equipment - Google Patents
Memory device, preparation method of memory device and electronic equipment Download PDFInfo
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Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N50/00—Galvanomagnetic devices
- H10N50/10—Magnetoresistive devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N50/00—Galvanomagnetic devices
- H10N50/01—Manufacture or treatment
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/011—Manufacture or treatment of multistable switching devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/20—Multistable switching devices, e.g. memristors
- H10N70/24—Multistable switching devices, e.g. memristors based on migration or redistribution of ionic species, e.g. anions, vacancies
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Hall/Mr Elements (AREA)
- Mram Or Spin Memory Techniques (AREA)
Abstract
The embodiment of the invention provides a memory device, a preparation method of the memory device and electronic equipment. The memory device includes: the magnetic tunnel junction comprises a resistance change material, a first conductive layer, a magnetic tunnel junction and a second conductive layer which are sequentially laminated; the resistive material is positioned between the first conductive layer and the second conductive layer; the resistance change material is attached to the edge of the magnetic tunnel junction so as to wrap the magnetic tunnel junction; the magnetic tunnel junction includes: a magnetic fixed layer, a barrier layer, and a magnetic free layer laminated in this order; and a conductive channel is formed in the region, close to the magnetic tunnel junction, of the resistance change material, and two ends of the conductive channel are respectively connected to the magnetic fixed layer and the magnetic free layer. The memory device provided by the embodiment of the invention can be equivalent to the parallel connection of the magnetic memory unit and the impedance memory unit in terms of electrical structure, and has the advantages of high read-write speed, unlimited read-write operation, high switching ratio and the like.
Description
Technical Field
The present invention relates to the field of semiconductor technologies, and in particular, to a memory device, a method for manufacturing the memory device, and an electronic apparatus.
Background
Currently, magnetic random access memories (Magnetic Random Memory, MRAM) are new types of nonvolatile memories that do not require continuous power during data storage, reducing the effects of leakage current during device data retention.
Although MRAM has magnetic resistance characteristics, and has characteristics of fast read-write speed, unlimited read-write operations, radiation protection, etc., MRAM has a low ON/OFF ratio. The lower switching ratio makes MRAM in the prior art difficult to meet the demands for higher performance memory devices in practical applications.
Disclosure of Invention
The embodiment of the invention provides a memory device, a preparation method of the memory and electronic equipment, and aims to provide the memory device which has the advantages of high read-write speed, infinite read-write operation and the like and has high switching ratio.
In order to solve the above technical problems, an embodiment of the present invention provides a memory device. The memory device includes: the magnetic tunnel junction comprises a resistance change material, a first conductive layer, a magnetic tunnel junction and a second conductive layer which are sequentially laminated; the resistive material is located between the first conductive layer and the second conductive layer; the resistance change material is attached to the edge of the magnetic tunnel junction so as to wrap the magnetic tunnel junction; the magnetic tunnel junction includes: a magnetic fixed layer, a barrier layer, and a magnetic free layer laminated in this order; the magnetization direction of the magnetic free layer can be turned over under the action of an externally applied magnetic field or polarization current; and a conductive channel is formed in the region, close to the magnetic tunnel junction, of the resistance change material, and two ends of the conductive channel are respectively connected to the magnetic fixed layer and the magnetic free layer.
Optionally, the conductive channel is an ion channel.
Optionally, the magnetic tunnel junction is in an elliptic cylindrical or cylindrical structure; the conductive path includes a plurality of; a plurality of the conductive channels are formed around the sides of the elliptic cylinder or the cylindrical structure.
Optionally, the resistive material includes: silicon oxide, silicon nitride, and hafnium oxide.
Optionally, when the resistive material is silicon oxide, a ratio of a silicon ion concentration to an oxygen ion concentration in a region of the resistive material having a distance of less than 10nm from an interface of the resistive material and the magnetic tunnel junction is a first ratio; the ratio of the concentration of silicon ions to the concentration of oxygen ions in the region of the resistive material, which is more than 10nm away from the interface of the resistive material and the magnetic tunnel junction, is a second ratio; the first ratio is greater than the second ratio; the conductive channel is a silicon ion channel.
Optionally, the magnetic fixing layer includes: a laminated magnetic reference layer and magnetic pinning layer; the magnetic reference layer is located between the magnetic pinning layer and the barrier layer; the magnetization directions in the magnetic reference layer and the magnetic pinning layer are fixed, and the magnetization directions in the magnetic reference layer and the magnetic pinning layer are opposite; wherein the magnetic reference layer and the magnetic free layer comprise ferromagnetic metallic materials; the magnetic pinning layer comprises an antiferromagnetic metal material.
Optionally, the magnetic reference layer further comprises a non-magnetic metallic material and/or an oxide; the magnetic free layer further comprises a non-magnetic metallic material and/or an oxide; the non-magnetic metal material comprises one or more of tantalum, ruthenium, tungsten, iridium and platinum.
Optionally, the magnetic reference layer is an integrated ferromagnetic layer SyF structure.
Optionally, the barrier layer is a magnesium oxide layer; the magnetic free layer is of a double-layer structure and comprises a CoFe layer and a CoFeB layer; the CoFe layer is located between the CoFeB layer and the magnesium oxide layer.
Optionally, the magnetic tunnel junction further comprises: a seed layer in contact with the first conductive layer and a capping layer in contact with the second conductive layer.
In another embodiment of the invention, an electronic device is provided. The electronic equipment comprises the storage device and the semiconductor substrate; the first conductive layer is deposited on the semiconductor substrate.
In another embodiment of the present invention, a method of manufacturing a memory device is provided. The preparation method comprises the following steps: preparing a magnetic tunnel junction on the first conductive layer; depositing a resistance change material on the periphery of the magnetic tunnel junction to obtain a semi-finished product; flattening the semi-finished product to remove the resistive material positioned above the magnetic tunnel junction; and depositing a second conductive layer on the semi-finished product after the planarization treatment to obtain the memory device.
Optionally, depositing a resistive material on the periphery of the magnetic tunnel junction, including: depositing the resistive material over the magnetic tunnel junction by a vapor deposition process; alternatively, spin-coating glass over the magnetic tunnel junction; and annealing the spin-on glass above the magnetic tunnel junction to generate the resistive material.
Optionally, the magnetic tunnel junction includes a seed layer, a magnetic pinning layer, a magnetic reference layer, a barrier layer, a magnetic free layer, and a capping layer.
The embodiment of the invention provides a novel nonvolatile memory unit with impedance characteristics and magnetic resistance characteristics, and the memory unit can be equivalent to the parallel connection of a magnetic memory unit and an impedance memory unit in terms of an electrical structure, has the respective advantages of the magnetic memory unit and the impedance memory unit, namely has the advantages of high switching ratio, quick read-write characteristics, infinite read-write operation and the like, and realizes the integration of a quick calculation function and a stable memory function in the same device unit.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, a brief description will be given below of the drawings required for the embodiments or the prior art descriptions, and it is obvious that the drawings in the following description are some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a memory device according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a memory device according to an embodiment of the present invention without a second conductive layer;
FIG. 3a is a timing diagram of a logic memory according to an embodiment of the present invention;
FIG. 3b is a timing diagram of a transparent memory according to another embodiment of the present invention;
FIG. 4 is a schematic flow chart of a method for manufacturing a memory device according to an embodiment of the present invention;
fig. 5 is a schematic structural diagram of a memory device with conductive channels according to another embodiment of the present invention.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The terminology used in the embodiments of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in this application and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise, the "plurality" generally includes at least two, but does not exclude the case of at least one.
It should be understood that the term "and/or" as used herein is merely one relationship describing the association of the associated objects, meaning that there may be three relationships, e.g., a and/or B, may represent: a exists alone, A and B exist together, and B exists alone. In addition, the character "/" herein generally indicates that the front and rear associated objects are an "or" relationship.
The words "if", as used herein, may be interpreted as "at … …" or "at … …" or "in response to a determination" or "in response to monitoring", depending on the context. Similarly, the phrase "if determined" or "if monitored (stated condition or event)" may be interpreted as "when determined" or "in response to determination" or "when monitored (stated condition or event)" or "in response to monitoring (stated condition or event), depending on the context.
It should also be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a product or system that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such product or system. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a commodity or system comprising such elements.
Prior to describing the technical scheme of the present invention in detail, the prior art in the field is briefly described.
Fig. 1 is a schematic structural diagram of a memory device according to an embodiment of the present invention. As shown in fig. 1, the memory device includes a resistive material 4, a first conductive layer 1, a magnetic tunnel junction 2, and a second conductive layer 3 stacked in this order; the resistive material 4 is located between the first conductive layer 1 and the second conductive layer 3; the resistance change material 4 is attached to the edge of the magnetic tunnel junction 2 so as to wrap the magnetic tunnel junction 2; the magnetic tunnel junction 2 includes: a magnetic fixed layer 21, a barrier layer 22, and a magnetic free layer 23 stacked in this order; wherein, the magnetization direction of the magnetic fixed layer 21 is fixed, and the magnetization direction of the magnetic free layer 23 can be turned over under the action of an externally applied magnetic field or polarization current; a conductive channel is formed in the region of the resistive material 4 near the magnetic tunnel junction 2, and two ends of the conductive channel are respectively connected to the magnetic fixed layer 21 and the magnetic free layer 23.
Wherein the first conductive layer 1 and the second conductive layer 3 include: one or more of tantalum, ruthenium, aluminum, copper, platinum, copper nitride, chromium, gold. As shown in fig. 1, the memory device can be regarded as an inner-outer double-layer structure, the inner-layer structure is formed by a magnetic tunnel junction (Magnetic Tunnel Junctions, MTJ), and the outer-layer structure is formed by a resistive material 4. A conductive channel is formed in the resistive material 4 in a region near the interface of the magnetic tunnel junction 2 and the resistive material 4. The conductive path is electrically connected in parallel with the magnetic tunnel junction. Furthermore, the magnetic tunnel junction 2, the first conductive layer 1 and the second conductive layer 3 constitute an MRAM; the resistive material 4, the first conductive layer 1 and the second conductive layer 3 constitute a RRAM, and thus the above-described memory can be regarded as a parallel structure of MRAM and RRAM. Since the core function unit in the MRAM is an MTJ, and the core function unit in the RRAM is an MIM (Metal-Insulator-Metal), the memory device can be considered as a parallel connection of the MTJ and the MIM as shown in fig. 1.
In the prior art, the MRAM has the characteristics of magnetic resistance, high read-write speed, unlimited read-write operation, radiation protection and the like, but has lower ON/OFF ratio; compared with MRAM, RRAM is limited by the on-off mechanism of the conductive wire, and has the advantages of relatively large switching ratio, good thermal stability, relatively low read-write speed and physically limited read-write times. Therefore, the memory device provided by the invention has the advantages of the MRAM and RRAM due to the parallel characteristic, namely, the memory device not only has the advantages of high read-write speed, infinite read-write operation and the like, but also has the advantages of high switching ratio, good thermal stability and the like. The application of the above-described memory device will be described in detail as follows:
since the MTJ includes a parallel configuration (P) and an antiparallel configuration (AP), and the MIM includes at least a high resistance state (High Resistance State, HRS) and a low configuration (Low Resistance state, LRS), the memory device provided in the embodiment of the present invention includes at least four configurations, i.e., P, AP, HRS and LRS, so that the memory function is realized and the logic computation is also realized.
The basic idea of applying the memory device to logic-in-memory is as follows: by utilizing the characteristic that the MTJs and MIMs are connected in parallel structurally, the MTJs are used for realizing high-speed logic calculation, and the MIMs are used for realizing high-capacity data storage. Wherein the MTJ may flip between a parallel state P and an anti-parallel state AP, and the MIM may flip between a high resistance HRS and a low resistance LRS. When the MIM is in a high resistance state, the MTJ can be used for computational operations, with intermediate results being suspended in the P or AP state of the MTJ. And then, storing the calculation result in the MTJ in the HRS or the LRS of the MIM according to a certain mapping relation (for example, the AP state corresponds to the LRS, and the P state corresponds to the HRS), thereby realizing nonvolatile storage.
For the convenience of understanding the working principle of the logic storage, the following description will be made in a specific implementation manner: for example: the switching voltage of the MTJ in the memory device provided by the present invention is 0.4V, the switching voltage of the MIM is 0.9V, and the resistances of the MTJ and MIM cells used in this example are respectively: r is R AP ＝1390Ω，R P ＝1160Ω，R HRS ＝64500Ω，R LRS ＝660Ω。
The 6 successive states involved in this example are defined as follows:
initializing: (INIT, i.e., defining the initial states of MTJ and MIM at this stage);
computation (com, i.e., implementing a high-speed logic computation function using MTJs during this stage; this stage may include multiple computation operations);
storage (storage, i.e., in this stage the data calculated in the upper stage MTJ is stored in the MIM);
sleep (i.e., power to the device is stopped at this stage), and data is stored in the MIM in a nonvolatile manner);
data recovery (restore), i.e. restore the data stored in the MIM into the MTJ again, prepare for the calculation of the next stage;
computation (com., i.e., high-speed logic computation can be performed using MTJ during this stage).
The timing diagram involved in this application is shown in fig. 3 a: where Voltage refers to an applied Voltage applied across the first conductive layer and the second conductive layer of the memory device shown in fig. 1; the MTJ-State is the State of the MTJ; MIM-State is the MIM State, current is the total current through the memory device.
During initialization, a +0.1V voltage is applied, the initial state of the MTJ is defined as an AP state, and the initial state of the MIM is defined as an HRS state; when +0.4V voltage is applied to the memory device, the MIM unit resistance is kept unchanged and still in an HRS state, and the MTJ is turned from an AP state to a P state; and then entering a calculation stage, carrying out logic calculation by the MTJ, wherein the MIM is always in an HRS state in the calculation stage, reading the state of the MTJ by an external reading circuit when the calculation stage is finished, and if the read MTJ is in an AP state, applying +0.9V voltage to enable the MTJ to be turned over from the AP state to the P state and turning over the MIM from the HRS to the LRS state, so that the calculated result of the MTJ, namely the AP state is stored in the LRS state in the MIM (namely the mapping relation defined above). After the calculation is finished, the device is in a dormant state and waits for the next calculation. Before the next calculation starts, the calculation result stored in the MIM needs to be restored to the MTJ, and the restoration process includes: the state of MIM is read through an external reading circuit, if the read MIM is LRS state, the MTJ can be turned over to AP state by only applying-0.9V voltage no matter what state the MTJ is, meanwhile, the MIM is turned over from LRS to HRS state (note: two purposes of applying-0.9V voltage are that firstly the MTJ is turned over to AP state to realize data recovery, secondly, the MIM is turned over from LRS to HRS state, and the accuracy of the result of logic calculation of the MTJ when the MIM is in high configuration is higher than that when the MIM is in low resistance state). And then proceeds to the next calculation stage.
The supplementary ones are: the stage marked (1) in fig. 3a is the first calculation operation of calculation stage com.1, and the stage marked (2) is the last calculation operation of calculation stage com.1; (6) The marked phase is the first computing operation of the next computing phase com.2.
It should be noted that when the state obtained by the external read circuit reading the MTJ is P-state, since the MIM is already in HRS state (the P-state corresponds to HRS state in the preset mapping relationship), it is not necessary to add +0.9v voltage to store data, and it is only necessary to directly sleep. If the state read from the MIM is the HRS, the MTJ can be turned over to the P state by applying +0.4V (note that if +0.9V is applied, the MIM will be turned over from the HRS to the LRS state, and when the MIM is the LRS state, the logic calculation accuracy of the MTJ will be reduced).
In addition, since the resistance of MIM in the high resistance state HRS is much greater than the resistance of MTJ, and the resistance of MIM in the low resistance state LRS is much lower than the resistance of MTJ. Considering the parallel nature of MTJ and MIM, when MIM is in LRS, the total resistance of the memory device is mainly determined by MIM resistance, at which time the state change of MTJ is difficult to read, and externally appears as if the resistance state of MTJ is "hidden", i.e. MTJ is in "Transparent" state; conversely, when the MIM is in the HRS, the device resistance is primarily determined by the resistance of the MTJ, so that the two configurations of parallel (P) and anti-parallel (AP) of the MTJ are externally readable, corresponding to the MTJ being in an "Opaque" (Opaque) state. Therefore, the memory device in this embodiment can also realize transparent memory.
In this example, the applied magnetic field is used to assist the MTJ flip, and in practical applications, it is not necessary to exist according to the MTJ film design and characteristics. For example: when the thickness of the magnetic free layer in the MTJ is thin, a polarization current can be applied by applying an applied voltage to realize the inversion of the MTJ; when the thickness of the magnetic free layer in the MTJ is thicker, the MTJ flip cannot be realized solely by applying a polarization current, and the MTJ flip can be assisted by adding an external magnetic field. In addition, in the MIM, an electric field is applied by applying an external voltage, and the MIM is inverted by the electric field. When the MIM is in a high-resistance state HRS, the conductive wire in the MIM is in an off state; when the MIM is in the low resistance state LRS, the conductive wire in the MIM is in a conducting state.
Fig. 3b is a timing diagram of a transparent memory application example, where mag field is an auxiliary magnetic field, voltage is an applied Voltage, MTJ-state is an MTJ configuration, MIM-state is an MIM configuration, device-state is a parallel resistance configuration of a memory Device, and current is a total current flowing through the memory Device.
In this example, at the initial stage, the initial state of the MTJ is defined as P-state, and the initial state of the MIM is defined as LRS-state. When a 0Oe magnetic field is applied and a-0.9V voltage is applied, the resistance state of the MTJ is unchanged, and the MIM is turned from an LRS state to an HRS state; when a magnetic field of-104 Oe is applied and a voltage of-0.4V is applied, the resistance state of the MIM is unchanged, and the MTJ is turned from the P state to the AP state.
As can be seen from fig. 3b, in the "Opaque" (Opaque) state phase, when the MIM is in HRS state, the MTJ resistance state is inverted by applying a-0.4V voltage and a-104 Oe magnetic field, or applying a +0.4v voltage and a +110Oe magnetic field, so that the MTJ configuration change can be read.
In the "Transparent" state, when the MIM is in LRS state, a-0.4V voltage and a-104 Oe magnetic field are applied, or a +0.4V voltage and a +110Oe magnetic field are applied, and the flip of the MTJ resistance state is not reflected on the parallel resistance configuration of the memory device, so the configuration change of the MTJ cannot be read.
The resistances of the MTJ and MIM cells in this example are respectively: r is R AP ＝1390Ω，R P ＝1160Ω，R HRS = 64500 Ω and R LRS ＝660Ω。
Embodiments of the present invention provide a novel nonvolatile memory device cell having both resistance and magnetoresistance characteristics, which may be electrically equivalent to a parallel connection of a magnetic memory cell and a resistive memory cell, with both a magnetic memory cell (MRAM) and a resistive memory cell
The RRAM has the advantages of high switching ratio, quick read-write characteristic, infinite read-write operation and the like, and realizes the integration of a quick calculation function and a stable storage function in the same device unit.
Further, the first conductive layer may be deposited on a semiconductor substrate or an insulating substrate. The semiconductor substrate may be a wafer integrated with various devices. I.e. 10 identified in fig. 1 may be a semiconductor substrate or an insulating substrate. The present invention is not particularly limited thereto, and may be selected according to actual needs.
In one possible method, as shown in fig. 1, the magnetic fixing layer 21 is covered on the first conductive layer 1; the second conductive layer 2 is covered on the magnetic free layer 23; the resistive material 4 is attached to the edges of the magnetic fixed layer 21, the magnetic free layer 23 and the barrier layer 22.
In another possible implementation, the magnetic free layer 23 is covered on the first conductive layer 1; the second conductive layer 2 is covered on the magnetic fixing layer 21; the resistive material 4 is attached to the edges of the magnetic fixed layer 21, the magnetic free layer 23 and the barrier layer 22.
The magnetization direction in the magnetic fixed layer 21 is fixed, and the magnetization direction in the magnetic free layer 23 can be reversed under the action of an externally applied polarization current or an externally applied magnetic field.
Note that, a conductive channel is formed in a region of the resistive material 4 near the magnetic tunnel junction 2. The conductive path is present at the interface after the memory device is fabricated. Therefore, when the memory device is applied to logic calculation or transparent storage, the memory device can directly enter a working state, and a large voltage or current does not need to be applied to two ends of the memory device to form a conductive channel, so that power consumption is reduced. Specifically, the conductive channel is an ion channel.
Further, the magnetic tunnel junction 2 may have an elliptic cylindrical or cylindrical structure, and the resistive material 4 is attached to a side surface of the elliptic cylindrical or cylindrical structure. The conductive path includes a plurality of; the plurality of conductive channels are formed around the side surface of the elliptic cylinder or the cylindrical structure, that is, the plurality of conductive channels are sequentially arranged along the circumferential direction of the magnetic tunnel junction of the elliptic cylinder or the cylindrical structure. Two ends of each of the plurality of conductive channels are respectively connected to the magnetic fixed layer 21 and the magnetic free layer 23, and the plurality of conductive channels are all distributed around the side surface of the elliptic cylindrical or cylindrical structure. For example: as shown in fig. 5, platinum manganese, cobalt iron boron, ruthenium, and cobalt iron boron, which are sequentially stacked, are the magnetic fixed layer 21, cobalt iron boron, which is covered on the magnesium oxide, is the magnetic free layer 23, magnesium oxide is the barrier layer 22, and the conductive path 41 is connected to the magnetic fixed layer 21 and the magnetic free layer 23. As shown in fig. 2, the magnetic tunnel junction 2 has an elliptic cylinder shape. Fig. 2 is a plan view, and an upper end surface of the MTJ has an elliptical shape.
In the case of manufacturing an MTJ based on In-plane magnetic anisotropy (In-plane Magnetic Anisotropy, IMA), the MTJ may be designed In an elliptical column shape, so that when the magnetization direction In the magnetic reference layer is fixed by an applied magnetic field, the applied magnetic field may be added along the major axis direction of the ellipse so that the magnetization direction In the magnetic reference layer coincides with the major axis direction. In addition, when the thickness of the magnetic free layer is thicker, an in-plane auxiliary magnetic field can be added along the long axis direction to assist the MTJ to turn over. In preparing an MTJ based on perpendicular magnetic anisotropy (Perpendicular Magnetic Anisotropy, PMA), the MTJ may be provided in either a cylindrical structure. It should be noted that the advantages of the cylindrical structure are: the device size is convenient to reduce and the process is simple.
Specifically, a region of the resistive material close to the magnetic tunnel junction refers to a region of the resistive material that is less than 10nm away from an interface of the resistive material and the magnetic tunnel junction. In general, a positive ion or negative ion aggregation phenomenon occurs in a region of the resistive material, which is located at a distance of less than 10nm from the interface of the resistive material and the magnetic tunnel junction, and the conductive path is formed only because of the positive ion or negative ion aggregation. Therefore, the region where the conductive channel exists is a region of the resistive material, where the distance from the interface between the resistive material and the magnetic tunnel junction is less than 10 nm.
Further, the magnetic pinned layer 21 may be a magnetic reference layer, or a combination of a magnetic reference layer and a magnetic pinning layer. In one possible implementation, the magnetic pinned layer 21 includes a magnetic reference layer in which the magnetization direction is fixed. In another implementation, as shown in fig. 1, the magnetic fixing layer 21 includes: a magnetic reference layer 211 and a magnetic pinning layer 212 stacked; the magnetic reference layer 211 is located between the magnetic pinning layer 212 and the barrier layer 22; the magnetization directions in the magnetic reference layer 211 and the magnetic pinned layer 212 are fixed, and the magnetization directions in the magnetic reference layer 211 and the magnetic pinned layer 212 are opposite; wherein the magnetic reference layer 211 and the magnetic free layer 23 comprise ferromagnetic metal materials; the magnetic pinning layer 212 comprises an antiferromagnetic metal material. Preferably, the magnetic reference layer further comprises a non-magnetic metallic material and/or an oxide; the magnetic free layer further comprises a non-magnetic metallic material and/or an oxide; the non-magnetic metal material comprises one or more of tantalum, ruthenium, tungsten, iridium and platinum. The magnetic properties of the magnetic thin film can be optimized by the non-magnetic metallic material and/or the oxide. The oxide may be a metal oxide, for example: magnesium oxide, aluminum oxide, and the like.
When the magnetization direction in the magnetic free layer 23 is identical to the magnetization direction in the magnetic reference layer 211, the parallel state P is set; when the magnetization direction in the magnetic free layer 23 is opposite to the magnetization direction in the magnetic reference layer 211, the state is an antiparallel state AP. The resistance of the MTJ in the parallel state P is less than the resistance in the anti-parallel state AP.
Further, the conductive path is connected between the magnetic reference layer 211 and the magnetic free layer 23.
In practice, the magnetic pinning layer 212 may be overlaid on the first conductive layer 1; the magnetic reference layer 211 overlies the magnetic pinning layer 212; the barrier layer 22 overlies the magnetic reference layer 211; the magnetic free layer 23 is overlaid on the barrier layer 22, and the second conductive layer 3 is overlaid on the magnetic free layer 23. Alternatively, the magnetic free layer 23 is covered on the first conductive layer 1, the barrier layer 22 is covered on the magnetic free layer 23, and the magnetic reference layer 211 is covered on the barrier layer 22; the magnetic pinning layer 212 is overlaid on the magnetic reference layer 211 and the second conductive layer is overlaid on the pinning layer 212.
The fixed magnetization direction in the magnetic reference layer 211 is ensured by the antiferromagnetic coupling between the magnetic reference layer 211 and the magnetic pinning layer 212.
The resistive material includes: silicon oxide (SiO) x ) One or more of silicon nitride and hafnium oxide, and in addition, the resistive material may further include: al (Al) 2 O 3 ,CoO,NiO,FeO x ,Cu x O,TiO 2 ,MnO 2 ,TaO x ，ZnO，ZrO 2 Wherein x is a number greater than or equal to 1.
When the resistive material 4 is silicon oxide (SiO x ) When the ratio of the silicon ion concentration to the oxygen ion concentration in the region of the resistive material 4, which is at a distance of less than 10nm from the interface of the resistive material 4 and the magnetic tunnel junction 2, is a first ratio; the resistance change materialThe ratio of the silicon ion concentration to the oxygen ion concentration in the region of the material 4, which is more than 10nm away from the interface of the resistive material 4 and the magnetic tunnel junction 2, is a second ratio; the first ratio is greater than the second ratio; the conductive channel is a silicon ion channel. That is, silicon ion aggregation occurs in a region of the resistive material 4 having a distance of less than 10nm from the interface of the resistive material 4 and the magnetic tunnel junction 2, thereby forming a silicon ion channel.
When the resistive material is silicon oxide (SiO x ) When the conductive path, also called conductive filament (Conductive filament, CF), is a Si ion path (Si path), it should be understood that: the conductive filaments CF may be formed of other ion channels in the case of other resistive materials.
Further, the magnetic reference layer 211 is a composite ferromagnetic layer SyF (synthetic ferrimagnetic) structure consisting of a ferromagnetic layer/a non-ferromagnetic layer/a ferromagnetic layer, i.e., a non-ferromagnetic layer is included between two ferromagnetic layers, for example: in fig. 5, the magnetic reference layer 211 includes a cobalt-iron-boron layer, a ruthenium layer, and a cobalt-iron-boron layer that are sequentially stacked, wherein the ruthenium layer is a non-ferromagnetic layer. The leakage magnetic field (stray magnetic field) applied to the magnetic free layer 23 can be reduced as compared to a single ferromagnetic layer structure, thereby ensuring the free flip characteristic of the magnetic free layer.
Further, the barrier layer 22 is a magnesium oxide layer or an aluminum oxide layer. The present embodiment is not particularly limited thereto, and may be selected according to actual needs.
It should be noted that when the barrier layer 22 is a magnesium oxide layer, it is preferable that the magnetic free layer 23 has a double-layer structure including a CoFe layer and a CoFeB layer; the CoFe layer is located between the CoFeB layer and the magnesium oxide layer. The magnetic free layer 23 is configured as a double-layer structure as described above, and boron B in the CoFeB layer is effectively prevented from diffusing into the magnesium oxide layer, so that damage to the magnesium oxide layer and the body-centered cubic (cubic) lattice structure of the CoFeB layer due to boron B diffusion is avoided, and further, degradation of tunnel magnetoresistance (Tunnel Magnetoresistance, TMR) due to lattice structure damage is avoided (note: the greater TMR, the better MTJ reliability).
As shown in fig. 5, the magnetic free layer 23 may have a simple single-layer structure, for example: cobalt iron boron CoFeB is a single layer.
Further, as shown in fig. 5, the magnetic tunnel junction 2 further includes: a seed layer 25 in contact with the first conductive layer 1 and a capping layer 24 in contact with the second conductive layer 3. That is, the magnetic tunnel junction includes a seed layer 25, a magnetic pinning layer 212, a magnetic reference layer 211, a barrier layer 22, a magnetic free layer 23, and a capping layer 24. The design of the seed layer and capping layer is a requirement to allow for resistance matching for wafer-level CIPT testing (Current-in-plane tunneling measurement). Tunnel magnetoresistance (Tunnel magnetoresistance, TMR) and Resistance area product (RA) were obtained by CIPT testing. In one possible implementation, a seed layer, a magnetic pinning layer, a magnetic reference layer, a barrier layer, a magnetic free layer, and a capping layer are sequentially deposited on the first conductive layer, where the capping layer overlies the magnetic free layer (i.e., the capping layer is located between the magnetic free layer and the second conductive layer), and effectively prevents oxidation of metals in the magnetic free layer. In another implementation scheme, a seed layer, a magnetic free layer, a barrier layer, a magnetic reference layer, a magnetic pinning layer and a cover layer are sequentially deposited on the first conductive layer, and the cover layer covers the magnetic pinning layer (namely, the cover layer is located between the magnetic pinning layer and the second conductive layer), so that metal in the magnetic pinning layer is effectively prevented from being oxidized.
In one implementation, the magnetic tunnel junction 2 includes a magnetic pinning layer 212 of antiferromagnetic metal: platinum manganese PtMn; magnetic reference layer 211 of ferromagnetic metal: sequentially stacking cobalt iron boron CoFeB, cobalt iron CoFe, ruthenium Ru, cobalt iron boron CoFeB and cobalt iron CoFe (note: in the embodiment, the magnetic reference layer 211 has a five-layer structure, and the intermediate ruthenium Ru is a nonmagnetic metal layer); barrier layer 22: magnesium oxide MgO; magnetic free layer 23 of ferromagnetic metal: laminated cobalt iron CoFe and cobalt iron boron CoFeB (note: the magnetic free layer 23 is a bilayer structure).
The composition ratio of the elements in the ferromagnetic metal material may be different, and the thickness of each layer in the magnetic reference layer 211 and the magnetic free layer 23 may be in the range of 0 to 5nm. For example: co in CoFeB is cobalt iron boron, and B=40:40:20, and Co is cobalt iron, and Fe=75:25. The barrier layer 22 contains magnesium oxide MgO and has a thickness in the range of 0 to 2nm. The first conductive layer may be tantalum (Ta) and ruthenium (Ru) stacked, and the second conductive layer may include chromium (Cr), gold (Au), and a total thickness ranging from 10 to 300nm.
In addition, the resistive material may be spin coated onto glass by spin coating, for example: spin-coating Spin-on polymer Accuflo, spin-coating and annealing are completed, the annealed resistive material comprises silicon oxide, and the closer to the interface of the resistive material and the magnetic tunnel junction, the more silicon ions and the less oxygen ions are. The upper end surface of the MTJ is elliptical and may be nano-sized. Wherein Spin-on polymer Accuflo contains elements such as silicon, oxygen, carbon, hydrogen, etc.
It should be noted that, when the conductive wire is formed in the region close to the magnetic tunnel junction in the resistive material in the prepared memory device, the memory device is structurally that the conductive wire (RRAM unit) is wrapped around the magnetic tunnel junction (MRAM unit), and the resistive material and the memory device are in an electrically parallel state. Wherein the magnetic tunnel junction may be based on perpendicular magnetic anisotropy (Perpendicular Magnetic Anisotropy, PMA) or In-plane magnetic anisotropy (In-plane Magnetic Anisotropy), MTJs may vary In material type, film thickness, shape, and the like. The device is of a double-layer structure, the inner-layer structure is composed of a traditional MTJ, a bottom electrode, a magnetic tunnel junction (a magnetic pinning layer, a magnetic reference layer, a barrier layer and a magnetic free layer) and a top electrode are sequentially arranged from bottom to top, and the outer layer is made of a resistance change material. The magnetic tunnel junction may include a magnetic pinning layer of antiferromagnetic metal, a magnetic reference layer of ferromagnetic metal, a barrier layer, and a magnetic free layer of ferromagnetic metal. The magnetic free layer and the magnetic reference layer comprise one or more of mixed metal materials including cobalt iron CoFe, cobalt iron boron CoFeB or nickel iron NiFe, the composition ratio of the elements in the mixed metal materials can be different, the magnetic free layer and the magnetic reference layer are both in a multi-layer structure, and the thickness range of each layer in the magnetic free layer and the magnetic reference layer is 0-5 nm; the barrier layer (i.e. oxide barrier layer) comprises magnesium oxide MgO and aluminum oxide Al 2 O 3 Hafnium oxide HfO 2 Or other oxides, in a thickness range of 0 to 10nm. The specific thicknesses of the layers of the magnetic tunnel junction, particularly the thicknesses of the magnetic free layer and the oxide barrier layer, can be selected in combination with specific practical application and process requirements. The magnetic free layer and the magnetic reference layer comprise non-magnetic metal materials and/or oxides besides ferromagnetic metals, and the magnetic free layer further comprises non-magnetic metal materials and/or oxides for optimizing the magnetic properties of the thin film; the non-magnetic metal is selected from one of metallic materials of tantalum (Ta), ruthenium (Ru), tungsten (W), iridium (Ir) and platinum (Pt) and a combination thereof, and the thickness range is 0-5 nm; the magnetic pinning layer comprises, but is not limited to, mixed metal materials of platinum-manganese PtMn, iridium-manganese IrMn, cobalt-platinum multilayer film [ Co/Pt ]] n And cobalt palladium multilayer film [ Co/Pd] n The thickness range is 0-50 nm, wherein n is a natural number greater than or equal to 1.
The details of an MTJ with in-plane magnetic anisotropy will be described below:
the film structure of the magnetic tunnel junction MTJ2 is sequentially from bottom to top in fig. 1: ta (5)/Ru (15)/Ta (5)/Ru (15)/Ta (5)/Ru (5)/PtMn (20)/CoFeB (1.5)/CoFe (2.0)/Ru (0.85)/CoFeB (1.5)/CoFe (1.5)/MgO (0.8)/CoFe (1.5)/CoFeB (1.5)/Ru (2)/Ta (5)/Ru (10), the thickness of the film layer being in brackets in nanometers, the symbol "/" being understood to be the interface between two adjacent films, for example: the "/" in Ta/Ru indicates the interface between the Ta layer and the Ru layer.
The first conductive layer is formed by using Ru (5) in the Ta (5)/Ru (15)/Ta (5)/Ru (15)/Ru (5) as a seed layer, wherein the bottommost Ta (5)/Ru (15)/Ta (5) in the seed layer can be used as the first conductive layer; the core layer structure of MTJ2 comprises PtMn (20)/CoFeB (1.5)/CoFe (2.0)/Ru (0.85)/CoFeB (1.5)/CoFe (1.5)/MgO (0.8)/CoFe (1.5)/CoFeB (1.5), wherein PtMn (20) is the magnetic pinning layer; coFeB (1.5)/CoFe (2.0)/Ru (0.85)/CoFeB (1.5)/CoFe (1.5) is a magnetic reference layer structure having an integrated ferromagnetic layer SyF (Synethetic Ferrimagnetic) structure consisting of a ferromagnetic layer/non-ferromagnetic layer, which reduces the leakage magnetic field (stray magnetic field) applied to the magnetic free layer 23 compared to a single ferromagnetic layer structure, thereby ensuring the free inversion property of the magnetic free layer; mgO (0.8) is a barrier layer 22, and CoFe (1.5)/CoFeB (1.5) is a magnetic free layer 23; ru (2) in Ru (2)/Ta (5)/Ru (10) is a capping layer.
The memory device provided by the embodiment of the invention is structurally: the conductive wire wraps around the magnetic tunnel junction to form a parallel structure of the conductive wire and the magnetic tunnel junction, so that the parallel connection of the MRAM and the RRAM is realized.
And (3) carrying out annealing treatment after spin-coating spin-on glass on the magnetic tunnel junction, so that conductive wires can be formed around the MTJ, and the parallel connection of the MTJ and the MIM is realized. The memory device can perform logic calculation in an MRAM structure (MTJ), perform storage in an RRAM structure (CF), and realize combination of calculation and storage in the same structure. In addition, the transparent storage function of the MTJ can be realized through the high-low resistance state of the RRAM.
The beneficial effects of the invention are as follows:
(1) The parallel connection of the MRAM cell and the RRAM cell is implemented in the same device.
(2) The device combines the advantages of two different memories, namely the MRAM and the RRAM, uses the MRAM with high reading and writing speed and unlimited times of reading and writing to perform a logic calculation function, and uses the RRAM with good data storage thermal stability to realize a storage function.
(3) The device uses the MRAM part to carry out logic calculation and uses the RRAM part to carry out storage, thereby realizing the integration of logic calculation and storage functions, and can also use the parallel structure to realize the transparent storage function, namely the conducting wire mainly plays a role of selecting, namely the transparent state or the non-transparent state.
(4) Prior art RRAM requires a process of forming conductive filaments before each start of operation, i.e., a large voltage or current is applied to form conductive filaments in the RRAM. This causes a loss in power consumption due to the large voltage or current that needs to be applied during this process. The memory device provided by the invention has the advantages that the conductive wires are formed after the preparation of the memory device is finished, so that the conductive wires do not need to be formed by applying larger voltage or current before each starting operation, and the power consumption is reduced.
The invention also provides an electronic device, which comprises the memory device and a semiconductor substrate; the first conductive layer is deposited on the semiconductor substrate. The memory device comprises a resistive material 4, a first conductive layer 1, a magnetic tunnel junction 2 and a second conductive layer 3 which are sequentially stacked; the resistive material 4 is located between the first conductive layer 1 and the second conductive layer 3; the resistance change material 4 is attached to the edge of the magnetic tunnel junction 2 so as to wrap the magnetic tunnel junction 2; the magnetic tunnel junction 2 includes: a magnetic fixed layer 21, a barrier layer 22, and a magnetic free layer 23 stacked in this order; wherein, the magnetization direction of the magnetic fixed layer 21 is fixed, and the magnetization direction of the magnetic free layer 23 can be turned over under the action of an externally applied magnetic field or polarization current; a conductive channel is formed in the region of the resistive material 4 near the magnetic tunnel junction 2, and two ends of the conductive channel are respectively connected to the magnetic fixed layer 21 and the magnetic free layer 23.
Fig. 4 is a flow chart of a method for manufacturing a memory device according to another embodiment of the present invention. As shown in fig. 4, the preparation method includes:
101. A magnetic tunnel junction is fabricated on the first conductive layer.
102. And depositing a resistance change material on the periphery of the magnetic tunnel junction to obtain a semi-finished product.
103. And flattening the semi-finished product to remove the resistive material positioned above the magnetic tunnel junction.
104. And depositing a second conductive layer on the semi-finished product after the planarization treatment to obtain the memory device.
In step 101, a physical deposition method may be used to sequentially deposit the films of the magnetic tunnel junction on the first conductive layer. Typically, the magnetic tunnel junction includes: a magnetic fixed layer, a barrier layer and a magnetic free layer. The deposition sequence of each layer of film in the magnetic tunnel junction is selected from the following two choices: a magnetic fixed layer- > a barrier layer- > a magnetic free layer is deposited; selecting two: magnetic free layer- > barrier layer- > magnetic fixed layer. Wherein the symbol "- >" indicates the next step. In practice, different deposition sequences may be selected according to the actual application.
The step of sequentially depositing the first conductive layer and each layer of the magnetic tunnel junction may be, but not limited to, magnetron Sputtering (Sputtering), atomic layer deposition (Atomic layer deposit, atomic layer deposition), pulsed laser deposition (Pulsed laser deposition ), molecular beam epitaxy (Molecularbeam epitaxy, MBE), electron beam evaporation (E-beam evap), and the like.
When the magnetic pinned layer includes: when the magnetic pinning layer and the magnetic reference layer are used, the deposition sequence is selected as follows: magnetic pinning layer- > magnetic reference layer- > barrier layer- > magnetic free layer deposited; selecting two: magnetic free layer- > barrier layer- > magnetic reference layer- > magnetic pinning layer.
When the magnetron sputtering is adopted to deposit each layer of film in the magnetic tunnel junction, the deposition process is carried out by bombarding the surface of the target material with argon ions under the high vacuum condition. Targets used include, but are not limited to, cobalt iron boron (CoFeB), cobalt iron (CoFe), magnesium oxide (MgO), aluminum oxide (Al 2 O 3 ) Ruthenium (Ru), tantalum (Ta), tungsten (W), cobalt (Co), platinum (Pt), palladium (Pd), nickel iron (NiFe), iridium (Ir), iridium manganese (IrMn), platinum manganese (PtMn), and the like. In a particular example, the base pressure (base pressure) prior to the magnetron sputtering process is 3×10 -8 Torr is equal to or higher than 3.10 -8 Torr。
In the process of deposition, the thin film deposited later can completely cover the thin film deposited before, and the situation that the magnetic free layer is contacted with the magnetic fixed layer can occur at the edge of each layer of thin film, therefore, the edges of each layer of thin film in the magnetic tunnel junction are required to be removed through photoetching, etching and other processes so as to reserve the central area of each layer of thin film, the boundary of each layer of thin film in the magnetic tunnel junction can be exposed, the problems of device failure and the like caused by contact between the magnetic free layer and the magnetic fixed layer are avoided, and the preparation of the magnetic tunnel junction is realized. Preferably, the layers of the magnetic tunnel junction are deposited by a magnetron sputtering method.
In step 102, depositing a resistive material on the periphery of the magnetic tunnel junction may be performed by one of the following methods:
spin-coating glass over the magnetic tunnel junction; annealing the magnetic tunnel junction spin-coated with the spin-on glass to generate the resistive material. For example: spin-on glass on the periphery of the magnetic tunnel junction, for example: spin-on glass may be Spin-onpolymer Accuflo. After spin coating, it is heated to perform an annealing operation. The spin-on glass method is adopted as the process used in spin-on coating. The annealing temperature is between 100 ℃ and 300 ℃. The annealing temperature is between 100 and 300 ℃, so that controllable conductive wires can be formed at the interface of the magnetic tunnel junction and the resistance change material, and the prepared memory device has better and more stable performance. Annealing may be performed using a hot plate (hot plate) or an oven (oven). Preferably, the annealing temperature is between 110 ℃ and 290 ℃. Spin coating glass on the upper end face and the side end faces of the magnetic tunnel junction is completed at one time.
In one embodiment, the spin-on-glass magnetic tunnel junction is annealed in a hot plate or oven at an annealing temperature of 100 ℃ or 300 ℃ to produce a resistive material, and experiments prove that conductive filaments can be formed at the interface using an annealing temperature of 100 ℃ or 300 ℃. In another embodiment, the spin-on-glass magnetic tunnel junction is annealed in a hot plate or oven at an annealing temperature of 110 ℃ or 290 ℃ to produce a resistive material, and experiments prove that conductive wires can be formed at the interface by using an annealing temperature of 110 ℃ or 290 ℃.
And a second method. Depositing the resistive material over the magnetic tunnel junction using a vapor deposition process, such as: deposition of silicon oxide (SiO) x Wherein x is a number of 1 or more) or a resistive material such as silicon nitride (SiN). The deposition is selected from PECVD (Plasma enhanced chemical vapordeposition ), sputtering, ALD (Atomiclayer deposit, atomic layer deposition), PLD (Pulsed laser deposition ) and low pressure chemical vapor deposition (Low pressure chemical vapor deposition, LPCVD)One or more of them. Preferably, a plasma enhanced chemical vapor deposition mode is adopted to directly deposit a resistance change material on the periphery of the magnetic tunnel junction; or LPCVD is adopted to deposit silicon oxide on the periphery of the magnetic tunnel junction, and Tetraethoxysilane (TEOS) is adopted as a raw material.
It should be noted that, before the magnetic tunnel junction is fabricated, a magnetron sputtering method may be used to deposit the first conductive layer on a semiconductor substrate, an insulating substrate, or other wafers integrated with various devices.
After the semi-finished product is obtained in step 102, the upper end surface of the magnetic tunnel junction is completely covered with the resistive material, so that the semi-finished product needs to be planarized to remove the resistive material above the magnetic tunnel junction. And the planarization treatment is adopted, so that the upper part of the magnetic tunnel junction is smoother, and the subsequent deposition of the second conductive layer is facilitated.
In step 104, a second conductive layer may be formed on the magnetic tunnel junction using photolithography, etching, damascene, and other processes. The second conductive layer may be a stack of chromium (Cr) and gold (Au). In specific implementation, the top electrode pattern may be first photoetched by using an ultraviolet exposure mode, then 5nm of Cr and 300nm of Au are sequentially deposited by using an electron beam evaporation mode to obtain the second conductive layer, and finally a lift-off process (lift-off) is performed to remove the photoresist, so as to obtain the top electrode. The top electrode material may comprise one of Al, ta, cr, cu, au or Pt, and combinations thereof.
The memory device prepared by the preparation method of the memory device has the novel nonvolatile memory device unit with the impedance characteristic and the magnetic resistance characteristic, and the memory device can be equivalent to the parallel connection of a magnetic memory unit and an impedance memory unit in terms of electrical structure, has high switching ratio, quick read-write characteristic and high thermal stability, can exhibit a plurality of nonvolatile resistance states, and realizes the integration of a quick calculation function and a stable memory function in the same device unit.
In one possible implementation, a magnetic tunnel junction is fabricated on a first conductive layer, comprising: sequentially depositing a multilayer film in the magnetic tunnel junction on the first conductive layer; the multilayer film is etched by photolithography to form an elliptic cylindrical or cylindrical magnetic tunnel junction.
In practice, magnetic tunnel junctions having particular shapes, including cylindrical, elliptical, or other shapes, may be prepared depending on the circumstances. From the above analysis, it can be seen that when preparing an MTJ with in-plane magnetic anisotropy, it can be designed into an elliptic cylindrical structure; in preparing the perpendicular magnetic anisotropic MTJ, it may be designed in a cylindrical structure.
Further, forming the elliptic cylindrical or cylindrical magnetic tunnel junction by photolithography and etching the multilayer film includes: forming a first mask plate with an elliptical or circular pattern on the upper end surface of the multilayer film through a photoetching process; and etching the multilayer film through the first mask plate by adopting a dry etching process to form the elliptic cylinder or cylindrical magnetic tunnel junction. Preferably, the etching may be performed by a hybrid process of inductively coupled plasma etching (inductively coupled plasma, ICP), reactive-Ion etching (RIE), and Ion milling (Ion milling), which is a pattern transfer process.
Further, the multilayer film of the magnetic tunnel junction comprises a seed layer, a magnetic pinning layer, a magnetic reference layer, a barrier layer, a magnetic free layer and a capping layer. The design of the seed layer and capping layer is a requirement to allow for resistance matching for wafer-level CIPT testing (Current-in-plane tunneling measurement). Tunnel magnetoresistance (Tunnel magnetoresistance, TMR) and Resistance area product (RA) were obtained by CIPT testing. In one possible implementation, a seed layer, a magnetic pinning layer, a magnetic reference layer, a barrier layer, a magnetic free layer, and a capping layer are sequentially deposited on the first conductive layer, where the capping layer overlies the magnetic free layer (i.e., the capping layer is located between the magnetic free layer and the second conductive layer), and effectively prevents oxidation of metals in the magnetic free layer. In another implementation scheme, a seed layer, a magnetic free layer, a barrier layer, a magnetic reference layer, a magnetic pinning layer and a cover layer are sequentially deposited on the first conductive layer, and the cover layer covers the magnetic pinning layer (namely, the cover layer is located between the magnetic pinning layer and the second conductive layer), so that metal in the magnetic pinning layer is effectively prevented from being oxidized. The capping layer and the seed layer may both be ruthenium Ru layers. The design of the seed layer and the capping layer also satisfies the requirements for resistance matching for wafer-level CIPT test (Current-in-plane tunneling measurement).
It should be noted that after the magnetic tunnel junction with the specific shape is obtained through the photolithography and etching process, the photolithography and etching process may be continuously used to continuously etch the first conductive layer located under the magnetic tunnel junction to obtain the bottom electrode.
The bottom electrode with micrometer scale is photoetched by ultraviolet photoetching process, and the nanometer-sized MTJ junction region is photoetched by electron beam exposure process.
Generally, after each layer of film in the magnetic tunnel junction is deposited, vacuum annealing treatment is required for each layer of film to fix the magnetization direction of the magnetic reference layer and optimize the characteristics such as the crystal structure of each magnetic layer. In particular, for the preparation of the MTJ oriented to magnetic anisotropy, a magnetic reference layer with a good magnetization direction fixed can be obtained by vacuum annealing treatment.
Preferably, during the vacuum annealing, the magnetization direction in the magnetic reference layer can be determined by adding an external magnetic field, and the magnetization direction in the magnetic reference layer is consistent with the magnetic field direction of the external magnetic field. For example: setting the magnetic field to be 1T-2T, the temperature to be 300-400 ℃ and the vacuum degree to be 10 -6 Torr is equal to or better than 10 -6 Torr. In preparing the MTJ facing magnetic anisotropy, the annealing condition is preferably 350 ℃ and the annealing time is 1 hour, and the magnetic field is an in-plane magnetic field of 1T. When preparing the perpendicular magnetic anisotropic MTJ, the ultra-high magnetic field vacuum annealing equipment is adopted, the magnetic field is set to be about 0T to 1T, and the temperature is between 200 ℃ and 500 ℃ to be better than 10 DEG C -8 And (5) carrying out Torr vacuum annealing treatment. After vacuum annealing, the morphology preparation of the magnetic tunnel junction structure is completed by using the traditional nano device processing technologies such as photoetching, etching, planarization and the like.
The bottom electrode and the top electrode are selected from, but not limited to, one of metallic materials tantalum (Ta), ruthenium (Ru), aluminum (Al), copper (Cu), platinum (Pt), copper nitride (CuN), and combinations thereof, and have a thickness in the range of 10 to 200nm. Typically, the memory device has a total thickness of between 100nm and 200nm after fabrication is complete.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and are not limiting; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention.
Claims (14)
1. A memory device, comprising: the magnetic tunnel junction comprises a resistance change material, a first conductive layer, a magnetic tunnel junction and a second conductive layer which are sequentially laminated;
The resistive material is located between the first conductive layer and the second conductive layer;
the resistance change material is attached to the edge of the magnetic tunnel junction so as to wrap the magnetic tunnel junction;
the magnetic tunnel junction includes: a magnetic fixed layer, a barrier layer, and a magnetic free layer laminated in this order; the magnetization direction of the magnetic free layer can be turned over under the action of an externally applied magnetic field or polarization current;
and a conductive channel is formed in the region, close to the magnetic tunnel junction, of the resistance change material, and two ends of the conductive channel are respectively connected to the magnetic fixed layer and the magnetic free layer.
2. The memory device of claim 1, wherein the conductive channel is an ion channel.
3. The memory device of claim 1, wherein the magnetic tunnel junction is in an elliptical or cylindrical configuration;
the conductive path includes a plurality of; a plurality of the conductive channels are formed around the sides of the elliptic cylinder or the cylindrical structure.
4. The memory device of any of claims 1-3, wherein the resistive material comprises: silicon oxide, silicon nitride, and hafnium oxide.
5. The memory device of claim 4, wherein when the resistive material is silicon oxide, a ratio of a silicon ion concentration to an oxygen ion concentration in a region of the resistive material that is less than 10nm away from an interface of the resistive material and the magnetic tunnel junction is a first ratio;
the ratio of the concentration of silicon ions to the concentration of oxygen ions in the region of the resistive material, which is more than 10nm away from the interface of the resistive material and the magnetic tunnel junction, is a second ratio;
the first ratio is greater than the second ratio;
the conductive channel is a silicon ion channel.
6. The memory device of any one of claims 1-3, wherein the magnetic pinned layer comprises: a laminated magnetic reference layer and magnetic pinning layer;
the magnetic reference layer is located between the magnetic pinning layer and the barrier layer;
the magnetization directions in the magnetic reference layer and the magnetic pinning layer are fixed, and the magnetization directions in the magnetic reference layer and the magnetic pinning layer are opposite;
wherein the magnetic reference layer and the magnetic free layer comprise ferromagnetic metallic materials; the magnetic pinning layer comprises an antiferromagnetic metal material.
7. The memory device of claim 6, wherein the magnetic reference layer further comprises a non-magnetic metallic material and/or an oxide; the magnetic free layer further comprises a non-magnetic metallic material and/or an oxide;
the non-magnetic metal material comprises one or more of tantalum, ruthenium, tungsten, iridium and platinum.
8. The memory device of claim 6, wherein the magnetic reference layer is an integrated ferromagnetic layer SyF structure.
9. The memory device of claim 8, wherein the barrier layer is a magnesium oxide layer;
the magnetic free layer is of a double-layer structure and comprises a CoFe layer and a CoFeB layer;
the CoFe layer is located between the CoFeB layer and the magnesium oxide layer.
10. The memory device of any of claims 1-3, wherein the magnetic tunnel junction further comprises: a seed layer in contact with the first conductive layer and a capping layer in contact with the second conductive layer.
11. An electronic device comprising the memory device of any one of claims 1-10 and a semiconductor substrate; the first conductive layer is deposited on the semiconductor substrate.
12. A method of manufacturing a memory device, comprising:
Preparing a magnetic tunnel junction on the first conductive layer;
depositing a resistance change material on the periphery of the magnetic tunnel junction to obtain a semi-finished product;
flattening the semi-finished product to remove the resistive material positioned above the magnetic tunnel junction;
and depositing a second conductive layer on the semi-finished product after the planarization treatment to obtain the memory device.
13. The method of manufacturing of claim 12, wherein depositing a resistive material on a periphery of the magnetic tunnel junction comprises:
depositing the resistive material over the magnetic tunnel junction by a vapor deposition process;
or,
spin-coating spin-on glass over the magnetic tunnel junction; and annealing the spin-on glass above the magnetic tunnel junction to generate the resistive material.
14. The method of claim 12 or 13, wherein the magnetic tunnel junction comprises a seed layer, a magnetic pinning layer, a magnetic reference layer, a barrier layer, a magnetic free layer, and a capping layer.
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| CN113471245A (en) * | 2020-03-30 | 2021-10-01 | 中芯国际集成电路制造(深圳)有限公司 | MRAM device and method of forming the same |
| CN112054035A (en) * | 2020-09-15 | 2020-12-08 | 中国科学院微电子研究所 | Memory device and manufacturing method thereof |
| CN112164706B (en) * | 2020-09-21 | 2022-11-08 | 上海磁宇信息科技有限公司 | Magnetic memory and manufacturing method thereof |
| CN112928206B (en) * | 2021-01-28 | 2022-08-19 | 广东省大湾区集成电路与系统应用研究院 | MTJ (magnetic tunnel junction) and driving method and manufacturing method thereof |
| CN113744777B (en) * | 2021-09-08 | 2024-01-02 | 北京航空航天大学 | Memory cell of magnetic random access memory and data multi-state memory control method |
| CN113866691B (en) * | 2021-12-02 | 2022-09-23 | 北京芯可鉴科技有限公司 | Tunneling magneto-resistance sensor and preparation method and using method thereof |
| CN115077750A (en) * | 2022-05-16 | 2022-09-20 | 南京邮电大学 | Pressure sensor based on black phosphorus barrier layer magnetic tunnel junction and preparation method |
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