CN108323009A - Device architecture and device layout - Google Patents
Device architecture and device layout Download PDFInfo
- Publication number
- CN108323009A CN108323009A CN201810027111.XA CN201810027111A CN108323009A CN 108323009 A CN108323009 A CN 108323009A CN 201810027111 A CN201810027111 A CN 201810027111A CN 108323009 A CN108323009 A CN 108323009A
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- Prior art keywords
- top layer
- welding end
- cell
- present
- architecture
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- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K7/00—Constructional details common to different types of electric apparatus
- H05K7/02—Arrangements of circuit components or wiring on supporting structure
- H05K7/023—Stackable modules
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10431—Details of mounted components
- H05K2201/10507—Involving several components
- H05K2201/10515—Stacked components
Abstract
Device architecture of the present invention, including：Bottom device cell, the bottom device cell welding is on a printed circuit board；Top layer device cell, the top layer device cell are welded on the bottom device cell.Device architecture and device layout of the present invention make full use of the space of height to limit, in in a limited space, increase the density of layout to reduce the area for accounting for plate of device, increase battery capacity to reduce the cabling of plank and account for plate space, effectively reduce the length of cabling, impedance is reduced, the competitiveness of product is promoted.
Description
Technical field
The present invention relates to printed wiring board fields, more particularly to surface mount (SMT) and device encapsulation field, especially
A kind of device architecture and device layout.
Background technology
The layout density of device is closer and closer, how smaller plank be spatially laid out as far as possible more devices come
Meet the design requirement of hardware.
On the one hand, device spacing reduces the area for accounting for plate, but device is also being miniaturized, and leads to the limited area reduced.
If the space of 24mm × 24mm can place 4 × 4 devices originally, now due to device accounts for plate suqare diminution, same area can
To place 6 × 6 devices, the layout density of device is by original 16/24/24=0.0278/mm2Promote 36/24/24
=0.06/mm2, layout density improves 115%, and the space of promotion is limited.
On the other hand, different element heights is inconsistent, how the utilization for rationalizing the height for accounting for plate, so
The limitation of area can really be solved.
Invention content
The purpose of the present invention is to provide a kind of device architectures for the layout density solving the problems, such as unit area.
In order to solve the above technical problems, device architecture of the present invention, including：Bottom device cell, the bottom device cell
Welding is on a printed circuit board；Top layer device cell, the top layer device cell are welded on the bottom device cell.
Preferably, the bottom device cell includes two bottom devices, two longitudinally spaced settings of bottom device
On the printed circuit board；The top layer device cell includes two top layer devices, two top layer device lateral separations
Setting；The both ends of the top layer device are connect with the both ends of the bottom device.
Preferably, it is respectively equipped with bottom device welding end at the both ends of the bottom device, at the both ends of the top layer device
It is respectively equipped with top layer device welding end；The top layer device welding end at single top layer device both ends respectively with two bottoms
The bottom device welding end of device homonymy is welded.
Preferably, spacing >=0.15 millimeter between two bottom device longitudinal directions；The top layer device welding end and institute
State length >=0.2 millimeter of the contact surface of bottom device welding end in a longitudinal direction.
Preferably, the center line of the top layer device welding end in a longitudinal direction exists with the unilateral bottom device welding end
Center line on longitudinal direction overlaps.
Preferably, length >=0.15 millimeter of the bottom device welding end on bottom device length direction；It is described
Length >=0.15 millimeter of the top layer device welding end on top layer device length direction.
Preferably, bottom bottom device welding end, the bottom device cell are equipped in the bottom of the bottom device cell
By fixed in the bottom bottom device welding end and the printed circuit board.
Preferably, it is equipped with bottom top device welding end at the top of the bottom device cell, in the top layer device list
The bottom of member is equipped with top layer bottom device welding end；
The top layer device cell by the top layer bottom device welding end the bottom device cell the bottom
In top device welding end.
Preferably, the bottom device cell is one kind in QFN device or BGA device, and the top layer device cell is
Another kind in QFN device or BGA device.
The present invention also provides a kind of device layouts, including：Device architecture, the device architecture are welded on printed circuit board
On；The device architecture is the device architecture according to claim 1 to 8 any one.
Preferably, the quantity of the device architecture is 15.
Preferably, the device layout further includes chip unit, and the quantity of the chip unit is five, five cores
The laterally homogeneous edge for being arranged in the printed circuit board of blade unit.
Device architecture and device layout of the present invention make full use of the space of height to limit, interior in a limited space, increase cloth
The density of office reduces the area for accounting for plate of device, increases battery capacity and reduces the cabling of plank and account for plate space, effectively reduces
The length of cabling, reduces impedance, promotes the competitiveness of product.
Description of the drawings
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technology description to do one simply to introduce, it should be apparent that, the accompanying drawings in the following description is this hair
Some bright embodiments for those of ordinary skill in the art without having to pay creative labor, can be with
Obtain other attached drawings according to these attached drawings.
Fig. 1 is device architecture schematic diagram of the present invention；
Fig. 2 is one structural schematic diagram of device architecture embodiment of the present invention；
Fig. 3 is two structural schematic diagram one of device architecture embodiment of the present invention；
Fig. 4 is two structural schematic diagram two of device architecture embodiment of the present invention；
Fig. 5 is three structural schematic diagram one of device architecture embodiment of the present invention；
Fig. 6 is three structural schematic diagram two of device architecture embodiment of the present invention；
Fig. 7 is device layout structural schematic diagram of the present invention.
Reference sign in device architecture and device layout attached drawing of the present invention：
1- printed circuit boards
2- bottom device cells
3- top layer device cells
4- device architectures
5- chip units
6- bottom devices
7- bottom device welding ends
8- top layer devices
9- top layer device welding ends
10- bottom bottom device welding ends
11- bottom top device welding ends
12- top layer bottom device welding ends
13- bottom solders
14- top layer solders
Specific implementation mode
The embodiment of the present invention is described below in detail, examples of the embodiments are shown in the accompanying drawings, wherein from beginning to end
Same or similar label indicates same or similar element or element with the same or similar functions.Below with reference to attached
The embodiment of figure description is exemplary, and is only used for explaining the present invention, and is not considered as limiting the invention.
In the description of the present invention, it is to be understood that, term "center", " longitudinal direction ", " transverse direction ", "upper", "lower",
The orientation or positional relationship of the instructions such as "front", "rear", "left", "right", "inner", "outside" is orientation based on ... shown in the drawings or position
Relationship is merely for convenience of description of the present invention and simplification of the description, and not indicating or implying the indicated device or element must have
There is specific orientation, with specific azimuth configuration and operation, therefore is not considered as limiting the invention.In addition, term " the
One ", " second " is used for description purposes only, and is not understood to indicate or imply relative importance or implicitly indicates indicated
The quantity of technical characteristic." first " is defined as a result, the feature of " second " can explicitly or implicitly include one or more
Multiple this feature.In the description of the present invention, unless otherwise indicated, the meaning of " plurality " is two or more.
In the description of the present invention, it should be noted that unless otherwise clearly defined and limited, term " installation ", " phase
Even ", " connection " shall be understood in a broad sense, for example, it may be being fixedly connected, may be a detachable connection, or be integrally connected；It can
Can also be electrical connection to be mechanical connection；It can be directly connected, can also indirectly connected through an intermediary, Ke Yishi
Connection inside two elements.For the ordinary skill in the art, above-mentioned term can be understood at this with concrete condition
Concrete meaning in invention.
Term QFN and BGA are one kind that packaging belongs to chip in the present invention.Specifically, QFN (Quad Flat
No-leadPackage, quad flat non-pin package) it is one of surface mount packages.The full name Ball Grid of BGA
Array (welded ball array encapsulation), it is to make array soldered ball as the ends I/O of circuit and track in the bottom of encapsulation structure base board
Road plate (PCB) mutual connection.The device encapsulated using this technology is a kind of surface mount device.
The present invention is utilization inconsistent by different element heights, that the height for accounting for plate is rationalized, with height
Difference solve the limitation of area.By being welded by bottom device and pcb board circuit, so that the device of lamination, that is,
Top layer and bottom device can play due function.
As shown in Figure 1, device layout structure of the present invention, including：The bottom device cell 2 being welded on printed circuit board 1
And it is welded on the top layer device cell 3 on bottom device cell 2.
Embodiment one
As shown in Fig. 2, device layout structure of the present invention includes two bottom devices 6 and two (bottom devices of top layer device 8
6 and top layer device 8 be chip device).Two bottom devices 6 are longitudinally spaced to be arranged on printed circuit board 1, in bottom device 6
Both ends be respectively equipped with bottom device welding end 7；Two top layer devices 8 are horizontally arranged at interval, and are set respectively at the both ends of top layer device 8
There is top layer device welding end 9.The top layer device welding end 9 at single 8 both ends of the top layer device bottom with two 6 homonymies of bottom device respectively
Device welding end 7 is welded, and the form of superposition is formed.
Wherein, spacing >=0.15 millimeter between two 6 longitudinal directions of bottom device.Top layer device welding end 9 is welded with bottom device
Length >=0.2 millimeter of the contact surface at end 7 in a longitudinal direction.The center line and list of top layer device welding end 9 in a longitudinal direction
The center line of the bottom device welding end 7 of side in a longitudinal direction overlaps.Bottom device welding end 7 is on 6 length direction of bottom device
Length >=0.15 millimeter.Length >=0.15 millimeter of the top layer device welding end 9 on 8 length direction of top layer device.It is such to set
It sets so that between bottom and top layer device and bottom device, the stacked relation between top layer device is more secured, more surely
It is fixed.
Embodiment two
As shown in Figure 3, Figure 4, device layout structure of the present invention includes that bottom device cell 2 (uses QFN devices in the present embodiment
Part), it is equipped with bottom bottom device welding end 10 in the bottom of bottom device cell 2, is printed with bottom solder on the printed circuit board 1
13, bottom device cell 2 (QFN device is used in the present embodiment) passes through the weldering of bottom bottom device welding end 10 and bottom solder 13
It connects, patch is in printed wiring board 1.
It (is used in the present embodiment in bottom device cell 2 (using QFN device in the present embodiment) and top layer device cell 3
BGA device) on opposite face, i.e., in the top of bottom device cell 2 (using QFN device in the present embodiment) and top layer device list
The bottom of member 3 (BGA device is used in the present embodiment) is respectively equipped with bottom top device welding end 11 and top layer bottom device welding end
12, it (is used in the present embodiment in welding bottom device cell 2 (using QFN device in the present embodiment) and top layer device cell 3
BGA device) when, bottom top device welding end 11 is corresponding with top layer bottom device welding end 12, and in bottom top device welding end
Top layer solder 14 is added between 11 and top layer bottom device welding end 12, then is welded, and realizes 3 (this implementation of top layer device cell
BGA device is used in example) patch is on bottom device cell 2 (in the present embodiment use QFN device).In the present embodiment, pass through
The addition of solder increases the stacking stability between top layer and bottom device, and improves firm welding.
Embodiment three
As shown in Figure 5, Figure 6, device layout structure of the present invention includes that bottom device cell 2 (uses BGA devices in the present embodiment
Part), it is equipped with bottom bottom device welding end 10 (being BGA soldered balls in the present embodiment) in the bottom of bottom device cell 2, in printing electricity
Bottom solder 13 is printed on road plate 1, bottom device cell 2 (BGA device is used in the present embodiment) passes through bottom bottom device
Welding of the welding end 10 (being BGA soldered balls in the present embodiment) with bottom solder 13, patch is in printed wiring board 1.
It (is used in the present embodiment in bottom device cell 2 (using BGA device in the present embodiment) and top layer device cell 3
QFN device) on opposite face, i.e., in the top of bottom device cell 2 (using BGA device in the present embodiment) and top layer device list
The bottom of member 3 (QFN device is used in the present embodiment) is respectively equipped with bottom top device welding end 11 and top layer bottom device welding end
12, it (is used in the present embodiment in welding bottom device cell 2 (using BGA device in the present embodiment) and top layer device cell 3
QFN device) when, bottom top device welding end 11 is corresponding with top layer bottom device welding end 12, and in bottom top device welding end
Top layer solder 14 is added between 11 and top layer bottom device welding end 12, then is welded, and realizes 3 (this implementation of top layer device cell
QFN device is used in example) patch is on bottom device cell 2 (in the present embodiment use BGA device).In the present embodiment, pass through
The addition of solder increases the stacking stability between top layer and bottom device, and improves firm welding.
As shown in fig. 7, device layout of the present invention includes multiple device architectures 4 and chip unit 5.Such as Fig. 3 of device architecture 4,
Shown in Fig. 4, including bottom device cell 2 (QFN device is used in the present embodiment), it is equipped with bottom in the bottom of bottom device cell 2
Layer device bottom welding end 10, is printed with bottom solder 13 on the printed circuit board 1, and bottom device cell 2 (uses in the present embodiment
QFN device) by the welding of bottom bottom device welding end 10 and bottom solder 13, patch is in printed wiring board 1.
It (is used in the present embodiment in bottom device cell 2 (using QFN device in the present embodiment) and top layer device cell 3
BGA device) on opposite face, i.e., in the top of bottom device cell 2 (using QFN device in the present embodiment) and top layer device list
The bottom of member 3 (BGA device is used in the present embodiment) is respectively equipped with bottom top device welding end 11 and top layer bottom device welding end
12, it (is used in the present embodiment in welding bottom device cell 2 (using QFN device in the present embodiment) and top layer device cell 3
BGA device) when, bottom top device welding end 11 is corresponding with top layer bottom device welding end 12, and in bottom top device welding end
Top layer solder 14 is added between 11 and top layer bottom device welding end 12, then is welded, and realizes 3 (this implementation of top layer device cell
BGA device is used in example) patch is on bottom device cell 2 (in the present embodiment use QFN device).In the present embodiment, pass through
The addition of solder increases the stacking stability between top layer and bottom device, and improves firm welding.
The quantity of device architecture 4 is 15, and the quantity of chip unit 5 is five.Device architecture 4 and chip unit 5 are equal
It is even to be arranged on printed circuit board 1, wherein the laterally homogeneous edge for being arranged in printed circuit board 1 of five chip units 5.Using this
The layout type of sample can arrange 65 devices, compared to current 40, have more 25.
Although the invention has been described by way of example and in terms of the preferred embodiments, but it is not for limiting the present invention, any this field
Technical staff without departing from the spirit and scope of the present invention, may be by the methods and technical content of the disclosure above to this hair
Bright technical solution makes possible variation and modification, therefore, every content without departing from technical solution of the present invention, and according to the present invention
Technical spirit to any simple modifications, equivalents, and modifications made by above example, belong to technical solution of the present invention
Protection domain.
Claims (12)
1. device architecture, which is characterized in that including：
Bottom device cell, the bottom device cell welding is on a printed circuit board；
Top layer device cell, the top layer device cell are welded on the bottom device cell.
2. device architecture according to claim 1, which is characterized in that the bottom device cell includes two bottom devices
Part, two bottom devices are longitudinally spaced to be arranged on the printed circuit board；
The top layer device cell includes two top layer devices, and two top layer devices are horizontally arranged at interval；
The both ends of the top layer device are connect with the both ends of the bottom device.
3. device architecture according to claim 2, which is characterized in that be respectively equipped with bottom at the both ends of the bottom device
Device welding end is respectively equipped with top layer device welding end at the both ends of the top layer device；
The top layer device welding end at the single top layer device both ends bottom with two bottom device homonymies respectively
Layer device welding end is welded.
4. device architecture according to claim 3, which is characterized in that spacing between two bottom device longitudinal directions >=
0.15 millimeter；Length >=0.2 of the contact surface of the top layer device welding end and the bottom device welding end in a longitudinal direction is in the least
Rice.
5. device architecture according to claim 3, which is characterized in that the top layer device welding end in a longitudinal direction in
Heart line is overlapped with the center line of the unilateral bottom device welding end in a longitudinal direction.
6. device architecture according to claim 3, which is characterized in that the bottom device welding end is long in the bottom device
Spend length >=0.15 millimeter on direction；Length >=0.15 of the top layer device welding end on top layer device length direction
Millimeter.
7. device architecture according to claim 1, which is characterized in that be equipped with bottom in the bottom of the bottom device cell
Bottom device welding end, the bottom device cell pass through fixed in the bottom bottom device welding end and the printed circuit board.
8. device architecture according to claim 7, which is characterized in that be equipped with bottom at the top of the bottom device cell
Top device welding end is equipped with top layer bottom device welding end in the bottom of the top layer device cell；
The top layer device cell by the top layer bottom device welding end the bottom device cell the bottom device
In the welding end of top.
9. device architecture according to claim 7 or 8, which is characterized in that the bottom device cell be QFN device or
One kind in BGA device, the top layer device cell are the another kind in QFN device or BGA device.
10. device layout, which is characterized in that including：
Device architecture, the device architecture welding is on a printed circuit board；
The device architecture is the device architecture according to claim 1 to 8 any one.
11. device layout according to claim 10, which is characterized in that the quantity of the device architecture is 15.
12. device layout according to claim 11, which is characterized in that the device layout further includes chip unit, institute
The quantity for stating chip unit is five, the laterally homogeneous edge for being arranged in the printed circuit board of five chip units.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810027111.XA CN108323009A (en) | 2018-01-11 | 2018-01-11 | Device architecture and device layout |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810027111.XA CN108323009A (en) | 2018-01-11 | 2018-01-11 | Device architecture and device layout |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN108323009A true CN108323009A (en) | 2018-07-24 |
Family
ID=62894015
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810027111.XA Pending CN108323009A (en) | 2018-01-11 | 2018-01-11 | Device architecture and device layout |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN108323009A (en) |
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| US20070145575A1 (en) * | 2004-01-27 | 2007-06-28 | Masato Mori | Circuit board and method for mounting chip component |
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| CN104332444A (en) * | 2013-06-28 | 2015-02-04 | 英特尔公司 | Solution to deal with die warpage during 3d die-to-die stacking |
| CN204144239U (en) * | 2014-09-01 | 2015-02-04 | 无锡华测电子系统有限公司 | The stack distribution structure of the high-power bare chip of a kind of homalographic |
| CN105789163A (en) * | 2016-03-23 | 2016-07-20 | 宜确半导体（苏州）有限公司 | Radio frequency front-end chip integration module and radio frequency front-end chip integration method |
| CN106409702A (en) * | 2016-11-22 | 2017-02-15 | 中国科学院微电子研究所 | Multi-chip stacked package structure and manufacture method thereof |
-
2018
- 2018-01-11 CN CN201810027111.XA patent/CN108323009A/en active Pending
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070145575A1 (en) * | 2004-01-27 | 2007-06-28 | Masato Mori | Circuit board and method for mounting chip component |
| CN1957470A (en) * | 2004-05-06 | 2007-05-02 | 皇家飞利浦电子股份有限公司 | A method of assembly and assembly thus made |
| CN101128926A (en) * | 2005-02-24 | 2008-02-20 | 艾格瑞系统有限公司 | Structure and method for fabricating flip chip devices |
| CN104332444A (en) * | 2013-06-28 | 2015-02-04 | 英特尔公司 | Solution to deal with die warpage during 3d die-to-die stacking |
| CN103887275A (en) * | 2014-01-24 | 2014-06-25 | 中国科学院微电子研究所 | Structure with realization of 3D interlayer vertical interconnection by using flexible substrate and manufacturing method thereof |
| CN204144239U (en) * | 2014-09-01 | 2015-02-04 | 无锡华测电子系统有限公司 | The stack distribution structure of the high-power bare chip of a kind of homalographic |
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| CN106409702A (en) * | 2016-11-22 | 2017-02-15 | 中国科学院微电子研究所 | Multi-chip stacked package structure and manufacture method thereof |
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